Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port (“AGP”) bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table (“GART table”) is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: The present invention provides a method for operating a core logic unit including an embedded graphics controller. This method facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a method for operating a core logic unit with an embedded graphics controller. This method includes receiving processor communications from a processor through a processor interface in the core logic unit, and transferring the processor communications through a switch to a graphics controller located in the core logic unit. It also includes receiving memory communications from a system memory through a memory interface in the core logic unit, and transferring the memory communications through the switch to the graphics controller. These processor communications and graphics communications are used to perform graphics computations in the graphics controller.

Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Abstract: A method and apparatus for managing memory used by a device driver in an operating system. The method comprises: (i) configuring a chipset to set up a mapping table for memory address translation, (ii) allocating a device memory in response to a request by the device driver, and (iii) mapping non-contiguous system memory to contiguous device memory using the mapping table.

Abstract: An apparatus and method for processing ultrasound data is provided. The apparatus includes an interface operatively connected to a memory, a programmable single instruction multiple data processor (or two symmetric processors), a source of acoustic data (such as a data bus) and a system bus. The memory stores data from the processor, ultrasound data from the source, and data from the system bus. The processor has direct access to the memory. Alternatively, the system bus has direct access to the memory. The interface device translates logically addressed ultrasound data to physically addressed ultrasound data for storage in a memory. The translation is the same for data from both the processor and the source for at least a portion of a range of addresses. The memory stores both ultrasound data and various of: beamformer control data, instruction data for the processor, display text plane information, control plane data, and a table of memory addresses. One peripheral connects to the ultrasound apparatus.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.

Abstract: A method for generalized flipping of pixmaps and other arrays of image data in a software display device interface for computer generated graphics applications. The display device interface enables application programs to create flipping surface structures representing on and offscreen pixmaps, textures, sprites, overlays, etc. The display device interface includes a flip function to control the flipping of these flipping structures. It also includes functions to synchronize access to the surfaces represented by the flipping structure. Applications and other processes can use these access synchronization functions to manipulate surfaces represented by the flipping structure without conflicting with a client's use of the surface. Clients other than the display controller can act as clients of the flipping operation. For instance, flipping structures can be used to implement video texture mapping, where the client of a texture flipping structure is a 3D rendering system.