Abstract: A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.

Abstract: This invention provides an image display apparatus for displaying data stored in a random access memory (RAM) such as LCD, more specifically a display driver achieving easy and flexible display control such as scroll in a display screen without increasing load on CPU and an image display apparatus including the same.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.

Abstract: A semiconductor memory device of a high degree of freedom in column and a graphics display system using the semiconductor memory device as a mapping memory are provided. The semiconductor memory device according to the present invention is comprised of a plurality of memory arrays and each memory array is comprised of a plurality of memory cell groups. A plurality memory cell groups in each memory array are independently selected according to the information of a separate column address. Column decoders select the column of a corresponding memory array in response to common column addresses and first or second separate column addresses. The first or the second separate column addresses select one memory cell group among memory cell groups in each memory array. The common column addresses select predetermined numbers of columns in each memory cell group.

Abstract: A method for transferring data between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, a DMA function is optimized to fetch data from an external memory representing a RGB color space and to provide the data for a JPEG conversion while performing YCrCb color space conversion on the fly. More specifically, data is transferred from the RGB color space memory to a DCT block-computation engine adapted to process a YCrCb color space memory. The method includes providing the data for an RGB display screen area as a tile array having C columns and R rows of tiles, where one tile corresponds to sufficient RGB data for a DCT of at least one of a Cr data array and a Cb data array. Data is fetched at addresses in the tile array by accessing the data one tile at a time, and both the row within each tile and the tile within the tile array are tracked.

Abstract: In data on which TrCH 1 and TrCH 2 is multiplexed, data 403 of TrCH 1 is written in from row 0 (401-1) of column 0 (402-1) to row 13 (401-14) of column 4 (402-5) from left to right of data write block 400 for second interleaving. Then, data 404 of TrCH 2 is written from row 13 (401-14) of column 5 (402-6) to row 14 (401-15) of column 29 (402-30) through row 14 (401-15) of column 0 (402-1). The written data is read from data write block 400 in the predetermined order in a direction, upwardly or downwardly, different for each column to map on each slot. It is thereby possible to demodulate the data accurately even when an interference component overlaps a fragment of data of a channel.

Abstract: A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

Abstract: An address generator (FIG. 6) of a display controller (16) includes an adder (62) that repetitively adds an image-row-offset value to the address generator's address output so that data sequentially fetched from a refresh memory (18) to refresh a display (20) properly represent the image data even though the display scanning orthogonal to the image data's sequence in the refresh memory. As the data are fetched, an omega network (90) re-orders the bits within the fetched data words in accordance with the current display scan so that the display will receive proper data even though each location contains data for a plurality of pixels in an orthogonally oriented image row.

Abstract: Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel data from the first memory unit and the order of converting the parallel data into the serial data.

Abstract: An image data processing method and system receives image data from a burst memory buffer and provides output image data to a vertical filter for filtering. The method determines whether a new frame of input image data has been received, said frame of data having a plurality of blocks, each block having a plurality of rows and columns. A vertical input buffer uses a read pointer, an oldest unused data pointer, and a write pointer to keep track of the data that is being read and stored. Data is read and stored into said vertical input buffer by determining the minimum offset for the block, reading a row of input image data from the burst memory buffer and skipping the row depending on the minimum offset until minimum offset reached, and storing the row of input image data in said vertical input buffer for processing by the vertical filter until the buffer is full. If the entire frame has been processed then the pointers are all reset.

Abstract: A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or column of data accessed by a burst frees up instruction bandwidth of a video controller. In particular, it is assured that each row and column of data associated with the data block has at least one sequential pair of data words associated with it. By assuring at least one sequential pair of data words, it is possible to issue a burst request for a minimum of two words of data with each row access, or column access of the video controller.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: An orthogonal memory is described that provides an improved method for converting image data into a bit plane format suitable for image compression operations, using a custom dual port memory. The memory comprises a matrix of memory cells that are addressable in orthogonal directions. Upon receipt of image information for storage, the image information is stored in the memory by storing each data word of the image information in a row of the matrix. Individual bit planes of the image information may be easily retrieved from the memory by retrieving individual columns of bits from the corresponding columns of the matrix, thus providing a highly efficient method for storing and accessing image information used to create bit planes.

Abstract: On storing two-dimensional arrangement data into a memory (1) having banks, 2n in number, each of which is individually assigned with a bank number B and includes row addresses identified by row address numbers A, an address converter (3) calculates, in response to a coordinate (X, Y) representing a particular data element of the data elements of the two-dimensional arrangement data, the bank number B of a particular bank of the banks where the particular data element is to be memorized. The bank number B is given by: B={Y×(2n×m+k)+X}mod 2n, where m is a positive integer, where k is a positive integer smaller than 2n and other than 1, and where mod is an operator for calculating a remainder. The address converter also calculates the row address number A of a particular address of the row addresses of the particular bank where the particular data element is to be memorized.

Abstract: A method and apparatus for image processing provides a memory having a plurality of individual parallel buffers constructed from random access memories (RAMs) for storing data related to a group of image pixels. The buffers each store a parallel, identical version of the image data so that an image processor can access data related to a given pixel in the overall data from each buffer simultaneously. An address expander for the buffer rows and buffer columns is used to convert a row and column address of a selected “central” pixel into a plurality of related pixel data addresses offset at predetermined distances from the selected pixel data's address. In this manner, the address expanders enable a group of related pixels, each in a different parallel buffer, to be accessed simultaneously, without requiring the processor to be interconnected with all of the buffers. This substantially reduces the complexity of processor interconnection design, while substantially enhancing processor speed.

Abstract: A volume rendering process is disclosed. Data including a plurality of voxels are recorded. Each voxel includes an opacity-adjusted value representative of a value of a parameter at a location within the volume adjusted by applying an opacity curve to the value. A computer is used to process such data. The process includes partitioning the plurality of voxels among a plurality of slices. Each slice corresponds to a respective region of the volume. For each slice, the process apportions the plurality of voxels associated with that slice among a plurality of cells associated with that slice. Each cell corresponds to a respective sub-region of the region associated with that slice. For each cell, the process determines that the cell is nontransparent if more than a predetermined number of the voxels associated with that cell have an opacity-adjusted value greater than a predetermined value. Otherwise the cell is determined to be transparent.

Abstract: A memory chip having fast access to pixel data of graphics image to be stored therein is described. The memory chip consists of data inputs and outputs (I/Os) divided into a plurality of blocks; memory arrays for storing data received from or sent to the I/Os, which are divided into the same number of blocks as the I/Os; and address input terminals for specifying addresses to be accessed by respective blocks of the memory arrays, which are divided into the same number of blocks as the memory arrays. The memory chip and the method for storing data enable reading data in a vertical line, in a diagonal line, and the like, at the same access speed as data in a horizontal line is being read. Furthermore, power consumption of the chip is significantly reduced, and the wiring arrangement of the I/Os is greatly simplified.

Abstract: An address generator (FIG. 6) of a display controller (16) includes an adder (62) that repetitively adds an image-row-offset value to the address generator's address output so that data sequentially fetched from a refresh memory (18) to refresh a display (20) properly represent the image data even though the display scanning orthogonal to the image data's sequence in the refresh memory. As the data are fetched, an omega network (90) re-orders the bits within the fetched data words in accordance with the current display scan so that the display will receive proper data even though each location contains data for a plurality of pixels in an orthogonally oriented image row.

Abstract: A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel data of the frame buffer to a display device using a set of controller addresses. The two sets of addresses are not necessarily the same. In fact, numerous advantages could be had from manipulating those two sets of addresses resulting in image rotation operations for the display device.