Memory Addresses Arranged In Matrix Row And Column Addresses) Patents (Class 345/571)
  • Patent number: 9179156
    Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Animesh Mishra, Naveen Doddapuneni, Jose M. Rodriguez
  • Patent number: 9020044
    Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: April 28, 2015
    Assignee: ATI Technologies ULC
    Inventors: Lei Zhang, Benedict C. Chien, Edward A. Harold
  • Patent number: 9009005
    Abstract: The lighting control apparatus has a memory unit, an operation input unit and a control unit. The memory unit stores an outer frame and addresses of luminaires and operating devices. The operation input unit inputs to designate a position where a small area is provided in a predetermined area on a layout drawing. The control unit provides, based on the outer frame and the addresses, a layout drawing that illustrates positions where luminaires and operating devices are arranged in the predetermined range within the outer frame. The control unit determines the luminaire and the operating device arranged in the small area. The control unit gives an operation right of the luminaire arranged in the small area to the operating device arranged in the same small area.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 14, 2015
    Assignee: KYOCERA Corporation
    Inventors: Nobuo Kuchiki, Takashi Baba, Mayumi Kono
  • Patent number: 8823406
    Abstract: Systems and methods for simultaneous optical testing of a plurality of devices under test. These systems and methods may include the use of an optical probe assembly that includes a power supply structure that is configured to provide an electric current to a plurality of devices under test (DUTs) and an optical collection structure that is configured to simultaneously collect electromagnetic radiation that may be produced by the plurality of DUTs and to provide the collected electromagnetic radiation to one or more optical detection devices. The systems and methods also may include the use of the optical probe assembly in an optical probe system to evaluate one or more performance parameters of each of the plurality of DUTs.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: September 2, 2014
    Assignee: Cascade Micotech, Inc.
    Inventors: Bryan Bolt, Eric W. Strid, Kazuki Negishi, Steve Harris
  • Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Patent number: 8576244
    Abstract: Provided is a video signal generation apparatus and method that may minimize crosstalk between a luminance signal and color difference signals. The video signal generation apparatus may generate the luminance signal using a nonlinear Y signal and then generate color difference signals using a nonlinear XYZ signal to maximize a de-correlation characteristic between the luminance signal and the color difference signals.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seo Young Choi, Ho Young Lee, Yun-Tae Kim, Du-Sik Park, Ji Young Hong
  • Patent number: 8452122
    Abstract: An image processing apparatus includes: an assumed deteriorated image pixel value computing unit configured to calculate a pixel value of an assumed deteriorated image, wherein deterioration of a target image configured of multiple channels is assumed, for each of the channels as an assumed deteriorated image pixel value; a pseudo target image pixel value computing unit configured to calculate, regarding a pixel of interest that is a pixel of the target image corresponding to the assumed deteriorated image, a pixel value estimated for each of the channels as a pseudo target image pixel value for each of the channels based on the pixel values of the pixel of interest, and pixels adjacent thereto; and a restored image creating unit configured to create a restored image restored from the target image based on the calculated assumed deteriorated image pixel value and the calculated pseudo target image pixel value.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: May 28, 2013
    Assignee: Sony Corporartion
    Inventors: Yasunobu Hitomi, Tomoo Mitsunaga
  • Publication number: 20130120419
    Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Inventors: Animesh Mishra, Naveen Doddapuneni, Jose M. Rodriguez
  • Patent number: 8427456
    Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: April 23, 2013
    Assignee: Japan Display Central Inc.
    Inventor: Kimio Anai
  • Patent number: 8341328
    Abstract: A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: December 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jon Skull
  • Patent number: 8331446
    Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.
    Type: Grant
    Filed: August 31, 2008
    Date of Patent: December 11, 2012
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Erik M. Schlanger, Brendan D. Donahe, Eric Swartzendruber, Eric J. DeVolder
  • Patent number: 8294697
    Abstract: Provided is a register circuit including a timing circuit controlled by an external control signal to receive an external timing signal and then to transmit a first timing signal and a second timing signal, wherein the first timing signal and the second timing signal have phases inverse to each other; two pass gates controlled by the first timing signal and the second timing signal to receive starting pulse signals and then transmit the pulse signals as one of the pass gates turns on; a signal output unit receiving the pulse signals to transmit an output signal; and two switches controlled by the external control signal to receive and to transmit the output signal as one of the switches turns on.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: October 23, 2012
    Assignee: Chimei Innolux Corporation
    Inventor: Dong Qian
  • Patent number: 8295334
    Abstract: A digital audio signal, a channel clock, and a bit clock are transmitted to the receiving apparatus via a pair of signal lines. The digital audio signal is input to a D/A converter via a first comparator. The channel clock and the bit clock are received, separated with first and second separation circuits, and input to the D/A converter via the second and third comparators. A reference electrical potential of the second comparator is corrected such that it becomes half or approximately half of an amplitude of the channel clock depending on an electrical potential change of the output of a second differential signal receiving circuit. A system clock is generated based on the bit clock. The digital audio signal is converted into the analog audio signal based on the channel clock, the bit clock, and the system clock, and then the converted analog audio signal is output.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Component Limited
    Inventor: Heiichi Sugino
  • Publication number: 20120262469
    Abstract: Systems and methods for realizing display drivers, especially OLED drivers having a high efficiency. With a single pass, using an algorithm based on simple equations based on gathered maximum display data, the driver can split an image to be displayed into multiple planes and tiles thus balancing peak current consumption. Furthermore the driver is able to optimize drive time periods in regard of many parameters.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 18, 2012
    Inventor: Stephen Allen
  • Patent number: 8269786
    Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: September 18, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: ChunJie Yu, Wentao Ye, Tsuyoshi Morimoto, Hirofumi Odaguchi
  • Patent number: 8266380
    Abstract: The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsuaki Hino
  • Patent number: 8264496
    Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics S.A.
    Inventors: Xavier Cauchy, Bruno Thery, Anthony Philippe, Mark Petrus Vos
  • Patent number: 8233003
    Abstract: An image processing device that supplies image data to a driver section of a display panel includes an encoding section that encodes image data on a block-by-block basis to generate encoded data, the image data corresponding to one scan line of an input image, the image data being divided into a plurality of blocks, a memory that stores the encoded data from the encoding section, and a decoding section that decodes the encoded data from the memory on a block-by-block basis to generate decoded data, the decoded data from the decoding section being supplied to the driver section.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: July 31, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Obinata
  • Patent number: 8000545
    Abstract: A method for accessing image data and a method for accessing YUV420 image data are disclosed. The method for accessing image data uses two different approaches to a buffer for accessing the JPEG image data, so that the method can achieve instant JPEG image data compression with only one buffer.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 16, 2011
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Jiann-Jong Tsai
  • Patent number: 7995068
    Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: August 9, 2011
    Inventors: Thomas E. Willis, Steven L. Midford
  • Patent number: 7872657
    Abstract: Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: January 18, 2011
    Assignee: NVIDIA Corporation
    Inventors: John H. Edmondson, James M. Van Dyke
  • Patent number: 7859541
    Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 28, 2010
    Assignee: NVIDIA Corporation
    Inventors: John S. Montrym, David B. Glasco, Steven E. Molnar
  • Patent number: 7839424
    Abstract: A system is provided for scaling image data comprising a Direct Memory Access (DMA) engine adapted to read the image data from a horizontal pixel strip in a column-by-column format, a scaling block adapted to scale the image data read by the read DMA engine into scaled column output data, and a buffer memory for storing the scaled column output data for the horizontal pixel strip. A method is also provided for scaling an image comprising reading pixel values from a pixel strip in a column-by-column manner across the pixel strip and scaling the pixel values for each column to produce scaled column output data. The scaled column output data for a plurality of columns is then read and the scaled column output data is scaled from the plurality of columns to produce scaled row output data for a row of pixels.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: November 23, 2010
    Assignee: Marvell International Ltd.
    Inventors: Gordon R. Clark, Douglas G. Keithley
  • Patent number: 7805561
    Abstract: A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: September 28, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Jon Skull
  • Patent number: 7750916
    Abstract: A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 6, 2010
    Assignee: Aspex Technology Limited
    Inventor: Martin Whitaker
  • Patent number: 7671865
    Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Thomas E. Willis, Steven L. Midford
  • Publication number: 20090295817
    Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 3, 2009
    Inventors: Chunjie Yu, Wentao Ye, Tsuyoshi Morimoto, Hirofumi Odaguchi
  • Patent number: 7593016
    Abstract: In an image processing system, high density storage of bit-plane data is provided in a secondary or page memory as well as high bandwidth access to the data by an image processor. The page memory provides storage of data not currently being processed. The page memory may also be part of a system that provides input and output of image data to and from the image processor. The image data may be handled outside the image processor in a packed pixel form and be converted between that form and bit-line form which the page memory stores during input and output. The bit-line data may be gathered into bit-planes for use by the image processor during movement of data from the page memory to the processing logic.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 22, 2009
    Assignee: Teranex Systems, Inc
    Inventor: Woodrow L. Meeker
  • Patent number: 7580042
    Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: August 25, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Chung, Kil-Whan Lee
  • Patent number: 7564462
    Abstract: System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: July 21, 2009
    Assignee: Teranex Systems, Inc.
    Inventors: Woodrow L. Meeker, Clara Ka Wah Sung, Carl Alan Morris
  • Patent number: 7561168
    Abstract: Performing color management of color image data using a device transform by generating an identifier key based on contents of a color measurement profile for a color device, the color measurement profile containing measurement data corresponding to the color device, determining if a device transform corresponding to the identifier key is present in a device transform cache disposed in a persistent memory, loading, in the case that it is determined that a device transform corresponding to the identifier key is present in the device transform cache, the device transform into a program-accessible transient memory, generating, in the case that it is determined that a device transform corresponding to the identifier key is not present in the device transform cache, a device transform based on the measurement data in the color measurement profile, and storing the generated device transform in the device transform cache in correspondence with the identifier key, and transforming the color image data based on the dev
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: July 14, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Todd D. Newman, John S. Haikin
  • Patent number: 7557801
    Abstract: In a display device and a control circuit thereof, mounting of a high-capacity memory device for synchronizing the reception cycle of a digital image signal with a drive cycle of the display device or for translating a format of a received digital image signal into a format to be displayed by the display device is avoided, while transmission volume of digital image signals to the display device is reduced to achieve downsizing and power saving. In a display device having a plurality of memory circuits in a pixel, a digital image signal is written into a memory circuit in the pixel using a decoder, whereby digital image data that is received without the use of a high-capacity memory device can be displayed even when the digital image signal is received in an arbitrary cycle.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: July 7, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tadafumi Ozaki
  • Patent number: 7545382
    Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: June 9, 2009
    Assignee: NVIDIA Corporation
    Inventors: John S. Montrym, David B. Glasco, Steven E. Molnar
  • Patent number: 7515159
    Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Tetsuo Kawano
  • Patent number: 7490190
    Abstract: A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Jon Skull
  • Patent number: 7425961
    Abstract: To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buffer 14 for storing an address and data in a memory writing is provided. When a display reading and a memory writing occurs simultaneously and row addresses of the memory writing and the display reading agree with each other, the memory writing is executed and also read data from addresses except a write address together with write data into the write address are used as data of the display reading. Also, when the row addresses of the memory writing and the display reading are different from each other, the write address and data are stored in the reservation buffer and also the display reading is executed. The similar mediation is applied in executing the reserved writing.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: September 16, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Akihito Tsukamoto
  • Patent number: 7187372
    Abstract: An image display system comprises: a transmission device (PC) 10, for transmitting image data upon receiving a drawing command from an OS or an application; and a receiving monitor 40, for displaying, on a high-resolution panel 41, image data received via a monitor cable 39, wherein the transmission device 10 includes a drawing command analysis device 20, for detecting an area on a screen wherein the content is changed by the drawing command, and for employing the detected area to calculate an area to be transmitted, and a graphics card 12, for transmitting a packet that includes the calculated area to be transmitted, and control data provided as header data for the area to be transmitted, and wherein the receiving monitor 40 includes a packet reception device 50, for analyzing the header data in the received packet and for, based on the header data, rendering image data in an internally provided frame memory.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: March 6, 2007
    Assignee: AU Optronics Corporation
    Inventors: Takenori Kohda, Sanehiro Furuichi, Moriyoshi Ohara, Kei Kawase
  • Patent number: 7154490
    Abstract: A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state setting register in which mounting state setting data showing a mounting state of the display driver is set, a RAM that stores display data, a row scanning flag generation circuit that generates a row scanning flag showing a scanning direction of row addresses based on the mounting state setting data, a row address decoder that decodes row addresses in accordance with the scanning direction designated by the row scanning flag, a column address decoder that decodes column addresses, a display address decoder that decodes display addresses, and a driving circuit that drives a display section based on display data read from the RAM in accordance with a decoding result of the display address decoder.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Tsuyoshi Yoneyama
  • Patent number: 7102646
    Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: September 5, 2006
    Assignee: NVIDIA U.S. Investment Company
    Inventors: Oren Rubinstein, Ming Benjamin Zhu
  • Patent number: 7066611
    Abstract: A beam projector is aligned with a linear array of receptors. An alignment receptor is at each end of the linear array of receptors. A beam is projected from the projector. The beam is swept until the alignment receptors sense the beam. A signal is transmitted upon each of the alignment receptors sensing the beam. The position of the beam projector is recorded in response to the transmitted signals. The alignment position of the beam projector, to align with the linear array of receptors, is computed from the recorded positions. The beam projector is aligned with the linear array of receptors according to the alignment position.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: June 27, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Daryl E. Anderson
  • Patent number: 7035991
    Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: April 25, 2006
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Akio Ohba
  • Patent number: 6992673
    Abstract: To provide a drawing device with which drawing speed can be increased without escalation of price of it. A drawing device is established as a GPU on an entertainment device to perform the drawing to a frame buffer in terms of one of different interleaved patterns. Each interleaved pattern is specified by a combination of pixel segments in the frame buffer. The GPU identifies the shape of a figure to be drawn and selects the interleaved pattern that fits for the selected shape of the figure. The pixel segments specified in the frame buffer are not overlapped with other pixel segments in the same interleaved pattern regardless of which interleaved pattern is selected.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: January 31, 2006
    Assignee: Sony Computer Entertainment, Inc.
    Inventors: Masaaki Oka, Toshiyuki Hiroi
  • Patent number: 6989825
    Abstract: In order to reduce the power consumed by the circuit when the image data is transferred to a memory in a display means, a write region detecting means 8 is provided to detect the address region in the graphics memory 2 accessed for writing by the image data writing means 1, and only such data that is within the region including the addresses accessed by the writing means 1 is transferred to the memory 5 in the display means 4. The region including the accessed addresses may for example a rectangular region of from the minimum vertical direction address to the maximum vertical direction address Y among the accessed addresses, and from the minimum horizontal direction address to the maximum horizontal direction address among the accessed addresses.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: January 24, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Naito, Shuji Sotoda, Takuji Kurashita, Kazuhiro Sugiyama
  • Patent number: 6985155
    Abstract: A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a plurality of memory units each having two memory cells adjacent to each other in the same row, one flag cell, and two transfer gates for transferring flag data of the flag cell to the flag cells of the memory units adjacent in a row direction and a column direction in accordance with the stored data of each memory cell and including a region growing circuit for writing correlation data as results of operation of correlation of adjacent pixels into all memory cells, starting the region growing processing from a designated position (address) to extract an object, and outputting the same to an image combining unit.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: January 10, 2006
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Akihiro Okumura
  • Patent number: 6975324
    Abstract: A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: December 13, 2005
    Assignee: Broadcom Corporation
    Inventors: Ramanujan K. Valmiki, Sandeep Bhatia
  • Patent number: 6937248
    Abstract: A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) is provided on the substrate interspersed with the pixel drive circuitry (16), wherein memory address circuitry (24,26,28,30) is provided enabling data to be written to each memory cell and enabling data to be read from each cell (22), independently of the signal data. Each memory cell (22) is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: August 30, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Martin J. Edwards, John R. A. Ayres
  • Patent number: 6912638
    Abstract: A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bus. Also, the controller can include a third controller to provide I/O functionality to an external device. The second processor processes the stored data in either a row or column configuration. A fixed-length instruction word can be decoded into two instructions, an operation instruction and an I/O instruction, and can be used to process the data. The I/O instruction can be disposed in an unused bit field of the operation instruction.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 28, 2005
    Assignee: Zoran Corporation
    Inventors: Timothy M. Hellman, Neil B. Epstein, Steve J. Pratt, Fred W. Andree, Karl M. Marks, Joerg Landmann, James W. Brissette
  • Patent number: 6903744
    Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: June 7, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Darel N Emmot
  • Patent number: 6900812
    Abstract: A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: May 31, 2005
    Assignee: ATI International SRL
    Inventor: Stephen L. Morein
  • Patent number: RE39529
    Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Koyo Katsura, Shinichi Kojima, Noriyuki Kurakami