Abstract: An address generator (FIG. 6) of a display controller (16) includes an adder (62) that repetitively adds an image-row-offset value to the address generator's address output so that data sequentially fetched from a refresh memory (18) to refresh a display (20) properly represent the image data even though the display scanning orthogonal to the image data's sequence in the refresh memory. As the data are fetched, an omega network (90) re-orders the bits within the fetched data words in accordance with the current display scan so that the display will receive proper data even though each location contains data for a plurality of pixels in an orthogonally oriented image row.

Abstract: Texture data containing pixel data indicating the color of a plurality of pixels arrayed in matrix fashion are stored in a texture buffer of a DRAM, and the multiple pixel data stored in the texture buffer is simultaneously accessed using a two-dimensional address (U, V) corresponding to the two-dimensional array of the plurality of pixels. The texture buffer stipulates unit blocks containing multiple pixel data to be simultaneously accessed, and stores a plurality of unit blocks making up texture data so as to be continuously positioned within a one-dimensional address space. Accordingly, the storage area of the texture buffer can be used efficiently, and further, simultaneous processing of image data of multiple pixels can be realized.

Abstract: Texture data which is two-dimensional image data indicating color data of multiple pixels positioned in a matrix form is stored in a texture buffer of a DRAM, a texture engine circuit combines the bit data making up the U address of a two-dimensional address (U, V) represented by n bits (wherein n is an integer of 1 or greater) and the bit data making up the V address of the two-dimensional address (U, V) represented by m bits (wherein m is an integer of 1 or greater), thereby generating an (n+m)-bit one-dimensional address, and the generated one-dimensional address is used to access the storage circuit. Accordingly, the storage area of the texture buffer can be used efficiently with a small circuit configuration.

Abstract: A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.

Abstract: A two-dimensional data processing apparatus, a two-dimensional data processing method, and a computer readable recording medium recorded with a two-dimensional data processing program, capable of simultaneously establishing manipulative capability and data reusability, by rendering various totalization to be readily executed for tabular format data as it is.