With Dc Level Control Patents (Class 348/257)
  • Patent number: 10200558
    Abstract: An object of the present invention is to detect the home position with a high accuracy without being affected by temperature. The present invention is an image reading apparatus having a reading portion, and the apparatus includes: an acquisition unit configured to acquire first data obtained by the reading portion reading a main scanning line in a state where a light source of the reading portion is turned on in a first light quantity, and second data obtained by the reading portion reading the main scanning line in a state where the light source of the reading portion is turned on in a second light quantity smaller than the first light quantity; a generation unit configured to generate difference data by subtracting the value of the second data from the value of the first data; and a determination unit configured to determine whether a mark arranged at a position corresponding to a home position of the reading portion has been detected on the main scanning line based on the difference data.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: February 5, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Noriko Takeuchi
  • Patent number: 9967494
    Abstract: A photoelectric conversion apparatus includes a pixel. The pixel includes a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor. The photoelectric conversion apparatus includes a control line, a voltage control unit, and a current source. The control line is electrically connected to a source of the amplification transistor. The voltage control unit controls the voltage of the control line. The current source outputs a reference current. A path of a current from the amplification transistor is separated from a path of the reference current. The photoelectric conversion apparatus includes a comparison unit configured to compare the current from the amplification transistor with the reference current. During a period in which a transistor connected to the gate of the amplification transistor is in a conductive state, the selection transistor is in a non-conductive state.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 8, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hirofumi Totsuka, Daisuke Yoshida, Yasushi Matsuno, Takashi Muto, Toru Koizumi
  • Patent number: 9451189
    Abstract: There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ?? modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ?? modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ?? modulator.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 20, 2016
    Assignee: Sony Corporation
    Inventors: Hayato Wakabayashi, Yosuke Ueno
  • Patent number: 9036040
    Abstract: An image processing system may process an image of indicia positioned behind a reflective surface. The indicia may be a vehicle identification number and the reflective surface may be a windshield of a vehicle. The image processing system may receive an initial image of the indicia positioned behind a reflective surface and process the initial image to produce a resulting image. In processing the initial image, the image processing system may identify an interest region of the initial image, where the interest region identifies a portion of the initial image affected by glare caused by the reflective surface, texturize the interest region to account for the glare, and remove a defocusing effect from the initial image to account for blur, reflection, or both, caused by the reflective surface. Then, the image processing system may extract data, such as the vehicle identification number, from the resulting image.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 19, 2015
    Assignee: United Services Automobile Association (USAA)
    Inventor: Amanda Shannon Danko
  • Patent number: 8953041
    Abstract: An Engineer's View (EV) wireless video system for powered and unpowered model railroad engines is disclosed. The invention uses commercially available wireless spy cameras, powered by a custom power supply circuit which is compatible with either DC or DCC track systems. The present invention is compatible with all commercial model railroad gauge diesel engines including HO and N Gauge or may be factory installed. The EV system demonstrates a remarkably stable and realistic image of a model railroad layout. Moreover, the present invention may also provide a stable source of power to the engine where stalling could occur at points of track defects.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 10, 2015
    Inventors: Richard Johnson Bartlett, Sr., William Travis Bartlett
  • Patent number: 8643073
    Abstract: A plurality of pixels PX include effective pixels and optical black pixels. Signal lines VL are provided corresponding to each column of the pixels PX and supplied with output signals of the pixels PX of the corresponding column. Clip transistors CL are provided corresponding to the respective signal lines VL and limit a potential of the corresponding vertical signal lines VL based on a gate potential. At least in a predetermined operating mode, a potential Vclip_dark is supplied to a gate of one of the clip transistors CL corresponding to at least one pixel column formed of the optical black pixels when reading a noise level from the pixels PX corresponding to the clip transistors CL and when reading a data level from the pixels PX corresponding to the clip transistors CL.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Nikon Corporation
    Inventor: Toru Shima
  • Patent number: 8558159
    Abstract: The present invention provides a radiation detection element that may suppress variation in wiring load, and that may increase the arrangement pitch of connecting portions connected to external circuits. Namely, plural pixels are disposed in an inclined matrix within a detection region, and a signal line is disposed for every two pixel lines in a vertical direction.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: October 15, 2013
    Assignee: FUJIFILM Corporation
    Inventor: Yoshihiro Okada
  • Patent number: 8416326
    Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 9, 2013
    Assignee: Sony Corporation
    Inventors: Ken Koseki, Tsutomu Haruta, Yukihiro Yasui, Yasuaki Hisamatsu
  • Patent number: 8102444
    Abstract: Techniques for implementing a Black Level Correction (BLC) processing operation on image data signal pixel values that results in little to no nonlinearity in the dark areas of the image due to black noise clipping, and avoids reducing image quality or adding cost, are provided. Image data signal pixel values are caused to maintain black level while being operated on by image data signal processor circuits that precede a Noise Reduction (NR) processing operation, thus allowing the BLC processing operation to be executed after the NR processing operation. With black noise mostly removed, little to no nonlinearity in the dark areas of the image due to black noise clipping results from the BLC processing operation.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: January 24, 2012
    Assignee: Zoran Corporation
    Inventors: David Vakrat, Noam Korem
  • Patent number: 8059205
    Abstract: An image signal processing apparatus includes a clamp circuit that clamps an image signal having a horizontal synchronization signal, an optical black level period representing an optical black level, and an effective signal period representing an image signal for one horizontal line so as to clamp a value offset from the image signal on the basis of a first reference value during the optical black level period and to clamp the image signal on the basis of a second reference value different from the first reference value during the effective signal period, and a level computation circuit that determines the second reference value on the basis of a signal level clamped during the optical black level period.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: November 15, 2011
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Toshio Nakakuki
  • Publication number: 20110149124
    Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 23, 2011
    Applicant: SONY CORPORATION
    Inventors: Ken KOSEKI, Tsutomu HARUTA, Yukihiro YASUI, Yasuaki HISAMATSU
  • Patent number: 7948532
    Abstract: A solid-state image-pickup device signal processing apparatus includes a solid-state image-pickup device, an amplifier for amplifying an output signal of the solid-state image-pickup device, an A/D conversion circuit for converting an analog output signal of the amplifier to a digital signal, a digital correlated double sampling circuit for removing noises, and a device for supplying an optional-value direct current signal to a video signal portion of a digital output signal of the A/D conversion circuit. The digital correlated double sampling circuit subtracts a field-through portion of the digital output signal from the video signal portion including the optional-value direct current signal added thereto so that the optional-value direct current signal remains after subtracting the field-through portion from the video signal portion including the optional-value direct current signal when the solid-state image-pickup device image-picks up a dark space.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: May 24, 2011
    Assignee: Jai Corporation
    Inventor: Isao Takahashi
  • Patent number: 7920188
    Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: April 5, 2011
    Assignee: Sony Corporation
    Inventors: Ken Koseki, Tsutomu Haruta, Yukihiro Yasui, Yasuaki Hisamatsu
  • Publication number: 20110074987
    Abstract: An A/D conversion section (11) counts clocks whose frequency corresponds to the size of output signals from pixels (10a), and digitalizes the result so as to create count values, and also calculates a difference between a first count value that relates to the output signal during a reset period of a pixel, and a second count value that relates to the output signal during an exposure period of the pixel, and then outputs this difference as an imaging signal for this pixel. A control unit (12) controls the A/D conversion section such that the length of the counting period of the first count value is equal to the length of the counting period of the second count value.
    Type: Application
    Filed: December 2, 2010
    Publication date: March 31, 2011
    Applicant: OLYMPUS CORPORATION
    Inventors: Yasunari Harada, Yuichi Gomi
  • Patent number: 7916062
    Abstract: An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: March 29, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jui-Yuan Tsai, Cheng-Jui Chen
  • Patent number: 7889251
    Abstract: Calibrating a white level in an image scanning device. A target white level is accessed. A high white level is determined for pixel data output by an amplifier. A gain adjustment to the amplifier is determined to correct a portion of an error between the target white level and the high white level. The gain adjustment is applied to the amplifier.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: February 15, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Chung Wai Ng, David Boisvert, Kunhong Qu, Mehmet Aslan
  • Patent number: 7825967
    Abstract: An imager having column-wise clamp voltage drivers. Each clamp voltage driver is substantially identical to the output circuitry of the imager's pixels in that column and is designed to track the noise experienced by the readout pixels. Each clamp voltage driver generates and drives the appropriate clamp voltage to store reset and pixel signals in associated column sample and hold circuitry while suppressing the noise typically experienced during the readout process.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: November 2, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Roger Panicacci
  • Patent number: 7800671
    Abstract: A method for reading from a cell of a network of photosensitive cells arranged in rows and in columns, each cell being adapted to providing an image voltage or a reference voltage, including charging, simultaneously for all the cells in the row of the cell, at least one capacitor with a resulting charge which is a function of the difference between a reference current and an image current respectively corresponding to the conversion, by an amplifying factor greater than one, of the reference voltage and of the image voltage, and measuring for the cell column the capacitor charge.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: September 21, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Josep Segura
  • Patent number: 7728888
    Abstract: A clamping circuit including: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from the A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from the potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from the potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from the D/A converter and an adjusting voltage outputted from the adjusting voltage generation circuit
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: June 1, 2010
    Assignee: Olympus Corporation
    Inventor: Makoto Ono
  • Patent number: 7646412
    Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: January 12, 2010
    Assignee: Sony Corporation
    Inventors: Yasuaki Hisamatsu, Tsutomu Haruta, Ken Koseki
  • Patent number: 7623164
    Abstract: An object of this invention is to enable performing accurate DC recovery operation for an output signal from an image sensing element, and obtaining a high-quality image free from any image degradation such as a horizontal streak. To achieve this object, an image sensing apparatus includes first and second clamping circuits on the output side of an image sensing element. The image sensing element outputs a signal from an effective pixel region, a first reference signal for DC recovery of an image signal that is set for each row, and a second reference signal that is uniformly set for the pixel region. The first clamping circuit DC-recovers a signal from the effective pixel region for each row on the basis of the first reference signal. The second clamping circuit uniformly DC-recovers signals from the effective pixel region for the pixel region on the basis of the second reference signal.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 24, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiro Takeda
  • Patent number: 7589795
    Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: September 15, 2009
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chung-Wen Wu, Wen-Hsuan Lin
  • Publication number: 20090201393
    Abstract: An imaging sensor pixel array includes a semiconductor substrate, a plurality of active pixels and at least one black reference pixel. The plurality of active pixels are disposed in the semiconductor substrate for capturing an image. Each of the active pixels includes a first region for receiving light including a p-n junction for accumulating an image charge and active pixel circuitry coupled to the first region to readout the image charge. The black reference pixel is also disposed within the semiconductor substrate for generating a black level reference value. The black reference pixel includes a second region for receiving light without a p-n junction and black pixel circuitry coupled to the photodiode region without the p-n junction to readout a black level reference signal.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Applicant: OmniVision Technologies, Inc.
    Inventors: Hsin-Chih Tai, Vincent Venezia, Duli Mao, Howard E. Rhodes
  • Patent number: 7567277
    Abstract: The present invention provides an image pickup device that can accurately adjust the black level value of the effective pixel area while correcting column noise contained in pixel signals of the effective pixel area.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: July 28, 2009
    Assignee: Sony Corporation
    Inventors: Seijiro Inaba, Kenji Tanaka
  • Publication number: 20090109305
    Abstract: Embodiments of a process comprising receiving a plurality of offset analog signals, each corresponding to one of a plurality of black pixels in a pixel array; obtaining a corresponding digital value for each offset analog signal; computing an average of the digital values; and computing a black-level offset that, if applied to the digital values, would make the average of the digital values equal to a target value. Also disclosed are embodiments of an apparatus comprising an analog-to-digital converter coupled to an analog channel to receive offset analog black pixel signals from the analog channel and to obtain a corresponding digital value for each offset analog signal; circuitry and logic coupled to the analog-to-digital converter to average the digital values corresponding to the black pixels and compute a black-level offset that, if applied to the digital values of the black pixels, would make the average of the digital values of the black pixels equal to a target value.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Tiejun Dai, Xiaodong Luo, Xiangchen Xu
  • Patent number: 7463282
    Abstract: In an analog front end (FE) IC chip having a CDS (Correlated Double Sampling) function and an AGC (Automatic Gain Control) function, a clamp circuit for clamping an output signal during a black reference signal period is equipped with a mechanism for suppressing the effect of noises contaminated from a power source, external circuits, etc.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: December 9, 2008
    Assignee: Sony Corporation
    Inventors: Nobuo Nakamura, Yoko Okuzaki, Ken Koseki, Yasushi Nakamoto
  • Patent number: 7432965
    Abstract: A black level correcting device includes: an A/D converting section converting a result of subtracting a feedback signal from an input pixel signal into a pixel value to be output; and a feedback controlling section generating the feedback signal and having a holding section, a feedback gain adjusting section, etc. The holding section clamps a maintaining level to the level of the feedback signal while pixel signals of OB pixels are output, and maintains and outputs the maintaining level while pixel signals of valid pixels are output. The feedback gain adjusting section multiplies the feedback signal by clamp accelerating gain in synchronization with starting readout of the pixel signals from the OB pixels. Accordingly, clamp time of the holding section is shortened, enabling stabilization of the maintaining level at a convergence level before starting readout of the pixel signals from the valid pixels. Consequently, a sag can be reduced.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: October 7, 2008
    Assignee: Nikon Corporation
    Inventor: Yoshizo Mori
  • Patent number: 7414655
    Abstract: An image sensor comprising a plurality of pixels arranged in at least two sub-arrays; first and second delay areas respectively connected to each sub-array for respectively receiving charge from the sub-array; wherein a pitch of the first delay area is different from the second delay area and at least two readout mechanisms for respectively receiving the charge from the delay areas, wherein a same line from the first and second sub-arrays is received by each delay area at substantially the same time.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 19, 2008
    Assignee: Eastman Kodak Company
    Inventors: Eric J. Meisenzahl, Herbert J. Erhardt
  • Patent number: 7397507
    Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: July 8, 2008
    Assignee: Sony Corporation
    Inventors: Ken Koseki, Tsutomu Haruta, Yukihiro Yasui, Yasuaki Hisamatsu
  • Patent number: 7394491
    Abstract: An image sensor of the present invention prevents the phenomenon that surrounding background of a bright object reflecting or emitting strong light like the sun is presented at dark and improves image quality of the image sensor by controlling the brightness of the bright object. The image sensor using correlated double sampling technology which outputs data of an object by using difference between a reset voltage signal and a data voltage signal of a unit pixel includes a plurality of unit pixels arranged in a matrix, each outputting the reset voltage signal and the data voltage signal; a plurality of clamping means, each coupled to each unit pixels for clamping up the reset signal to a predetermined voltage level; and a voltage controlling block for adjusting voltage level supplied to a gate of each of clamping means.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 1, 2008
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Chang-Min Bae, Kwang-Ho Yoon
  • Patent number: 7372493
    Abstract: An imager having column-wise clamp voltage drivers. Each clamp voltage driver is substantially identical to the output circuitry of the imager's pixels in that column and is designed to track the noise experienced by the readout pixels. Each clamp voltage driver generates and drives the appropriate clamp voltage to store reset and pixel signals in associated column sample and hold circuitry while suppressing the noise typically experienced during the readout process.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Roger Panicacci
  • Patent number: 7358995
    Abstract: An imaging apparatus includes a solid-state imaging device that outputs a captured image signal in current mode, which in turn is subjected to CDS processing in current mode by a current signal detector, thus suppressing FPN noise. A captured image signal output by the current signal detector is amplified by a programmable gain amplifier to a certain level, and the amplified signal is converted by a current-to-voltage transducer into a voltage signal. In a clamp circuit including a current-output differential amplifier and a current adder, the differential amplifier compares the voltage signal with a reference voltage from a reference voltage source and feeds back a clamp current to the current adder so that the difference between the voltage signal and the reference voltage becomes substantially zero. The current adder is required to simply add a signal current and the clamp current.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: April 15, 2008
    Assignee: Sony Corporation
    Inventors: Ken Koseki, Tsutomu Haruta, Yasuaki Hisamatsu, Yukihiro Yasui
  • Patent number: 7355640
    Abstract: An image capturing device having a function of clamping an image signal. When the image capturing device is activated, a synchronous signal generating section begins creation of a horizontal synchronous signal, and a counter begins counting a pulse of the horizontal synchronous signal. When the counted value reaches a predetermined value, the clamping capability control section changes the level of a clamp mode signal to an H level. During a period from the start of power supply to the image capturing device to the raising of the level of a clamp mode signal to an H level, a clamp pulse generating section sets a longer width for a clamp pulse than in a normal operation so that a switch element of a clamping circuit remains in an on state in a longer period, whereby a smaller time constant for clamping is set. After elapse of a predetermined period, the switch element is controlled so as to remain in an ON state in a normal period, which is relatively short, whereby a larger time constant for clamping is set.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 8, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsuya Takahashi, Tohru Watanabe, Osamu Tabata
  • Patent number: 7295234
    Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: November 13, 2007
    Assignee: Sony Corporation
    Inventors: Yasuaki Hisamatsu, Tsutomu Haruta, Ken Koseki
  • Publication number: 20070222873
    Abstract: A signal compensation circuit for correcting DC offsets in an analog manner includes a storage unit, a multiplexer, and an arithmetic unit. The storage unit is used for storing a plurality of offset-correcting signals. The multiplexer includes at least two input ends coupled to the storage unit, each input end used for receiving an offset-correcting signal. The multiplexer includes at least one control end receiving a selector signal for selecting one offset-correcting signal from the plurality of offset-correcting signals received according to the selector signal. A first input end of the arithmetic unit is coupled to an output end of the multiplexer for receiving the selected offset-correcting signal, and a second input end of the arithmetic unit receives an image signal. The arithmetic unit executes a compensation operation based on the analog signals received at the two input ends of the arithmetic unit.
    Type: Application
    Filed: March 26, 2007
    Publication date: September 27, 2007
    Inventor: Yen-Cheng Chen
  • Publication number: 20070165122
    Abstract: A filter performs a filtering process by sampling a digital video signal only for an OB period. A first subtracter subtracts an OB data target value from the output value of the filter. A second subtracter sets a subtraction amount based on the subtracted result of the first subtracter and subtracts the subtraction amount from the digital video signal. A digital analog converter converts the subtracted result of the first subtracter to an analog signal and outputs it to an analog clamper. The analog clamper performs a subtracting process to an analog video signal based on the output value of the digital analog converter.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 19, 2007
    Inventors: Keiichi Tsumura, Shinji Yamamoto
  • Patent number: 7245322
    Abstract: The invention provides an imaging apparatus in which when a difference in sensitivity between two photosensitive elements having different sensitivities is used to achieve a wide dynamic range, a correction amount of a low sensitivity portion is determined from information of a high sensitivity portion to reduce a burden of an internal process. A black level correction value of a dependent photosensitive pixel is calculated by multiplying a black level correction value of a main photosensitive pixel by the ratio of the cell area of the main photosensitive pixel to the cell area of the dependent photosensitive pixel. It is not necessary to perform control to capture an imaging signal from the dependent photosensitive pixel belonging to an OB portion for determining the black level correction value of the dependent photosensitive pixel.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: July 17, 2007
    Assignee: FUJIFILM Corporation
    Inventors: Kazuya Oda, Hirokazu Kobayashi
  • Patent number: 7245321
    Abstract: A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes multiple circuits for reading out values of pixels from the active sensor array. Each readout circuit can be associated with a respective pair of columns in the array and can include first and second sample-and-hold circuits. The first and second sample-and-hold circuits are associated, respectively, with first and second columns of pixels in the array. Each readout circuit also includes an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit. The readout circuit also has an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Roger Panicacci, Barmak Mansoorian, Sandor Barna, Alexander I. Krymski
  • Patent number: 7102672
    Abstract: A method, apparatus, and system for accounting for dark current in the output of an imaging array is presented. A dark current monitor on the monolithic semiconductor imaging array is provided. The dark current monitor may be darkened pixels of the imaging array, darkened pixels of another array, or a temperature monitor and associated circuitry necessary to calculate relative dark current from the monitored temperature.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: September 5, 2006
    Assignee: Electro Optical Sciences INC
    Inventor: Adam Jacobs
  • Patent number: 7064785
    Abstract: Apparatus and method of correcting for dark current in a solid state image sensor, include capturing an image with the image sensor to produce a digital image having pixel values; correcting the pixel values with a dark level correction value; employing a control system to adjust the dark level correction value to drive the number of pixels having values lower than a predetermined value chosen to represent dark scene content to a predetermined range.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: June 20, 2006
    Assignee: Eastman Kodak Company
    Inventors: Wayne E. Prentice, Stephen M. Coppola
  • Patent number: 6952240
    Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 4, 2005
    Assignee: Exar Corporation
    Inventors: Richard L. Gower, Eric G. Hoffman, Bhupendra K. Ahuja, J. Antonio Salcedo
  • Patent number: 6900837
    Abstract: An image sensor and a pixel reading method used this image sensor, in which the accuracy of a black level can be increased by that an optical black region being the black level reference of signals is read every horizontal line at a local or random access mode, are provided. And also the structure of a camera system used this image sensor can be simplified is provided. The image sensor is a MOS type image sensor composed of a pixel array region and an optical black region disposed at the one end in the pixel array region. And the MOS type image sensor provides a mode selector that selects the local access or random access mode or a frame access mode. When the local access or random access mode is activated, the image sensor decides a pixel reading region in the pixel array region. The image sensor reads information of one or more pixels having a designated horizontal line address in the pixel reading region every horizontal line address.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: May 31, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Hidemitsu Nikou
  • Patent number: 6792141
    Abstract: A system and method for processing digital video. The invention allows for manual level and gain adjustment of the video similar to that used in a histogram based automatic level and gain control system using a cumulative distribution function. Level changes are made by an offset to the existing automatic level and gain. Level changes are first made by applying an offset L and the midscale gray intensity bin on the histogram is located. Gain changes are made by changing the relative gain multiplier (G) which acts on the automatic level and gain algorithm causing the gain to change equally about midscale gray (i.e., midscale gray is maintained). In accordance with the invention, as part of the histogram based manual level and gain algorithm, the local gain is clipped to a predetermined maximum in order to prevent an overly noisy picture when too much gain is applied. The inventive method determines how to prevent a shift in the level when increasing the gain (i.e., G>1) even when clipping is applied.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: September 14, 2004
    Assignee: Raytheon Company
    Inventor: Lee J. Huniu
  • Patent number: 6774942
    Abstract: An improved offset correction circuit for an image digitizing system having a correlated double sample and hold circuit, a programmable gain amplifier and an analog-to-digital converter. The output of the analog-to-digital converter is provided to a dual offset correction circuit. The dual offset correction circuit provides both first and second correction values as feedback signals. In one embodiment, the first correction value is a coarse correction which is applied prior to amplification by the programmable gain amplifier. The second correction value is a fine correction offset which is applied as feedback after the programmable gain amplifier.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: August 10, 2004
    Assignee: Exar Corporation
    Inventors: Jose A. Salcedo, Srinivas N. Neti, Charles A. Rogers
  • Publication number: 20040145665
    Abstract: The invention provides an imaging apparatus in which when a difference in sensitivity between two photosensitive elements having different sensitivities is used to achieve a wide dynamic range, a correction amount of a low sensitivity portion is determined from information of a high sensitivity portion to reduce a burden of an internal process.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 29, 2004
    Inventors: Kazuya Oda, Hirokazu Kobayashi
  • Patent number: 6765613
    Abstract: A number of different elements are added together in a staggered way to avoid the total loss of resolution caused by the binning process. The circuit for doing this includes a variable gain. In a second circuit for carrying this out, to fixed pattern noise reduction circuits are used.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Sandor L. Barna, Eric R. Fossum
  • Patent number: 6738098
    Abstract: A method and apparatus within a television receiver for electronically aligning signals within the receiver by controlling support circuitry for an IF module. A video amplifier is coupled to an output of the IF module. A control voltage source (DAC 114) controls a DC level control circuit within the video amplifier (244) such that the video signal is amplified and DC level shifted to align the video signal with down stream circuitry.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: May 18, 2004
    Assignee: Thomson Licensing S.A.
    Inventor: Daniel Mark Hutchinson
  • Publication number: 20040075758
    Abstract: Image data is inputted from a data processing device 23 into storage means 24 formed on a light-emitting element (yellow) line head 28 so that light emitting elements in one line 28a expose pixels on an image carrier in response to output signal from a shift resistor 24a. As the image carrier is moved in the direction of X to bring said pixels to reach the position corresponding to light emitting elements in the next line 28b, the image data is transmitted to a shift resistor 24b so that the shift resistor 24b outputs the image data to light emitting elements in the line 28b, whereby the pixels are exposed to light again. The movement of the image carrier and the transmission of the image data to the respective shift resistors are sequentially conducted, thereby conducting multiple exposure of each same pixel.
    Type: Application
    Filed: May 30, 2003
    Publication date: April 22, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yujiro Nomura, Mitsukazu Kurose, Kiyoshi Tsujino
  • Patent number: 6720999
    Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: April 13, 2004
    Assignee: Cirrus Logic, Inc.
    Inventors: Douglas R. Holberg, Sandra M. Johnson, Nadi R. Itani, Argos R. Cue
  • Publication number: 20040046872
    Abstract: An object of the invention is to provide an image sensing apparatus capable of sensing an image in consideration of the influence of inserting/removing an optical filter, an image sensing method, a recording medium, and a program. To achieve this object, a brightness value calculation unit calculates the first brightness value representing the brightness of part or all of an object which is imaged on a CCD image sensing element. A brightness value correction unit calculates the second brightness value by correcting the first brightness value calculated by the brightness value calculation unit on the basis of the light reduction amount generated by inserting an ND filter. A system controller controls an optical system and signal processing in a DSP circuit by using the second brightness value calculated by the brightness value correction unit.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 11, 2004
    Inventor: Yoshiro Udagawa