Abstract: An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

Abstract: A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.

Abstract: A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.

Abstract: A method for manufacturing a spectroscopic sensor includes: (a) forming a light receiving element on a semiconductor substrate; (b) forming an angle restricting filter on the semiconductor substrate; and (c) forming a spectroscopic filter on the angle restricting filter. The step (c) of forming a spectroscopic filter includes: (c1) forming a first light transmitting film having a peripheral edge that overlaps a light blocking portion in plan view ox the semiconductor substrate by a lift-off method; and (c2) forming a second light transmitting film at a position spaced apart from the first light transmitting film in plan view of the semiconductor substrate by the lift-off method, the second light transmitting film having a peripheral edge that overlaps the light blocking portion in plan view of the semiconductor substrate.

Abstract: In a solid-state image pickup apparatus including a pixel array having pixels each including photoelectric conversion element arranged in a matrix, a synchronization signal generation unit generates a horizontal synchronization signal to define a first horizontal period and a second horizontal period different in length from the first horizontal period. Based on the horizontal synchronization signal, a reset scanning circuit sequentially selects and resets pixels in rows of the pixel array, and a readout scanning circuit sequentially selects pixels and reads a pixel signal therefrom. In each pixel, the charge is accumulated in a charge accumulation period starting when the resetting is performed and ending when the pixel signal is read. In one vertical period, the first horizontal period and the plurality of second horizontal period both appear a plurality of times, wherein the second horizontal period appears periodically.

Abstract: An image sensor includes a charge accumulation region of a first conductivity type, an isolating semiconductor region formed from an impurity semiconductor region of a second conductivity type, a channel stop region formed from an impurity semiconductor region of the second conductivity type which is located on the isolating semiconductor region, and an insulator arranged on the channel stop region. The insulator includes a first insulating portion arranged above the isolating semiconductor region via the channel stop region, a second insulating portion arranged adjacent to an outside of the first insulating portion, wherein thickness of the second insulating potion decreases with an increase in distance from the first insulating portion, and a third insulating portion formed on the first insulating portion, wherein the third insulating portion has upper and side faces connecting the upper face to an upper face of the second insulating portion.

Abstract: A method is for monitoring the electrical integrity of lines of photosites of an imaging device with matrix array of photosites. The control lines of photosites may include for each line of photosites an emission of elementary electrical control signals for the photosites of the line. The method may include diagnosis of the elementary electrical control signals emitted.

Abstract: A solid-state imaging device includes: a pixel array unit that includes a plurality of pixels arranged two dimensionally and a plurality of read-out signal lines used for reading out pixel signals from the plurality of pixels; test voltage applying units that are disposed at the read-out signal lines and apply test voltages of various voltage levels to the read-out signal lines; a reference voltage generating circuit that includes a MOS transistor used for generating a reference voltage and can change an operating point of the MOS transistor; and an operating point control unit that controls a process of adjusting the operating point of the MOS transistor based on the test voltages and the reference voltage.

Abstract: A method of operating an image sensor includes adjusting a capacitance coupled to a circuit node within a pixel cell. The circuit node is coupled to selectively receive an image charge acquired by a photo-sensor of the pixel cell. A conversion gain is selected from multiple conversion gains for the pixel cell by adjusting the capacitance. A voltage level from multiple voltage levels is selected for use as a reset signal when the reset signal is asserted. The reset signal controls resetting of the circuit node during operation of the pixel cell. The voltage level is selected dependent upon which of the multiple conversion gains is selected by adjusting the capacitance. The reset signal is asserted to reset a voltage at the circuit node.

Abstract: An image sensor includes a conductive well in a semiconductor substrate, a photo sensitive device (PSD) in the semiconductor substrate below the conductive well, the PSD and conductive well overlapping each other, and a charge transmission unit in the semiconductor substrate and adjacent to the conductive well, the charge transmission unit having a structure of a recessed gate and being positioned in a recess region of the semiconductor substrate.

Abstract: An image sensor includes a substrate having a plurality of photosensitive areas, a light shield positioned spanning the photosensitive areas in which light shield a plurality of apertures are formed, and a plurality of microlens each disposed centered on one of the apertures such that a focal point of the incident light through each microlens is substantially extended into the substrate to a point where a portion of the incident light directed onto the periphery of each microlens is blocked by a light shield.

Abstract: An image sensor array includes image sensors having photo TFTs to generate photocurrent in response to received images. The photo TFTs each have their respective gate electrodes and source electrodes independently biased to reduce the effects of dark current. Storage capacitors are coupled to each photo TFT and discharged upon generation of a photocurrent. Each storage capacitor is coupled to a readout TFT that passes a current from the storage capacitor to a data line. The photo TFT may be disposed above the storage capacitor to increase the exposed surface area of the photo TFT.

Abstract: An image sensor has at least two photodiodes in each unit pixel. A high dynamic range is achieved by selecting different exposure times for the photodiodes. Additionally, blooming is reduced. The readout timing cycle is chosen so that the short exposure time photodiodes act as drains for excess charge overflowing from the long exposure time photodiodes. To improve draining of excess charge, the arrangement of photodiodes may be further selected so that long exposure time photodiodes are neighbored along vertical and horizontal directions by short exposure time photodiodes. A micro-lens array may also be provided in which light is preferentially coupled to the long exposure time photodiodes to improve sensitivity.

Abstract: The present invention relates to a photo-detecting apparatus capable of obtaining the intensity distribution of incident light at the same timing even when the intensity distribution of incident light may change with time. The photo-detecting apparatus comprises a photo-detecting section in which plural pixels are arranged in a two-dimensional array, and a signal processing section. Each of plural pixels constituting the photo-detecting section has a first photodiode and a second photodiode, N first photodiodes included in the group of pixels constituting the m-th row of the two-dimensional array being electrically connected to each other through multiple lines, while M second photodiodes included in the group of pixels constituting the n-th column of the two-dimensional array being electrically connected to each other through other multiple lines.

Abstract: Methods and circuits for reducing noise for a passive pixel sensor (PPS) array of an image sensor are described. A noise reduction circuit includes a noise reduction integrator circuit configured to detect a potential voltage of a column line of the PPS array and generate a potential voltage substantially equal to the potential voltage of the column line. The noise reduction circuit also includes a conductor line oriented longitudinally along the column line and configured to receive the generated potential voltage from the noise reduction integrator circuit. The conductor line is placed at a potential voltage that is the same as the potential voltage of the column line. A parasitic capacitance formed between the conductor line and the column line is substantially reduced.

Abstract: An image sensor array includes image sensors having photo TFTs to generate photocurrent in response to received images. The photo TFTs each have their respective gate electrodes and source electrodes independently biased to reduce the effects of dark current. Storage capacitors are coupled to each photo TFT and discharged upon generation of a photocurrent. Each storage capacitor is coupled to a readout TFT that passes a current from the storage capacitor to a data line. The photo TFT may be disposed above the storage capacitor to increase the exposed surface area of the photo TFT.

Abstract: Dark current caused by a crystalline defect in an interfacial surface of a device isolating layer is prevented according to an image sensor and a method of manufacturing the same. A first device isolating layer adjacent to a photodiode disposed on an upper surface of a semiconductor substrate protrudes from the semiconductor substrate. A side surface of the first device isolating layer is covered by a first spacer with a refractivity greater than that of the first device isolating layer. The photodiode is insulated by the device isolating layer protruding from the semiconductor substrate to prevent the dark current. By forming the spacer on the sidewall of the device isolating layer to attain total reflection, efficiency of light incident to the photodiode is improved.

Abstract: A solid state image pickup device is provided which includes: a semiconductor substrate having a light reception region; a well being formed in the semiconductor substrate; charge accumulation regions disposed in the well in a matrix shape; a vertical transfer channel disposed in the well; a light shielding film formed above the semiconductor substrate; and a horizontal transfer channel connected to the vertical transfer channels, wherein the light reception region includes: a first region in which an opening is formed through the light shielding film above each of the charge accumulation regions; a second region in which an opening is not formed through the upper light shielding film; and a third region defined between the first and second regions along the column direction of the charge accumulation regions, the third region not having at least partially the well and not having an opening formed through the upper light shielding film.

Abstract: An image sensor comprises a detector circuit (17) with detector diodes (3), which are reverse biased during image sensing. It is characterized in that the cathode voltage of the detector diodes is controlled by forward biasing detector circuit (17) diodes via the read circuit (20). The control diodes can be dedicated diodes or forward biased photodetector diodes. In the latter case, a picture is taken in several sequences.

Abstract: An image pick-up includes a number of active sensor elements (11; 12; 13; 14) arranged in an array and a number of conductive lines extending over the surface of the array for the transfer of supply and signals. Each sensor element includes a light sensor (20) and an amplifier. According to the invention, a reduction in the number of lines can be achieved while functionality is maintained. In a first and a second embodiment (11; 12), a sensor element includes a first switch (S1) associated with the sensor and a second switch (S2; S3) associated with the amplifier, the switches being controlled by a common control signal. In a third embodiment (13), a sensor element includes a series arrangement of a first switch (S1) and a second switch (S2) included between the sensor and a supply line. In a fourth embodiment (14), a select signal is also used as a supply for the amplifier.

Abstract: A pixel structure of an image sensor, the pixel structure for providing sensor signals in response to incident light is provided. The pixel structure includes light selective elements, the light selective elements having predetermined thicknesses to absorb only light having wavelengths corresponding to the visible region of the light spectrum.

Abstract: The method is for reading a capacitive sensor and may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines. The method includes preliminarily resetting the output voltage of the charge amplifier, connecting all the deselected row and column plates of the array to a reference voltage and connecting a feedback capacitor and the selected capacitor to an inverting input of the amplifier, applying a step voltage on the capacitor that is connected to the inverting input of the amplifier, and reading the output voltage at steady-state.

Abstract: The present invention relates to a CMOS active pixel sensor which includes a compensation circuit capable of compensating a lowered pixel voltage output due to leakage current of a photodiode. The CMOS active pixel sensor having a light sensing unit for generating an output voltage when light is incident thereupon, the sensing unit having an amount of leakage current before the incidence of light. A reset unit resets the output voltage of the light sensing unit to an initial reset voltage in response to a reset signal. A sense transistor has a source, a drain coupled to a power source voltage, and a gate coupled to the output of the light sensing unit. A select transistor has a drain connected to a source of the sense transistor, and provides the voltage of the sense transistor to a bit line, in response to a select signal. A compensation unit supplies a voltage corresponding to the output voltage of the light sensing unit lowered by the leakage current.

Abstract: A current mode device for an active pixel sensor includes a voltage to current converter which includes an operation that occurs inside a source follower. The device operates to draw no current while the current is incoming. The device uses two stages of double sampling—one before the current-mode op amp and one after.

Abstract: An amplifier type solid-state imaging device is operated in a capacitor load operation system. This solid-state imaging device is made high in reliability and an arrangement of the horizontal output circuit portion is simplified. The solid-state imaging device includes a plurality of pixel MOS transistors each of which is connected between a voltage source (V.sub.DD) and a vertical signal line, a control electrode thereof being connected to a scanning line and charges generated by photoelectric conversion being accumulated near the channel thereof, a load capacitor element connected between the vertical signal line and a first potential, and a reset MOS switch for resetting the load capacitor element to a reset potential. A potential of the vertical signal line is also reset. When a signal is read out, the potential of the load capacitor element is set to substantially the same potential as the channel potential of the pixel MOS transistor.

Abstract: An active pixel sensor circuit and method. According to one embodiment, a photodetector produces a voltage at a floating diffusion node in accordance with light sensed by the photodetector. An active element is coupled at a control terminal to the floating diffusion node and is directly couplable at an output terminal to an output line. The active element is configured to provide an output voltage on the output line having a magnitude related to the magnitude of the floating diffusion node voltage.

Abstract: In a color CCD (charge-coupled device) imaging device where chromatic filter components are formed on sensor units functioning as pixels, respectively, and small condenser lenses are provided on the respective chromatic filter components, it is so constructed that areas of the small condenser lenses are varied, depending upon film thickness of the respective chromatic filter components. Then, the sensitivity increasing rates for the respective pixels of the color CCD imaging device are uniformed.

Abstract: A photosensor formed on an insulating substrate has a transparent top gate electrode arranged on the upper side of a semiconductor layer for photoelectric conversion and a bottom gate electrode arranged on the lower side of the semiconductor layer. If light is applied from the top gate electrode side in a state in which a bottom gate voltage V.sub.BG =+20 V is applied to the bottom gate electrode and a top gate voltage V.sub.TG =-20 V is applied to the top gate electrode, electron-hole pairs are generated in the semiconductor layer and only the holes are held in the semiconductor layer by the effect of the top gate voltage V.sub.TG =-20 V. Therefore, an n-channel is formed in the semiconductor layer and a drain current I.sub.DS flows. It was confirmed that the drain current I.sub.DS will not flow even if illumination light is applied when the bottom gate voltage V.sub.BG is set at 0 V. Therefore, the selection or non-selection state of the photosensor can be controlled by the bottom gate voltage V.sub.TG.

Abstract: A photosensor formed on an insulating substrate has a transparent top gate electrode arranged on the upper side of a semiconductor layer for photoelectric conversion and a bottom gate electrode arranged on the lower side of the semiconductor layer. If light is applied from the top gate electrode side in a state in which a bottom gate voltage V.sub.BG =+20 V is applied to the bottom gate electrode and a top gate voltage V.sub.TG =-20 V is applied to the top gate electrode, electron-hole pairs are generated in the semiconductor layer and only the holes are held in the semiconductor layer by the effect of the top gate voltage V.sub.TG =-20 V. Therefore, an n-channel is formed in the semiconductor layer and a drain current I.sub.DS flows. It was confirmed that the drain current I.sub.DS will not flow even if illumination light is applied when the bottom gate voltage V.sub.BG is set at 0 V. Therefore, the selection or non-selection state of the photosensor can be controlled by the bottom gate voltage V.sub.TG.

Abstract: An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell's output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp.