Abstract: A method of implementing dynamic ground sharing in an image sensor with pipeline architecture starts with a pixel array capturing image data. Pixel array includes pixels to generate pixel data signals, respectively. A readout circuitry acquires the image data from a row in the pixel array. An analog-to-digital conversion (ADC) circuitry included in the readout circuitry samples the image data from the row to obtain sampled input data. When the ADC circuitry is sampling, a ground sharing switch is closed to couple the pixel array and the ADC circuitry to a common ground. When the ADC circuitry is not sampling, the ground sharing switch is open to separate the pixel array and the ADC circuitry from the common ground. The ADC circuitry converts the sampled image data from analog to digital to obtain an ADC output. Other embodiments are described.

Abstract: In a signal processing device of an embodiment, an integration circuit accumulates a charge from a photodiode in an integrating capacitor element, and outputs a voltage value according to the amount of charge. A comparator circuit, when the voltage value from the integration circuit has reached a reference value, outputs a saturation signal. A charge injection circuit, in response to the saturation signal, injects an opposite polarity of charge into the integrating capacitor element. A counter circuit performs counting based on the saturation signal. A holding circuit holds the voltage value from the integration circuit. An amplifier circuit outputs a voltage value that is K times (where K>1) larger than the voltage value held by the holding circuit. An A/D converter circuit sets a voltage value that is K times larger than the reference value as the maximum input voltage value, that is, a full-scale value, and outputs a digital value corresponding to the voltage value from the amplifier circuit.

Abstract: According to one embodiment, a solid-state imaging device includes an analog-to-digital conversion circuit which subjects a first and a second pixel voltages from pixels to first and second signal processing, and outputs a digital value corresponding to a difference value between the first pixel voltage and the second pixel voltage, a reference voltage generation circuit which outputs reference voltages having first and second pulse waveforms to the analog-to-digital conversion circuit. The reference voltage generation circuit includes an integration circuit. In the first signal processing which compares the reference voltage with the first pixel voltage, the reference voltage generation circuit supplies a first current to the integration circuit, and generates the first pulse waveform, after the first signal processing, the reference voltage generation circuit supplies a second current to the integration circuit, and returns a voltage value of the first pulse waveform to an initial value.

Abstract: An image sensor and a method of fabricating the same are provided. The image sensor includes a substrate having a pixel region including a plurality of unit pixels and a non-pixel region, at least one first well in the non-pixel region, an interconnect structure on a first side of the substrate, and a base well in the non-pixel region and between the first well and a second side of the substrate.

Abstract: According to one embodiment, in a pixel array unit, pixels that accumulate photoelectrically converted charges are arranged in a matrix shape. A vertical signal line transmits a signal read out from the pixels in the vertical direction. An acceleration circuit shifts the potential of the vertical signal line in advance before a signal is read out from the pixels. The acceleration control circuit controls timing for shifting the potential of the vertical signal line in advance. The timing control circuit generates a control signal for controlling the acceleration control circuit.

Abstract: An image sensor includes an electronic shutter layer that is used to drain charge away from the photosensitive regions during an electronic shutter operation. A current reference component is electrically connected to a contact to the electronic shutter layer. The current reference component produces a signal having a level that is constant as a load current varies from zero to a threshold current level. A scaler component is electrically connected between the current reference component and an electronic shutter pulse driver component. The scaler component transmits the signal to the electronic shutter pulse driver component when the load current does not exceed the threshold current level. When the load current exceeds the threshold current level, the scaler component scales the level of the signal to a different level and transmits the scaled signal to the electronic shutter pulse driver component.

Abstract: According to one embodiment, a solid-state imaging device includes an analog-to-digital conversion circuit which subjects a first and a second pixel voltages from pixels to first and second signal processing, and outputs a digital value corresponding to a difference value between the first pixel voltage and the second pixel voltage, a reference voltage generation circuit which outputs reference voltages having first and second pulse waveforms to the analog-to-digital conversion circuit. The reference voltage generation circuit includes an integration circuit. In the first signal processing which compares the reference voltage with the first pixel voltage, the reference voltage generation circuit supplies a first current to the integration circuit, and generates the first pulse waveform, after the first signal processing, the reference voltage generation circuit supplies a second current to the integration circuit, and returns a voltage value of the first pulse waveform to an initial value.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: The method and apparatus for resetting an Active Pixel Sensor (APS) array comprises a controller for sequentially pre-resetting groups of one or more sensors in the array and then simultaneously resetting all of the sensors. The groups may be formed from one or more adjacent or non-adjacent individual sensors, rows or columns of sensors. The apparatus may further include a detector for sensing the bias voltage present on the array substrate in order for the controller to determine the number of sensors in the groups being reset. This method and apparatus assure that current flow is kept at a fairly steady level to avoid large variations in current flow that may disrupt other functioning circuits on the substrate including latch-up.

Abstract: An electronic imager includes a plurality of pixels having photosensors for accumulating charge corresponding to individual pixel values of a sensed image. Each of the pixels includes an anti-blooming function which allows charge in excess of a predetermined amount to be drained from the photosensor thus reducing the charge from the pixel that migrates to adjacent pixels. The imager also includes circuitry which controls the anti-blooming function in response to image intensity to reduce dark current in the imager caused by the anti-blooming function.

Abstract: A driving method is applied to a solid-state imaging apparatus having photoelectric conversion portions, transfer portion for reading out signal charges, and an excess charge draining portion for draining charges exceeding a saturation charge amount that is set by a reference voltage. One of driving modes is selected from a full pixel mode in which accumulated signal charges are detected individually for each pixel and a pixel mixing mode in which signal charges of a predetermined number of pixels are mixed to be detected. In the full pixel mode, the draining portion is supplied with the reference voltage having the same value during a charge accumulation period and a read transfer period for read transferring charges. In the pixel mixing mode, the draining portion is supplied with the reference voltage having a low level during the charge accumulation period and the reference voltage having a high level during the read transfer period.

Abstract: In a solid state imaging device, signal charges are branched to be output to in the form of one or plural outputs. At a horizontal transfer speed not lower than a predetermined transfer speed, the imaging device transfers signal charges of color attributes classified by a branching section, to plural horizontal transfer paths, where the signal charges are converted into analog voltage signals, which will be output synchronously. At a horizontal transfer speed lower than the predetermined transfer speed, the analog voltage signal converted is output from, e.g. the horizontal transfer path which has been selected. Output amplifiers arranged on the horizontal transfer paths are differentiated in sensitivities in detecting signal charges, depending on color attributes of signal charges supplied, and output the analog voltage signals.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: An electronic imager includes a plurality of pixels having photosensors for accumulating charge corresponding to individual pixel values of a sensed image. Each of the pixels includes an anti-blooming function which allows charge in excess of a predetermined amount to be drained from the photosensor thus reducing the charge from the pixel that migrates to adjacent pixels. The imager also includes circuitry which controls the anti-blooming function in response to image intensity to reduce dark current in the imager caused by the anti-blooming function.

Abstract: In an image sensor array, as would be used in an input scanner such as in a digital copier, an original image is moved relative to a linear array of photosites. Each photosite includes at least two wide photosensors, each of which extends substantially across the photosite along the array direction, and at least two narrow photosensors, which are arranged next to each other along the array direction. In one embodiment, the wide photosensors include primary-color filters and the narrow photosensors are clear-filtered.

Abstract: An image-sensing device has pixel areas for outputting CCD signals of plural channels, and an adjusting portion for adjusting a level of each channel of the CCD signals outputted from the pixel area. A first channel CCD signal is provided from a pixel area 11a, a horizontal OB area 15a, a slide shift area 12a, and an HCCD 13a. A second channel CCD signal is provided from a pixel area 11b, a horizontal OB area 15b, a slide shift area 12b, and an HCCD 13b. Both of the first and second CCD signals are supplied to the adjusting portion with a reference signal added. The adjusting portion controls CCD signal of each channel by making the level of reference signal the same. The variation of the shift efficiency of electric charge in the border of pixel areas 11a and 11b for each channel, and in the slide shift areas 13a and 13b can be compensated.

Abstract: An image-sensing apparatus for compensating video signal of a plurality of channels, adds an electric charge of a pilot signal on a signal vertically transferred in an image-sensing device 11. A pixel area of the image-sensing device 11 is divided into a plurality of pixel areas to obtain an output signal of a plurality of channels. The pilot signal is add to an output signal of each pixel area corresponding to each channel for twice a field period, and for different electric potential. The control circuit 15 obtains a difference between the two pilot signals in one filed period, and controls the gain compensation 17 to make the pilot signal level in each channel equal. Additionally, the pilot signal is not used for compensation but the previous signal is used when a smear element is detected from the output signal of each channel.

Abstract: Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and fixed pattern noise is eliminated through comparison of the photosignal level and the reset level of the floating drain. In a second mode of operation, simultaneous integration and readout processes are achieved through cessation of spill charges over the transfer gate. In a third mode of operation, regulation of the reset photodiode and transfer gate enables voltage gain between the photodiode and the sense node.

Abstract: A charge division arrangement for a CCD device for producing a divided charge output from an input charge, comprising an input for receiving an input charge, an array of elements and an output. The array of elements being arranged in rows and columns and having clock connections to allow charge in each row to be successively clocked from one row of elements to the next. At least some of the elements being arranged in a charge division unit having a first element and a second element in adjacent columns and being communicable at least temporarily so that charged introduced into the first element is divided between the first element and the second element, the charge division unit being arranged to produce divided charge for production at the output. The arrangement allows a small amount of charge to be introduced into a CCD circuit.

Abstract: A solid-state image sensor has a readout architecture that incorporates charge multiplier cells into a horizontal register of a CCD image sensor, and includes a first CCD register adjacent to at least a second CCD register and coupled to the said first register through a charge overflow barrier. A high Dynamic Range readout system results in which the DR is not restricted by the voltage swing limitations on the charge detection node. As the charge is multiplied, the horizontal register structure increases in width and more charge multiplication gates are added per stage. A charge overflow region follows the charge multiplier. In this region the amount of charge that exceeds a certain predetermined threshold is split off into another register. A detection node that has different conversion sensitivity may terminate this register. The process of charge overflow and splitting off may continue for more than two steps.

Abstract: A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.

Abstract: An image sensing device for transferring electric charge from a plurality of photoelectric converters disposed therein. The image sensing device is divided into a plurality of pixel areas. At least a pair of the divided pixel areas contiguous to each other have a vertical transfer CCD, an oblique shift CCD and a horizontal transfer CCD to transfer the electric charge from the photoelectric converters to an output stage. The output stage is at least disposed contiguous to the boundary of the divided pixel areas adjacent to each other.

Abstract: In a photoelectric conversion device having a plurality of pixel cells each of which includes a photoelectric conversion element, a field effect transistor having the gate area for storing signal charge generated by the photoelectric conversion element and the source-drain path for outputting a signal corresponding to the signal charge stored in the gate, a first power supply line for supplying electric power to the field effect transistor, and a first switch connected between the field effect transistor and the first power supply line, when a reset voltage for resetting the gate of the field effect transistor is Vsig0, a threshold voltage of the field effect transistor is Vth, current flowing through the field effect transistor is Ia, a voltage applied via the first power supply line is Vc1, and a series resistance of the first switch is Ron, each pixel cell is configured to satisfy a condition determined by Vc1?Ron×Ia>Vsig0?Vth.

Abstract: A method and circuit for compensating variations induced by temperature, strain and manufacturing technology in CMOS video sensors. Using at least two reference CMOS sensors, held at the same temperature level as the CMOS video sensors to be compensated and which are not irradiated, two reference signals are generated whereof one corresponds to a reference dark value whilst the other one, in response to the application of an electric current, corresponds to a reference illumination value. The reference signals are amplified separately of each other. At least one correction value is stored in a memory unit for each CMOS video sensor point to be compensated, such that output signals corrected by FPN (=fixed pattern noise) will be obtained. The FPN-corrected output signals as well as the reference signals obtained are supplied to the A/D converter where the output signals of the CMOS video sensor are compensated and converted into digital signals.

Abstract: Structures and methods for three-dimensional image sensing using high frequency modulation includes CMOS-implementable sensor structures using differential charge transfer, including such sensors enabling rapid horizontal and slower vertical dimension local charge collection. Wavelength response of such sensors can be altered dynamically by varying gate potentials. Methods for producing such sensor structures on conventional CMOS fabrication facilities include use of “rich” instructions to command the fabrication process to optimize image sensor rather than digital or analog ICs. One detector structure has closely spaced-apart, elongated finger-like structures that rapidly collect charge in the spaced-apart direction and then move collected charge less rapidly in the elongated direction. Detector response is substantially independent of the collection rate in the elongated direction.

Abstract: In a photosensitive apparatus having photodiodes, such as a photosensor chip used in digital office equipment, a “fat zero” initial bias is injected on the photodiode. With every cycle of operation, a first fat zero is placed on the photodiode and then sampled. Then, a second fat zero is placed on the photodiode just before the integration of a light signal from an image being recorded. The light signal plus the second fat zero is transferred out of the photodiode and the sampled signal is subtracted therefrom, leaving only the light signal. The system obviates both fixed-pattern and some thermal noise within the apparatus.

Abstract: A digital pixel sensor-based modular digital imaging system includes several integrated circuit modules. At least one module includes an integrated circuit die having a digital pixel sensor array and a frame buffer, and at least one module includes an integrated circuit die having control circuitry and/or I/O circuitry. In certain embodiments all component modules are generally the same; in other embodiments the component modules include different integrated circuits that perform different functions. A higher pixel count imaging system may be made by disposing several component modules having lower pixel count digital pixel sensor arrays adjacent one another.

Abstract: Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and fixed pattern noise is eliminated through comparison of the photosignal level and the reset level of the floating drain. In a second mode of operation, simultaneous integration and readout processes are achieved through cessation of spill charges over the transfer gate. In a third mode of operation, regulation of the reset photodiode and transfer gate enables voltage gain between the photodiode and the sense node.

Abstract: An optical detector includes a charge-coupled device (CCD). The CCD comprises an active cell for receiving a narrow beam of incident illumination and generating photoelectrons in response thereto, and a first stage readout register comprising a row of N transfer cells, where N>1. A first stage gate structure transfers charge packets consecutively from the active cell into the first stage readout register, whereby N successive charge packets are read into the N cells respectively of the first stage readout register. N second stage readout registers each comprise M transfer cells, where M>1, and a second stage gate structure transfers N charge packets from the N cells of the first stage readout register into respective first cells of the second stage readout registers and subsequently shifts the N charge packets from the respective first cells of the second stage readout registers to respective Mth cells thereof.

Abstract: A photoelectric converter output processing system includes a photoelectric converter for converting light signals into electric output signals, a voltage storage device capable of storing a reference voltage, a voltage supply device that supplies a preset voltage, a control device that selectively couples the voltage supply device to the voltage storage device so that the voltage storage device is charged to the reference voltage when the photoelectric converter is generating one of the electric output signals and a reset reference signal, and an amplifier coupled to the photoelectric converter and the voltage storage device. The amplifier amplifies the photoelectric converter electric output signals based on the reference voltage stored in the voltage storage device. Thus, reliable CCD output amplification is achieved, starting with the first effective CCD sensor output cycle.

Abstract: A solid-state camera device of the present invention includes a semiconductor substrate, a plurality of charge storage regions formed on the semiconductor substrate, a charge transfer region formed on the semiconductor substrate, for transferring charges read from the plurality of charge storage regions, a bias charge injection diode formed on the semiconductor substrate, for injecting a bias charge into the charge storage region, and sweeping out section for sweeping at least part of the charge remaining in the charge transfer region before resetting part of the bias charge injected into the charge storage region to emit part of the bias charge into the charge transfer region. That is, the present invention has a feature that the residual charge lying in the charge transfer region below the transfer gate specified for reading is swept before resetting the bias charge after injecting the bias charge into the charge storage region.

Abstract: A method and apparatus for reducing bloom in output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: A picture element sensor circuit in an image array scanner is tested by driving a reset FET with a controllable voltage to set the reverse-bias voltage across the photo-diode at any selectable level of test voltage. In this way each pixel sensor circuit in the array may be tested as if it had received a desired amount of illumination. Alternatively, the drive voltage for the reset transistor is provided over the column output line. The controllable test voltage can be applied to the column line when no row access enable signal is applied to the array. In this situation the column line source follower circuit is inhibited by the row access FETs. Thus, a separate test voltage can be driven onto the column line, through a reset switch, and connected through the pixel sensor reset transistor to the pixel sensor photo-diode. The variable reset voltage, that is driven onto the column line, can be varied between ground and the normal bias voltage V.sub.

Abstract: A device for producing an output voltage which is proportional to an applied magnetic field. The device includes a plurality charge injection regions, a corresponding plurality of charge exit regions, and a charge transfer region. The charge transfer region includes gate electrodes which serve to propagate at least one isolated charge packet across the charge transfer region in a predetermined direction from the charge input region to the charge output region. The charge packet is subject to the applied magnetic field which is perpendicular to the charge transfer region so as to induce a resultant potential that is orthogonal to both the applied magnetic field and the predetermined direction. Furthermore, the resultant potential effects a lateral redistribution of charge carriers in the packet. A recirculation configuration allows for a recycling of the packet from the output region back to the input region in order to accommodate a continuation of the redistribution of charge carriers.

Abstract: A method and apparatus for generating timing signals within the sensor in an imaging system by making provisions internally within a sensor that allows the sensor to generate the timing signals which are then output to the system to control the image sensor timing This alleviates the system from the responsibility of counting pixels and lines. The sensor will give at predetermined times, outputs which have the same wave form as the normal video output but with a much higher amplitude than the maximum video output recognized by the image processing system. These output signals will identify the end of the line and likewise will identify the end of the frame (or field). The resulting sensor can maintain its own timing sequence accurately tracking the time for lines and frame readout.

Abstract: A solid-state imaging device includes a substrate, and an array of charge-packet storage cells or picture elements (or "pixels") arranged on the substrate, each including a storage diode that stores therein a signal charge packet indicative of an incident light. A charge transfer section is coupled with the array of picture elements. The transfer section includes a charge-coupled device (CCD) register layer that is spaced apart from the storage diode to define a channel region therebetween, and a first insulated electrode overlying the register layer and the channel region. A reset section is coupled to the storage diode, for potentially resetting the storage diode by additionally injecting an extra charge packet into the storage diode and by causing the charge to drained from the storage diode.

Abstract: A test system for a photosensitive array includes an on-board test circuit with a single input terminal, wherein the output of the test circuit directly affects the value of a bias charge placed on a selected photodiode. The test circuit enables a quick test for the presence of a desired bias charge when a digital-high voltage is entered on the single input terminal, and also enables a more precise test of photodiode response linearity by application of a predetermined analog voltage to the single input terminal.

Abstract: A method for driving a CCD solid state imaging device of a frame-interline type is disclosed. The CCD imaging device comprises a semiconductor substrate, an image section including a number of pixels arranged two-dimensionally and each having a radiation sensor, transfer gate and a first vertical CCD, a storage section, a horizontal CCD shift register, and an output section. The semiconductor substrate having a protruding portion as a drain member is biased at a low level for accumulating signal charges during an effective picture interval and at a higher level for draining all of the signal charges during a frame shift transfer period. The amplitude of the driving signals for driving gate electrodes of the vertical CCD shift registers can be large without reading out noise-forming charges so that the transfer efficiency can be improved in a CCD imaging device.

Abstract: A CCD delay line comprises of first, second and third transfer regions which are formed in a semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region.

Abstract: An FIT or IT solid-state imaging device comprising a p-type Si substrate in which n-type regions forming storage diode portions, signal read-out portions, n-type CCD channels, and p.sup.

Abstract: A method and apparatus for reducing bloom in an output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: A charge coupled device includes shift registers, a common transfer electrode, and a floating and diffusion layer. Clock pulses are applied to the common transfer electrode. In response to the clock pulses, the common transfer electrode outputs signal charges to the floating and diffusion layer at a time when the shift registers are not being driven. Therefore, there is no output voltage level difference between the different shift registers.

Abstract: A virtual phase image sensor has majority carriers supplied to a virtual gate 24 by a conductor 32 overlying the image sensor, the virtual gate 24 and the conductor 32 each in contact with a conductive channel stop region 30.

Abstract: A solid imaging device that minimizes the degradation in charge transfer efficiency attributable to narrow channel effect by enlarging the apparent width of the horizontal output gate outlet. Miniaturization of the floating diffusion (FD) region is not hampered despite the apparent widening of the horizontal output gate outlet. The inventive imaging device utilizes a floating diffusion amplifier as the charge detector that detects a charge signal transferred from a horizontal CCD. In this device structure, ions are implanted into the substrate surface side of the region adjacent to the FD region in the horizontal output gate in such a manner that the channel potential of the adjacent region will become appropriately deeper than that of the forward-half region next to the adjacent region.