Abstract: A method for frame rate up conversion. The method is executed by a frame rate up-converter. The frame rate up-converter receives a plurality of consecutive input video frames and detects luminance information for a current frame. The frame rate up-converter generates a first output frame according to the luminance information for the current frame and a preceding frame before the current frame and generates a second output frame according to the luminance information for the current frame and a succeeding frame after the current frame, wherein the second output frame is outputted after the first output frame.

Abstract: An image processing apparatus according to the present invention extracts a characteristic value of a luminance in relation to respective fields of an input video, and determines the presence of a scene change between adjacent fields. A gamma curve is then generated on the basis of the magnitude of the characteristic value. When a difference in the characteristic value between fields is larger than a predetermined value and a scene change does not exist, the gamma curve to be applied to a subsequent field is modified such that the correction characteristic of the gamma curve does not vary rapidly. The luminance is then corrected using the modified gamma curve.

Abstract: Provided is a frame rate conversion apparatus for inputting a video signal and inserting an interpolation frame into the video signal so as to convert a frame rate of the video signal. The apparatus includes: an input unit for inputting the video signal; a video interpolation unit for generating an interpolation frame and performing an interpolation process of the video signal; and a control unit for controlling the generation process of the interpolation frame by the video interpolation unit. The video interpolation unit performs the interpolation frame generation process by using a plurality of methods, and the control unit controls switching between the plurality of interpolation frame generating methods.

Abstract: Arrangement for generating a pull-down switch-off signal The invention relates to an arrangement (1) for generating a pulldown switch-off signal for a video compression encoder, which signal is determined by the arrangement (1) in dependence on a converted signal which is produced from an NTSC signal by means of an inverse 3:2 pull down conversion, wherein the circuit arrangement includes a M(ean) A(bsolute) D(istortion) (MAD) detector (2) and a circuit (3) for determining Hadamard coefficients, wherein the MAD detector (2) produces a MAD signal which indicates for each block of predefined size the difference between the picture contents of two consecutive frames, wherein the circuit (3) for determining the Hadamard coefficients delivers two coefficients in blocks per frame, from which coefficients a first coefficient indicates the sum of the differences of the pixels of adjacent scanning lines i and i+1 and a second coefficient indicates the sum of the differences of the pixels of scanning lines i and i+2, a

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: An image signal processing unit includes a frame rate conversion circuit performing double frame rate conversion on an input image signal from a first frame frequency to a second frame frequency. When performing frame rate conversion with the motion correction process, a motion vector is determined between a first frame image and a third frame image, and three interpolation frame images are formed through the motion correction process to the first frame image based on the motion vector, and are inserted between the first and third frame images so as to establish the second frame frequency. When performing frame rate conversion without the motion correction process, an interpolation frame image same as the first frame image is inserted between the first and second frame images, and an interpolation frame image same as the second frame image is inserted between the second and third frame images.

Abstract: A projection display may include a frame rate conversion section selectively performing a first frame rate conversion process or a second frame rate conversion process, an image process section selectively performing a black insertion process or a pair-frames gamma process, and outputting a result as a pair of consecutive image frames, a projection display section projecting and displaying an image on the basis of the video signal processed by the frame rate conversion section or the image process section, and a control section controlling the frame rate conversion section or the image process section according to a selected operation on a menu screen, where the control section performs the user interface function so that the black insertion process or the pair-frames gamma process by the image process section is selected with priority over the first frame rate conversion process by the frame rate conversion section.

Abstract: An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived.

Abstract: Method and apparatus for improving the quality of super-resolution video imaging by suppressing ringing artifacts, reducing high-frequency noise, reducing blocking artifacts, and smoothing out jagged edges of the image to generate pictures that appear cleaner with less edge degradation. The method operates in a recursive manner within a sequence of low resolution images. Conventional SR processing is primarily enhanced within the invention by adding an artifact suppression section which creates a high frequency component signal ?SRi having significantly reduced artifacts therein achieving higher quality super-resolution image output. The method can be applied to images and image sequences (video) in monochrome or color and in any desired pixel format. The method can be implemented within image processing devices, in particular those containing programming for executing the described method steps.

Abstract: A method for efficient digital capturing of analog video signals of computer game consoles is provided. The video format of the signal is changed from 480p to 720p, without any scaling artifacts. The number of active horizontal resolution lines and active vertical resolution lines is reduced in the higher definition space, so that the output picture is a pixel-for-pixel transformed replica of the 480p image.

Abstract: An image converter converts an image rendered at a given vertical synchronous frequency into an image compatible with the specification of a display. A frame memory holds the image converted by the image converter by switching a plurality of buffers. A display controller selects one of the buffers in accordance with the vertical synchronous frequency of the display, and scans out the image from the frame memory accordingly. A switch instruction issuing unit issues a frame buffer switch instruction for designating a frame buffer to scan out from subsequently, in synchronization with the vertical synchronous frequency of the display, instead of immediately after the execution of an image converting process by the image converter.

Abstract: A video apparatus with high-resolution imaging device capable of producing standard or lower resolution images from a random or selected and variable region of viewing area.

Abstract: An apparatus for creating an interpolation frame includes a first computing unit that computes a first motion vector in relation to a first block in a first reference frame, a second extracting unit that extracts a second block in a second reference frame based on the first motion vector, a first calculating unit that calculates a correlation between the first block and the second block, a third extracting unit that extracts a third block that is shifted from the second block by a certain number of pixels, a second calculating unit that calculates a correlation between the first block and the third block, and a third computing unit that computes a motion vector for an interpolation block based on a most-highly correlated block-pair.

Abstract: Systems and methods for converting a picture frame rate between a source video at a first rate and a target video at a second rate. A system may include a phase plane correlation calculator configured to determine a first motion vector estimate. The system may further include a global motion calculator configured to determine a second motion vector estimate based on the previous frame data, the current frame data, and the first motion vector estimate. The system may also include a motion compensated interpolator for assigning a final motion vector through a quality calculation and an intermediate frame generator for generating the intermediate frame using the final motion vector.

Abstract: An image processor includes a motion vector acquisition section for acquiring and outputting an image motion vector in pixel or a predetermined block unit from plural frames included in an input image signal; and a frame interpolation section for generating an interpolated frame by using the motion vector provided by the motion vector acquisition section and for combining the interpolated frame with a frame of the input image signal, thereby composing a signal of a new frame sequence. The motion vector acquisition section includes a first motion vector acquisition section acquiring a motion vector by matching process and a second motion vector acquisition section acquiring a motion vector based on a relative misalignment of a predetermined edge component between two temporally successive frames in a specific area of an input image signal's frame.

Abstract: An apparatus for processing an image includes a motion vector detector, a motion-blurring-mitigated image generator, and a spatial resolution creation unit. The motion vector detector is configured to detect a motion vector by using an image that is made up of multiple pixels and acquired by an image sensor having time integration effects. The motion-blurring-mitigated image generator is configured to generate a motion-blurring-mitigated image in which motion blurring of a moving object is mitigated by using the motion vector detected by the motion vector detector on the assumption that a pixel value of pixel of the moving object in the image is a value obtained by integrating, in a time direction, a pixel value of each pixel in which no motion blurring that corresponds to the moving object occur as it is moved.

Abstract: The present invention relates to the field of video data de-interlacing, and in particular to a method for reconstructing full-resolution frames from a line-skipped-sequence of fields and a corresponding apparatus. It is the particular approach of the present invention to substitute missing lines of a block of a reconstructed full-resolution frame by lines from another field, e.g. the preceding field, and translating the substitute lines vertically and horizontally so as to optimized a smoothness measure computed for the thus reconstructed block. In this manner, an error-prone a priori determination of motion vectors based an interpolation of the interlaced images in the vertical direction can be avoided. The present invention may also be applied to sequences generated from a full-resolution sequence by a line-skipping operation that keeps only every Kth line and discards the other K?1 lines.

Abstract: An apparatus for frame rate up conversion comprises a motion-compensated frame rate converter, a primitive frame rate converter and a determination circuit. The determination circuit designates either the motion-compensated frame rate converter or the primitive frame rate converter to output an interpolated frame according to an index that estimates an output quality of the motion-compensated frame rate converter.

Abstract: A system and method for downscaling signal data, where the system includes an antenna receiving video signal data; an analog-to-digital converter coupled to the antenna and converting the received analog signal data to digital signal data; a memory storing video downscaling instructions; and a video downscaling processor, coupled to the memory and the analog-to-digital converter, wherein the video downscaling processor, upon reading the video downscaling instructions from the memory and executing the downscaling instructions: divides the digital video signal data into a plurality of blocks, wherein each block comprises a plurality of pixel elements; and cycles through the plurality of blocks, and for every block in the plurality of blocks, generates a new block, wherein the new block comprises a plurality of new pixels evenly spaced within the new block.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: Disclosed herein is a signal transmission apparatus, including: a two-pixel sampling out control section adapted to sample out, from among pixel samples extracted from a class image defined by a 3840×2160/100P, 119.88P, 120P/4:4:4, 4:2:2, 4:2:0/10-bit, 12-bit signal of the UHDTV1 wherein the pixel number of one frame exceeds a pixel number prescribed by the HD-SDI format, two pixel samples adjacent each other on the same line such that the pixel samples on each odd-numbered line of each frame are sampled out to a first sub image and a second sub image from among first to fourth sub images and the pixel samples on each even-numbered line of each frame are sampled out to the third sub image and the fourth sub image; a line sampling out control section; a field sampling out control section; a word sampling out control section; and a readout control section.

Abstract: A method for converting video data in a first video format to video data in a second interlaced video format comprising: determining a number of frames of the first video format to map into a frame of the second video format, the frame of the second video format having four fields; determining a number of lines from each of the number of frames of the first video format to be mapped into each of the four fields of the frame of the second video format; selecting the determined number of lines from each of the number of frames of the first video format; determining a sequence for mapping the number of selected lines into the fields of the frame of the second video format; and mapping the selected lines from each of the number frames of the first video format into the four fields of the frame of the second video format according to the determined sequence.

Abstract: Techniques and tools for high accuracy position calculation for picture resizing in applications such as spatially-scalable video coding and decoding are described. In one aspect, resampling of a video picture is performed according to a resampling scale factor. The resampling comprises computation of a sample value at a position i,j in a resampled array. The computation includes computing a derived horizontal or vertical sub-sample position x or y in a manner that involves approximating a value in part by multiplying a 2n value by an inverse (approximate or exact) of the upsampling scale factor. The approximating can be a rounding or some other kind of approximating, such as a ceiling or floor function that approximates to a nearby integer. The sample value is interpolated using a filter.

Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a detection unit configured to detect a start of a reproducing of a motion picture to be displayed on a display unit; a change unit configured to change a refresh rate of the display unit when the start of the reproducing of the motion picture is detected, the refresh rate being changed not by changing an operating frequency of the display unit, the refresh rate being changed by changing a blanking period, the blanking period being a period during which a drawing operation of a screen on the display unit is not performed; and a control unit configured to control the display unit to display the motion picture based on the changed refresh rate.

Abstract: A method of transmitting a digital video stream having a plurality of image frames and being characterized by a vertical resolution and a frame rate. A temporal multiplexing operation is applied to the image frames of the video stream in order to generate a compressed video stream having the same vertical resolution and half the frame rate of the video stream. This compressed video stream is then transmitted in lieu of the original video stream. At the receiving end, temporal de-multiplexing and pixel interpolation operations are applied to the frames of the compressed video stream in order to reconstruct the original video stream.

Abstract: A method for converting frames that can display smooth moving images is provided. A memory (16) to which image data of frames in the NTSC format is written is provided. A memory controller (14) for retrieving image data of an odd field and an even field from the memory (16) every odd field period and even field period in the frame period of the PAL format is provided. An interpolating circuit (76) is provided. The interpolating circuit (76) mixes the image data of the odd field retrieved by the memory controller (14) and image data of a next odd field at a predetermined ratio to output as image data of an odd field in the frame period of the PAL format, and mixes the retrieved image data of the even field and image data of a next even field at a predetermined ratio to output as image data of an even field in the frame period of the PAL format. A coefficient-generating circuit (73) for changing the mixing ratios in the interpolating circuit (76) every field period of the PAL format is provided.

Abstract: The present invention is generally directed to automated methods and systems for converting image streams having a first frame rate to a second frame rate without the need for user intervention. Embodiments of the present invention obviate the effects of processing of a telecine process. In one embodiment, where frames are encoded by a single video field, a statistical analysis of the differences between adjacent frames reveals a telecine pattern, thereby identifying which frames to remove. In another embodiment, where frames are encoded by even and odd video fields, which are interleaved to produce the frame, a statistical analysis of the differences between adjacent fields reveals the telecine pattern, identifies which frames to remove, and identifies frames that are candidates for re-interleaving.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: Disclosed herein is a display driving signal processor and a display apparatus. A display driving signal processor includes: input means; number-of-horizontal pixels converting means; second clock generating means; and output means. A display apparatus includes: an image displaying portion; input means; number-of-horizontal pixels converting means; second clock generating means; and output means.

Abstract: A rate conversion unit determines a frame thinning-out rate to thin out frames on the basis of a recording rate at the time of photographing and a display rate for display on a display apparatus so that a temporal updating interval of a video image between continuous fields becomes constant. After that, a frame is repeatedly inserted so that a frame rate becomes equal to the display rate.

Abstract: There is provided an image processing method capable of improving the picture quality. The image processing method comprises: incorporating input frame pictures to be displayed on a display device, on the basis of an input picture signal and an input synchronizing signal which is synchronized with the input picture signal; recording the incorporated input frame pictures in an input frame memory; and producing output frame pictures from input frame pictures, which have been recorded in the input frame memory, by producing an interpolated picture or inserting a black raster picture or thinning out the frame pictures, between input frame pictures corresponding to a picture information of the input frame picture to be displayed, on the basis of the picture information and the input synchronizing signal and an output synchronizing signal.

Abstract: There is provided an image processing method capable of improving the picture quality. The image processing method comprises: incorporating input frame pictures to be displayed on a display device, on the basis of an input picture signal and an input synchronizing signal which is synchronized with the input picture signal; recording the incorporated input frame pictures in an input frame memory; and producing output frame pictures from input frame pictures, which have been recorded in the input frame memory, by producing an interpolated picture or inserting a black raster picture or thinning out the frame pictures, between input frame pictures corresponding to a picture information of the input frame picture to be displayed, on the basis of the picture information and the input synchronizing signal and an output synchronizing signal.

Abstract: A frame rate converting apparatus for converting a frame rate of an input first image signal and outputting the image signal having the converted frame rate as a second image signal. The apparatus includes an input section into which the first image signal is input; a detecting section for detecting a time difference between synchronization timing of each frame of the first image signal and synchronization timing of each frame of the second image signal; a section for determining an output method of outputting the first image signal in conformity with a frame rate of the second image signal, based on a time period of each frame of the first image signal, a time period of each frame of the second image signal, and the above time difference; and an output section for outputting the first image signal as the second image signal in accordance with the determined output method.

Abstract: A pickup 1 generates a video signal based on an arbitrarily set frame rate. A frame rate converter 2 converts a frame rate of the video signal output from the pickup 1 into a predetermined frame rate. Frame rate conversion information output units 6 and 4 output information on frame rate conversion in a manner corresponding to a video signal after the frame rate conversion.

Abstract: For example, samples included in a frame constituted by a 3840×2160/24P,25P,30P/4:4:4,4:2:2,4:2:0/10,12-bit signal are mapped into first to fourth sub-images specified in the HD-SDI format, in units of two adjoining samples. Thus, it is possible to transmit through a transmission constitution for the HD-SDI format. The signal can be converted into serial digital data permitting a bit rate of 10.692 Gbps or the like and transmitted, and the receiving side can accurately reproduce original data.

Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.

Abstract: A motion vector detection section detects a motion vector by using an image that is made up of multiple pixels and acquired by an image sensor having time integration effects. A time resolution creation section generates an image that has a higher time resolution by using the detected motion vector and the image made up of the multiple pixels. A motion-blurring-mitigated image generation section generates a motion-blurring-mitigated image in which motion blurring of a moving object is mitigated by using the detected motion vector on the assumption that a pixel value of pixel of the moving object in the image is a value obtained by integrating, in a time direction, a pixel value of each pixel in which no motion blurring that corresponds to the moving object occur as it is moved.

Abstract: A method and an apparatus are disclosed for increasing the frame rate of an input video signal by interpolating video frames between original video frames of the input video signal and inserting interpolated video frames between original video frames of the input video signal to produce an output video signal having a higher frame rate than the input signal.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: According to one aspect, the invention provides an apparatus for converting data encoded in a graphics signal to at least one output signal. The apparatus includes an input, a plurality of outputs, signal processing circuitry and a controller. The input is adapted to receive the graphics signal where the graphics signal includes a plurality of frames generated at least in part from original data. The signal processing circuitry is adapted to locate, in the graphics signal, data corresponding to the original data, convert the data corresponding to the original data to output data and communicate the output data to the plurality of outputs. The controller is adapted to monitor a capacity of the signal processing circuitry and generate a signal that results in at least one disposable frame being added to the plurality of frames. The signal processing circuitry is adapted to discard the at least one disposable frame.

Abstract: A circuit for converting the format of image data, the motion of the image data being smooth, includes a memory (16) to which moving image data in the NTSC format is written; a memory controller (14) retrieving respective signals, from the memory (16), required for producing image data of an odd field and an even field in the PAL format; line-interpolating circuits (73) and (74) converting retrieved image data into first image data and second image, respectively, both image data having the line frequency of the PAL format; a frame-interpolating circuit (75) outputting the image data of the odd field in the PAL format by mixing image data of the odd field of the first image data and image data of the odd field of the second image data at a predetermined mixing ratio, and outputting the image data of the even field in the PAL format by mixing image data of the even field of the first image data and image data of the even field of the second image data at a predetermined mixing ratio; and a coefficient-generatin

Abstract: An apparatus for displaying a video image on a display system comprises a decoder for converting the video image into continuous fields arranged in a first sequence, the continuous fields having a first scan rate different from a second scan rate of the display system, and sending a first signal indicating the first scan rate, a system identifier for sending a second signal indicating the second scan rate, a controller in response to the first signal and the second signal for determining interrupt points for the continuous fields, the interrupt points dividing the continuous fields into odd-numbered sections of fields and even-numbered sections of fields, a buffer for storing the continuous fields, a reorganizing unit for reorganizing one of the odd-numbered or even-numbered sections of fields into reorganized sections of fields, and a multiplexing circuit for selecting the reorganized sections of fields from the reorganizing unit, and selecting the other of the odd-numbered or even-numbered sections of field

Abstract: An image processing apparatus converts an interlaced signal including a signal converted so as to be matched to a frame rate of an input video signal with original images arranged on a basis of a predetermined sequence as the video signal into a progressive signal. The image processing apparatus includes a field-interpolated signal generator generating a progressive field-interpolated signal by interpolating a signal at a selected position corresponding to a scanning line to be interpolated in a present field, the signal at the selected position belonging to one of a field preceding the present field and a field succeeding the present field; and a double image detector determining whether a pixel in the field-interpolated signal forms a part of a double image, and replacing a pixel in the field-interpolated signal which forms a part of a double image in the field-interpolated signal with a predetermined substitute signal.

Abstract: An encoded bit stream having a frame rate of 24 Hz or 23.976 Hz and a progressive format for both NTSC and PAL is recorded on a recording medium. An encoded stream reproduced from the recording medium is supplied to a decoder 20. In the decoder 20, the encoded stream is decoded and 24 p or 23.976 p video is obtained. A video converting portion 25 converts the reproduced video into a display video in accordance with the display format of a monitor 26. For the NTSC range, 29.97 i or 59.94 p display format can be used. For the PAL range, 25 i or 50 p display format can be used.

Abstract: A system and method that convert a video source from a first rate to a second rate. The system may have as an input a video that may be frame-based or field-based at a first rate, and convert the input video to an output video that may be frame-based or field-based at a second rate. The first rate may be 50 Hz and the second rate may be 60 Hz. Converting from the first rate to the second rate may comprise repeating frames or fields. For example, when converting from a frame-based 50 Hz input video to a frame-based 60 Hz output video, the output video comprises frames where every sixth frame is a repeated version of the preceding frame.

Abstract: The video rate processor (10) is made up of an Input Video Stream input (11), at least one Input Processor/Input Devices (12), at least one Most Recent Frame Buffer (14), and at least one Output Processes/Output Device (16). The video rate processor (10) is dynamically tuned to the specific requirements of a user and the capabilities of the user's device. Further, the video rate processor (10) enables to receipt of video images in real time or from archived files while substantially maintaining the integrity of the video information.

Abstract: A multi-format digital video production system enables a user to process an input video program to produce an output version of the program in a final format which may have a different frame rate, pixel dimensions, or both. An internal production format of 24 fps is preferably chosen to provide the greatest compatibility with existing and planned formats associated with HDTV standard 4:3 or widescreen 16:9 high-definition television, and film. Images are re-sized horizontally and vertically by pixel interpolation, thereby producing larger or smaller image dimensions so as to fill the particular needs of individual applications. Frame rates are adapted by inter-frame interpolation or by traditional schemes, including “3:2 pull-down” for 24-to-30 fps conversions. Simple speed-up (for 24-to-25 conversions) or slow-down (for 25-to-24 conversions) for playback, or by manipulating the frame rate itself using a program storage facility with asynchronous reading and writing capabilities.

Abstract: The present invention provides a technique relating to a frame rate conversion which enables display of an image of extended definition by smoothening the movement of the image. Therefore, the invention fixes the direction of interpolation using information on a first frame which appeared before the insertion time of the interpolated frame, a second frame appeared before the first frame, a third frame appeared after the insertion time, and a fourth frame appeared after the third frame, based on the insertion time of the interpolated frame. The interpolated pixel is generated from pixels of the second frame and the third frame located in the direction of interpolation, and generates the interpolated frame. Then, the interpolated frame is inserted into the inputted image signal to convert the frame rate.

Abstract: An image pickup apparatus has a solid-state image pickup device which outputs a charge signal according to a timing signal, a sampling unit which samples the charge signal in response to the timing signal, an A/D converting unit which converts a sample signal to a digital signal in response to the timing signal, and a timing unit which, in response to the number of first clocks in a horizontal period of the timing signal when a picture signal is outputted at a first frame rate (60 fps), generates a timing signal having the number of clocks in the horizontal period higher than the number of the first clocks, and supplies a timing signal based on the generated timing signal, the sampling unit, and the A/D converting unit in case of a second frame rate (50 fps) lower than first frame rate.

Abstract: A video signal processor includes a synchronization signal generator configured to generate a first internal synchronization signal corresponding to a standard of an input video signal, and to generate a second internal synchronization signal synchronized with the first internal synchronization signal. A first synchronizer is configured to synchronize the input video signal with the first internal synchronization signal, and to generate a first internal video signal. A second synchronizer is configured to synchronize the first internal video signal with the second internal synchronization signal, and to generate a second internal video signal by controlling the frame rate of the first internal video signal. A codec is configured to execute both decoding of an encoded video signal and encoding of the second internal video signal in designated time partitions within each cycle of the second internal synchronization signal.