Abstract: A video interface system and method produce an interlaced video signal from a noninterlaced graphics signal produced by a computer. The video interface system receives a digitized noninterlaced graphics signal directly from the graphics system of the computer and converts the graphics signal into an analog interlaced video signal. The noninterlaced graphics signal is characterized by a higher resolution and higher frequency than the analog interlaced video signal. In the preferred embodiment, the video interface is connected to a decoder within the graphics system. The decoder generates and combines timing signals with pixel values from a frame buffer to produce a noninterlaced graphics signal.

Abstract: An image display system, in which a display image of a monitor of the first scanning system is taken by a TV camera of the second scanning system to pick up video signals to be displayed on a monitor of the second scanning system. The output of the TV camera of the second scanning system is multiplied by a factor.alpha. (.alpha. is any real number satisfying 0<.alpha.<1) in a first multiplier. This multiplication result is added together with another input value in an adder. The output of the adder is stored in a frame memory. One frame of video signals read out of the adder is multiplied by another factor (1-.alpha.) in the second multiplier. The first and second multiplication results are added together in the adder, and the addition result is returned to the frame memory as feedback. As a result, the video signals output from the TV camera are averaged to prevent an offensive image to the eye of the display.

Abstract: A system and method for eliminating flicker in an interlaced video-display image using an input-video processor, a feature-video processor, a frame buffer, an RGB-output processor, an output-video processor, a control processor, and a synchronized-clock doubler. An input video signal is processed as processed component video information and written to a video memory at a horizontal-scan rate and a vertical-scan rate. Based on the input video signal, a vertical-scan synchronization pulse and a horizontal-scan synchronization pulse are generated and then harmonically doubled. The processed component video information is read from the video memory, responsive to the harmonically doubled synchronization pulses, at a harmonically doubled horizontal-scan rate and a harmonically doubled vertical-scan rate, reading in an interlaced format, with each frame being contiguously read twice in a proper odd-even order as when normally read to generate four fields of video information per frame which may be interlaced.

Abstract: An image format converter for an HDTV is disclosed including a decoder for decoding transmitted data to thereby output video data, image format information, picture structure information, an input frequency sync signal, an input vertical sync signal, and an input line sync signal; a sync signal generator for outputs a display line sync signal, display vertical sync signal, process line sync signal, and process vertical sync signal, according to the input image format and displayed image format, using the image format information and the input frequency sync signal output from the decoder, a display format signal externally input in accordance with the display format, and an externally input reference clock; and a format converter for converting the input video signal into a sequential scanning mode of 60 Hz frame rate or an interlaced scanning mode of 60 Hz frame rate, using the information values output from the decoder and sync signal generator.

Abstract: A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.

Abstract: Video down-conversion apparatus in which lines of successive output video field are interpolated from lines of respective input video fields, the apparatus being selectively operable to interpolate each output field from an input field of either field polarity so that the successive output video fields can maintain a regular odd-even field polarity sequence even if there is a discontinuity in the field polarity sequence of the input video fields.

Abstract: A system and method for generating NTSC and PAL formatted composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components in accordance with NTSC and/or PAL formats. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Alternatively, a pixel clock frequency equal to an integer multiple of the carrier frequency may be used and modulation in accordance with the NTSC and PAL formats may be accomplished by inverting, setting to zero or leaving unmodified the chrominance components. The architecture of this system greatly reduces hardware complexity and bandwidth requirements.

Abstract: An interpolation method and apparatus for converting pixels according to image formats, prevents deterioration of picture quality by performing a bilinear conversion which uses a larger number of pixels than does the conventional interpolation method which uses only two pixels. When a ratio between an interpolation point and a vertical line of unconverted pixels is .DELTA.1, a ratio between the interpolation point and a horizontal line of unconverted pixels is .DELTA.2, and eight unconverted pixels A1-A4 and B1-B4 on two lines adjacent to the interpolation position are used along with a coupling coefficient .alpha., a final interpolation signal I is generated according to the following equations:I1=(1-.DELTA.1)(1-.DELTA.2)A1+(1-.DELTA.1).DELTA.2A2+.DELTA.1(1-.DELTA.2)A3 +.DELTA.1.DELTA.2A4;I2=(1-.DELTA.1)(1-.DELTA.2)B1+(1-.DELTA.1).DELTA.2B2+.DELTA.1(1-.DELTA.2)B3 +.DELTA.1.DELTA.2B4; andI=.alpha.I1+(1-.alpha.)I2.

Abstract: A method and apparatus is provided for converting the frame rate of digital video data from one frame rate to another frame rate without introducing motion artifacts into the converted video data stream. A high frame rate video stream is converted into a lower frame rate video stream by selecting whole frames from the high frame rate video stream and outputting the selected frames as the lower frame rate video stream. To insure that only whole frames are selected from the high frame rate video stream, the frame rate of the high frame rate video stream is locked to the frame rate of the lower frame rate video stream. A frame cycle is defined to be an integer number of frames in the higher frame rate stream. The higher and lower frame rates are locked by repeatedly selecting and outputting as the lower frame rate video stream, over a time period that is substantially equal to one frame cycle, an integer number of frames from each frame cycle of the higher frame rate.

Abstract: A variable coefficient, non-separable spatio-temporal interpolation filter is used to deinterlace an interlaced video signal to produce a progressive video signal. The interlaced video signal is input to a video memory which in turn provides a reference and plurality of offset video signals representing the pixel being interpolated and spatially and temporally neighboring pixels. A coefficient index, transmitted with the interlaced video as an auxiliary signal, or derived from motion vectors transmitted with the interlaced video, or derived directly from the interlaced video signal, is applied to a coefficient memory to select a set of filter coefficients. The reference and offset video signals are weighted together with the filter coefficients in the spatio-temporal interpolation filter, such as a FIR filter, to produce an interpolated video signal.

Abstract: An electronics control system for full color and monochrome flat panel displays which automatically accommodates video signals of numerous types and formats, whether interlaced, non-interlaced, composite, or video signals with separated sync signals. Display of such video signals on a wide selection of flat panel display systems also is accommodated. Incoming and output video rates are asynchronous. Plug-in modules allow the system to convert video signals of numerous types and modes for display on any flat panel display system. Images are both automatically, and under user control, up-sized and down-sized, positioned and oriented to fit the flat panel display being used. Color images are automatically reduced to grey scale monochrome when a monochrome flat panel display is being used. Push-pull A/D converter circuitry for digitizing color video signals is used to reduce cost while conserving power.

Abstract: A circuit and method for vertically expanding a display image in an image processing apparatus. The circuit includes a section for generating a signal for classifying a field of a color signal as an even field or an odd field; a multiplexer for multiplying lines of data output from a first memory and a second line memory by coefficients according to the signal for classifying the field as being an even field or an odd field; and a line of data output section for outputting a new line of data by adding the two lines of data corresponding to the lines of data output from a first memory and a second line memory.

Abstract: Method of motion-compensated video processing such as standards conversion, uses motion vectors assigned on a pixel-by-pixel basis. The pixels of an input video signal are written to locations in a video store determined by the motion vector assigned to that pixel. Multiple vectors can address a single written pixel to enable mixing of backward and forward vectors. A confidence value governs the accumulation of pixels and the later interpolation between motion compensated fields.

Abstract: A method and system for performing inverse telecine processing requires a minimum amount of memory capacity. Specifically, the inverse telecine processing technique requires only first and second dual field buffers. The first dual field buffer has a first even buffer (1E) and a first odd buffer (1O). The second dual field buffer has a second even buffer (2E) and a second odd buffer (2O). The input video sequence to be processed comprises a sequence of video fields of alternating even and odd parity. The even fields of the input sequence are written into the even buffers of the two dual field buffers on an alternating basis and the odd fields of the input sequence are written into the odd buffers of the dual field buffers on an alternating basis. This order is changed (i.e., toggled) when a repeat field is detected. The repeat field is dropped by writing over it with the next field of the same parity in the input sequence.

Abstract: A method for calculating the pixel values of a sub-pixel accuracy motion compensated block of video pixels from one or two reference blocks, as is required in typical digital video compression and decompression systems uses a minimal amount of temporary storage memory resulting in a compact architecture suited for inexpensive consumer applications. This method utilizes a pixel pipeline within a block line pipeline to calculate the half pel accurate reference blocks and to average two blocks to result in a prediction block of pixels. The lines from each reference block are input to the invention alternately resulting in reduced memory requirements.

Abstract: A graphics subsystem converts a first graphics data stream for display on a computer monitor having a first refresh rate into a second graphics data stream for a television monitor having a second, slower refresh rate. The graphics subsystem has a first memory for storing one horizontal scan line of pixel data and a second memory for storing one half of a horizontal scan line of pixel data. Multiplexers direct data to a first summing circuit from an input port and from the first memory itself, so that a first horizontal line of input pixel data is initially stored in the first memory and a second horizontal line of input pixel data is combined with the first horizontal line of data by the first summing circuit, and the resulting combined pixel data is stored in back into the first memory. A controller sends the combined pixel data from the first memory to a second summing circuit while a next horizontal line of input pixel data is received.

Abstract: A method for converting between relatively dose field rates of perhaps 60 Hz and 59.94 Hz, monitors the phase difference between input and output field rates. Initially, output fields are created by synchronising input fields. As the measured phase passes a threshold, the method switches to interpolation mode for a short, fixed interval and then returns to synchronization. The method offers much of the sharpness associated with simple synchronization but avoids the visible discontinuities of field drops or repeats.

Abstract: A method and device for performing source transitions in a video system which performs entropy encoding such that a transition occurs only after the fields which define a frame picture have been received by the encoder. The method and device also provides arrangement for ensuring that initially after the switch to the second program source consecutive fields of information from the second program source which will be encoded as a frame picture are provided.

Abstract: A system for conversion of non-standard video signals to standard video signals for transmission and presentation picks off an internal analog video signals from imaging diagnostic equipment (such as a CAT scanner or MRI equipment), converts it to analog video signal of different, preferably standard format, prints it or stores it, and when desire transmits the reformatted image information to the physician's terminal. Preferably the storage and transmission is in binary digitized form. At a receiving station, the received signal is stored, decoded and applied in appropriate analog vide form to an associated CRT display for reproduction of the diagnostic images. The equipments at both the control site of the diagnostic station and at the remote terminals may constitute PC's (personal computers) plus an additional video monitor.

Abstract: A television signal format converter is provided for converting without loss of picture information a television format or a motion picture film image format to or from a given recorder/player format. An interface converts between RGB and luminance/chrominance inputs and between analog and digital inputs. The interface couples a source signal format to a plurality of pairs of memories. A clock and control circuit controls addressing of the memories for reading and writing so that conversion is performed between a source format and the format required for a given high definition digital video tape recorder or any other comparable recorder.

Abstract: A method and device for transcoding a digital signal first oversamples the input signal, converts the sampling rate to an oversampled output signal, filters the signal to reduce unwanted bands and decimates the oversampled output signal to produce a transcoded signal having the target sampling rate. This allows the conversion to be implemented in the composite domain, requiring a single sampling rate converter, and significantly reduces the complexity of the filter required to filter the output signal.

Abstract: The present invention is an NTSC-PAL converter which can eliminate generation of bar noise, and convert image data from the NTSC format to the PAL format with less memory capacity. The converter comprises three field memories (1), (2) and (3) for storing image data in the NTSC format in which odd and even-numbered field data in the NTSC format are sequentially written. In reading for forming the image data in the PAL format, two memories which are not being written are selected so that data are sequentially read from memories in combination of, for example, (1) and (2); (2) and (3), and (3) and (1). That is, frame data for the PAL format is formed by adding and reading field data, and by interpolating them in predetermined interval. This eliminates such situation where writing of image data in the NTSC format overtakes reading of PAL image data.

Abstract: Motion compensated video signal processing apparatus for interpolating an output image of an output video signal from a corresponding pair of temporally adjacent input images of an input video signal comprises: means for generating a plurality of local motion vectors to represent image motion of respective search blocks of one input image of the pair between that image and the other image of the pair; means for detecting blocks of the output image pointed to by each local motion vector; means for assigning a group of motion vectors to each block of the output image, the group being selected from a set of motion vectors comprising at least those local motion vectors pointing to that block of the output image; and a motion compensated interpolator for interpolating pixels of each block of the output image from the pair of input images, using a motion vector from the group assigned to that block.

Abstract: A digital video signal reception apparatus comprising a multiplexer selection controller for outputting a plurality of control signals according to a format of a compressed input digital video signal, a decoder for decoding the compressed input digital video signal, a frame rate conversion circuit for convening a frame rate of the decoded digital video signal from the decoder into a desired value under the control of the multiplexer selection controller, a multiplexer for selecting one of the decoded digital video signal from the decoder and an output video signal from the frame rate conversion circuit under the control of the multiplexer selection controller, a decimation circuit for performing a decimation operation to convert the number of horizontal scanning lines of an output video signal from the multiplexer into a desired value, a display mode conversion circuit for performing a display mode conversion operation so that an output video signal from the decimation circuit can be displayed in a desired di

Abstract: A device for converting image signal frame format including a motion compensator for restoring image signals by carrying out motion compensations employing motion information, variable length decoding, inverse multiplex conversion, displaced frame difference, inverse quantization, and inverse discrete cosine conversion. A first frame ratio convertor is used for classifying areas by pixels and converting frame ratios of image signals received from the motion compensator according to the classified areas. The device provides users with the advantage of natural display pictures having good picture quality by carrying out classification of the corresponding pixel areas and subsequent interpolation utilizing various informations applied from an image signal decoder.

Abstract: To display a more natural display screen without sense of strangeness, when displaying a video signal having a greater number of horizontal scanning lines than the number of horizontal display lines of the display means. The video signal is displayed by thinning at a rate of one out of every plurality of video signal groups. Accordingly, missing of only upper and lower portions of the video signals of the display screen is prevented, and when the video signal is compressed and displayed, a natural display screen without sense of strangeness is presented.

Abstract: A video format conversion apparatus for a high definition television comprising a decoding circuit for decoding a transmitted, encoded signal into a video signal, a frame rate conversion circuit for converting a frame rate of the video signal from the decoding circuit into 30 Hz, a decimation circuit for converting the number of vertical and horizontal scanning lines of a selected one of the video signal from the decoding circuit and an output video signal from the frame rate conversion circuit, an interlaced scanning format conversion/selection circuit for converting a scanning format of a selected one of the video signals from the decoding circuit and the frame rate conversion circuit and an output video signal from the decimation circuit into an interlaced scanning format and outputting a selected one of the converted video signal of the interlaced scanning format and the video signal from the decoding circuit, and a selection control controller for controlling the frame rate conversion circuit, the decima

Abstract: An apparatus for converting a frame format of a television signal to a display format includes a scanning format conversion circuit for converting a scanning format of an input video signal to a progressive scanning type if it is of an interlaced scanning type, a scanning line conversion circuit for converting the number of vertical scanning lines of an output video signal from the scanning format conversion circuit to that of the display format, a horizontal pixel conversion circuit for converting the number of horizontal pixels of an output video signal from the scanning line conversion circuit to that of the display format, and a format control circuit for controlling the scanning format conversion circuit, the scanning line conversion circuit and the horizontal pixel conversion circuit to convert a frame format of the input video signal to the display format.

Abstract: In an arrangement for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal, is for doubling the field frequency, for the purpose of noise reduction, motion compensation and line flicker reduction, a memory arrangement (1, 2) provided for doubling the field frequency, which memory arrangement precedes a motion compensation arrangement (5) whose output signal is applied to a noise reduction arrangement (6), and a line flicker reduction arrangement (7) is provided which receives the output signals from the noise reduction arrangement (6) and the motion compensation arrangement (5), while the converted picture signal is obtained from the output signal of the noise reduction arrangement (6), the line flicker reduction arrangement (7) or the motion compensation arrangement (5), dependent on the position with respect to time of a field

Abstract: A pixel generator and method of generating pixel data for creating frames of video pixel data from fields of input video pixel data. The pixel processor 16 includes a field buffer circuit 36 that stores a plurality of fields of input video pixel data. Coupled to the field buffer are a feature detector 38 and a pixel generator 40. The feature detector 38 generates one or more feature magnitude signals based upon one or more of the fields of input video pixel data. The pixel generator 40 has at least two logic circuits for generating at least two different intermediate pixel data values based on the input pixel data. Coupled to feature detector 38 is feature analyzer 42 that selects a feature weight corresponding to each intermediate pixel data value, the weight being based upon the value of the feature magnitude signals. Coupled to feature analyzer 42 and pixel generator 40, is a pixel averager 44 that generates output pixel data based upon a weighted average of the intermediate pixel data values.

Abstract: A display control apparatus includes an X-driver for sequentially obtaining the horizontal picture signals from a PAL video signal, and supplying the obtained signal to each of the horizontal pixel lines of an NTSC liquid crystal display panel, and a Y-driver for sequentially selecting the horizontal pixel lines, in a preset number every time the X-driver supplies a horizontal picture signal to each of the horizontal pixel lines. In particular, the Y-driver includes logic gate circuit for updating the preset number on the basis of a selection pattern in which at least first and second numbers of horizontal picture lines are determined as selection units of lines to be selected at one time, the selection units are combined at a predetermined ratio, and the combination of the selection units is repeated for each predetermined number of the horizontal picture signals, thereby assigning the horizontal pixel lines to almost all the horizontal picture signals.

Abstract: A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (J,L), which comprises a video signal demultiplexer receiving the transmission channels (J,L); and respective processing blocks for separately handling the signals from each of the channels (J,L). Each processing block includes a video image format converter, a local memory connected to an output of the converter, and at least one median filter and one systolic filter cascade connected after the memory for restoring, by interpolation, signal samples related to successive lines of the video image. A summing node adds the outputs from each processing block so as to obtain a time mean between restored samples of the channels (J,L).

Abstract: A method and apparatus for processing image data produced by an electronic camera (such as image data read from a CCD device of an electronic camera) by over-sampling and then interpolating the data to convert the format and/or resolution of the data. The format of the image data may be converted to a format suitable for display on a computer monitor or the like. The invention enables the aspect ratio of a frame of image data output from a CCD device to be converted to 1:1. Preferably, the image data are filtered by a filter having a characteristic opposite to the frequency characteristic of the interpolation function, and then interpolated so that the interpolation can be carried out at a portion where the change of the frequency characteristic is small, thereby improving the image quality of the fully processed output image.

Abstract: An apparatus for converting an input video signal to a modified video signal comprises a memory for storing data corresponding to the input video signal, an address signal generating device for reading data from the memory and an interpolating filter for interpolating the data read from the memory to obtain a modified video signal. The data are stored and read from the memory using a clock having a predetermined frequency. However, since the number of addresses being read in one horizontal display varies with the conversion rate of video signals, the length of one horizontal display of the modified video signal is different from that of the input video signal.

Abstract: A double standards converter for converting video signals formatted according to a first standard having a slower frame rate to a second standard having a faster frame rate prior to intermediate signal processing, and for converting the signals resulting from the intermediate signal processing to a third format having the same frame rate as the original video signals. The input video signals are first time base corrected and then converted to the second format repeating a frame in a periodic manner related to the time ratios between the first and second frame rates. After intermediate signal processing, the resulting signals are converted to the third format having the slower frame rate by deleting each repeated frame. Each repeated frame presented to the intermediate signal processor is excepted from the intermediate signal processing in order to avoid the introduction of discontinuities when the leading and trailing frames are joined by deleting the repeated frame.

Abstract: A method of processing an input 60 field/second video signal generated by 3232 pulldown to produce an output video signal, comprises producing from the input signal a series of progressive scan format frames, each frame corresponding to a respective one of the input fields, and comparing blocks of pixels in each progressive scan frame with blocks of pixels in the following frame to derive motion vectors representing the motion of the content of respective blocks between frames. The motion vectors are utilized to monitor the field sequence of the input signal, and fields or frames of the output video signal are produced using input fields or progressive scan frames selected in dependence upon the field sequence of the input signal, at least some of the output fields or frames being produced by motion compensated temporal interpolation utilizing the motion vectors.

Abstract: In an electronic endoscope system, an imaging device images a subject at a first frame frequency. A signal generating unit receives image signals of the subject imaged by the imaging device to generate signals of a standard TV system having a second frame frequency that is approximately n/m-fold (where, n and m are natural numbers, and n is unequal to m) of the first frame frequency. Then, a timing control unit synchronizes the first frame frequency of the imaging device with the second frame frequency using a predetermined timing signal output by the signal generating unit. The timing controller can also synchronize a first frame frequency of a color field sequential illumination unit with a second frame frequency using a predetermined timing signal.

Abstract: A time base changer for a video converter for converting between a sequence of input video images at an input video rate and a sequence of output video images at an output video rate is operable to convert from one of a number of input video rates to an output video rate. The time base changer includes N video stores 32 where N is a integer greater than one, each for storing a video image. The video stores are enabled cyclically and at the appropriate input video rate for storing successive input video images in successive video stores. Multiplexers 36 connected to the video stores can output pairs of video images from the video stores at the output video rate. The time base changer includes a counter 38 which can be clocked at the appropriate one of the input video rates. The counter is preferably a modulo-N counter.

Abstract: A scanning line converting apparatus for converting between NTSC and PAL formats includes a plurality of line memories, an arithmetic circuit and a picture memory. Switches in the lines connecting these elements permits the order of connection to be shifted between first and second states. When converting from the PAL system to the NTSC system, 5 lines are formed by varying the mutual signal ration of 2 lines for every 6 lines, while, when converting from the NTSC system to the PAL system, 6 lines are formed by varying the ratio of 2 lines for every 5 lines, thereby making it possible to convert the lines of one field of different broadcasting methods when actually scanning the picture tube. The ratios used in computations performed by the arithmetic circuit are related to horizontal synchronizing signals and to vertical blanking signals, while they are also related to constants which are furnished by a percent block. A method for converting between different broadcasting formats is also described.

Abstract: A film-to-video format detector (24) for a digital television receiver (10). The detector (24) receives pixel data from a current field and a second preceding field. It determines a set of pixel difference values, sums them to obtain a field difference value, and compares the field difference value to a threshold. These steps are repeated to obtain a series of field difference indicators. This series is analyzed to determine whether it has a pattern corresponding to a film-to-video format.

Abstract: An image memory device wherein data necessary for interpolation is read out simply and successively from a frame memory at a time without requiring a complicated timing control circuit to allow interpolation processing to be performed at a high speed. Image data are temporarily stored into a plurality of parallel frame memories having an interleave construction. Conversion addresses for the frame memories are generated based on different conversion rules from a plurality of address decoders and applied in parallel at a time to the frame memories so that data at neighboring points of a coordinate position for an object of interpolation are outputted at a time from the frame memories. The neighboring point data are inputted in parallel at a time, or pipeline inputted, to an interpolation calculation circuit so that coefficients are generated from individual pipelines. Product sum calculation is performed for the coefficients and the neighboring point data.

Abstract: A motion compensation image processing apparatus and method for generating motion vectors that represent image motion between a pair of input images from which an output image is derived by motion compensated interpolation. A plurality of motion vectors are generated for each pixel of the output image and it is determined whether respective test blocks of each of the pair of input images, pointed to by each of the plurality of motion vectors, lie partially outside their respective input images. If one or both of the test blocks lies partially outside its respective input image, the degree of correlation between the test blocks is detected by performing a first correlation test on parts of the test blocks lying inside their respective input images. However, if both of the test blocks lie wholly inside their respective input image, the degree of correlation between the test blocks is detected by performing a second correlation test.

Abstract: An input digital video signal representing a series of input frames with at least some of the input frames each having a first picture portion having a first acquisition characteristic (such as 60 Hz, 2:1) and a second picture portion having a second acquisition characteristic (such as 30 Hz, 1:1) is processed to produce an output video signal representing a series of output frames having generally the same acquisition characteristic (such as 24 Hz, 1:1). The method comprises the steps of distinguishing between the first and second picture portions in the input frames (for example by determining the difference between input fields (a.sub.1, a.sub.2 ; a.sub.3, a.sub.4 ; . . . ) of a pair, or by detecting a key signal accompanying the input video signal) and processing the first and second picture portions differently to produce the output frames.

Abstract: In an image display apparatus including a display unit for displaying an image of an inputted video signal thereon with a predetermined field frequency and a predetermined number of scanning lines using vertical and horizontal synchronizing signals for deflection of display in response to the inputted video signal, a first converter converts an inputted first video signal having a first field frequency which is lower than the predetermined field frequency and having the predetermined number of scanning lines, into an output second video signal having the predetermined field frequency and the predetermined number of scanning lines, and outputs the output second video signal to the display unit.

Abstract: Pairs of temporally adjacent input images are interpolated to produce motion compensated images using motion vectors generated from said but not all of the pairs of input images from which the output images are interpolated.

Abstract: In an image display apparatus including a display unit for displaying an image of an inputted video signal thereon with a predetermined field frequency and a predetermined number of scanning lines using vertical and horizontal synchronizing signals for deflection of display in response to the inputted video signal, a first converter converts an inputted first video signal, having a first field frequency which is lower than the predetermined field frequency and having the predetermined number of scanning lines, into an output second video signal having the predetermined field frequency which is and the predetermined number of scanning lines, and having outputs the output second video signal to the display unit.

Abstract: A video input signal is vertically interpolated and applied along with a field delayed and a field advanced video signal to respective inputs of a first median filter the output of which is applied along with a line delayed and a line advanced signal to respective inputs of a second median filter to provide an interpolated video output signal. The resultant double median filtered signal and a field delayed signal are applied via respective time compressors to a multiplex switch to provide an output signal of progressive scan form and in which every other line thereof is interpolated by double median filtering.

Abstract: The system for converting a 50 Hz, 312.5 lines per field video composite input signal into a 60 Hz, 262.5 lines per field video composite output signal includes an A/D converter for converting the entire video input signal into a digital video composite signal. The digital video composite signal is stored in a dual port, FIFO, random access field memory. Write cycle commands are generated by gate array logic (GAL) circuits based upon a color subcarrier signal typical of the 60 Hz, 262.5 line output signal, and a horizontal and vertical field signal based upon the 50 Hz input signal. Read commands for the RAM are generated by the GAL based upon an independently generated 60 cycle (Hz) signal. The GAL also deletes between 15 or 30 video lines from the top of each field based upon a timing relationship from a vertical blanking signal, or in the case of the VCR, the head switch signal and a line count generated from the horizontal sync signal of the video composite input signal.

Abstract: In a method of converting a 60 field/s 2:1 interlaced video signal to 24 frame/s film, for each sequence of five input fields: the fields of at least one pair of the input fields are each progressive scan converted to form a pair of frames, and a weighted addition of the frames is made on a pixel-by-pixel basis to form an output video frame with a shifted temporal centroid, so that the temporal centroids of the output video frames are equally spaced. The output video frames are then recorded on film. In another method, the progressive scan conversion and weighted addition is performed by a single filter.

Abstract: A color television system conversion apparatus converts a television signal of a first television system into a television signal of a second television system by converting the carrier frequency of the chrominance signal of the first television system into the carrier frequency of the second television system. The carrier frequency converted chrominance signal is converted into a digital signal in response to the clock of the carrier frequency of the second television system. The digital chrominance signal is digitally decoded into two color difference signals of the first color television system. The two decoded color difference signals are converted so as to have the number of lines and the number of fields of the second television system through extraction and interpolation processes. The converted color difference signals are encoded digitally into a luminance signal of the second television system.