Abstract: A frame rate converter that receives segments having an input frame rate and provides the segments at a rate of N times the frame rate, where each segment is selected from a group consisting of a frame or field, including: a storage device which stores the segments, where the segments include a first, second, and third segments; and a display device coupled to receive the segments from the storage device and to provide the first, second, and third segments, where the display device provides the first segment and then provides the second segment following completion of providing the first segment where the second segment is previously available or otherwise again provides the first segment. The frame rate converter further includes a decoder device, where the third segment includes a field that includes a top line of an alternate frame and is encoded in 3:2 format and where the decoder device adjusts a time stamp of the third segment.

Abstract: An image data display apparatus includes a terminal display unit, an NTSC display unit, and a frame memory having a first port and a second port, for storing an image data. A display timing control unit generates a terminal display timing signal and an NTSC display timing signal. A frame memory control unit generates a first read control signal in response to the terminal display timing signal such that the image data is read out from the first port of the frame memory, and a second read control signal in response to the NTSC display timing signal such that at least a part of the image data is read out from the second port of the frame memory. A first converting unit converts the image data read out from the first port of the frame memory into a terminal display signal such that the read out image data is displayed on the terminal display unit.

Abstract: An inventive method for adapting a display frame rate in a receiver to a picture frame rate of a received signal includes the steps of comparing a picture frame rate of a received signal with a display frame of a receiver, adjusting lines per field or lines per frame displayed in response to the comparing step, and generating a display frame rate control signal for the receiver in response to the adjusting step.

Abstract: This invention is to enable, at low cost, image display with little line flicker based on an interlaced image signal and satisfactory movie display characteristics. The first de-interlace mode in which interlaced scanning line signals in the consecutive odd- and even-numbered fields are received by storage means, and the scanning line signals in the consecutive odd- and even-numbered fields are alternately read out to perform de-interlacing, and the second de-interlace mode in which scanning line signals in the odd- or even-numbered field are read out in units of fields and magnified in the vertical direction to perform de-interlacing are prepared. The scanning line signals are compared between the fields to determine whether the signal is a movie or a still image. When it is determined that the signal is a still image, the signal is displayed on a display device using a non-interlaced signal obtained in the first de-interlace mode.

Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps.

Abstract: A vertical video format converter is disclosed including a memory unit which consists of a plurality of line memories to store input video data in one of the line memories, a filter for multiplying video data items respectively output from line memories by coefficients input into corresponding video data item positions and adding the multiplied data items to output filtered data. In the present invention, the position of the filter center value is not fixed, but can be located arbitrarily and the filter coefficients need not be symmetrical. Moreover, an interpolation may be performed by one-time filtering, resulting in faster data processing.

Abstract: A multimode scan converter includes a delay element (33) for delaying one horizontal line of video signal and selectively re-displaying that line. A multiplexer (30) is arranged to selectively provide either luminance signal or chrominance signal to the delay element. Output signal from the delay element and output signal from the multiplexer are coupled to a proportioning circuit (34) which sums the two signals in complementary proportions (e.g. K and 1-K). A second multiplexer (35), which provides up-converted output luminance signal, is arranged to selectively pass the luminance signal or signal from the proportioning circuit. A third multiplexer (36), which provides up-converted output chrominance signal, is arranged to selectively pass the chrominance signal or signal from the proportioning circuit.

Abstract: A video signal processing apparatus which can perform a liquid crystal display without a deterioration of a picture quality even when a CCD sensor of the NTSC system is used at the time of the PAL system is provided. The video signal processing apparatus has a 1H delay circuit and a selecting circuit. Upon PAL system, by switching the selecting circuit once every seven lines and performing a pre-interpolation, the lines are compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system. In case of performing the liquid crystal display, the timing of an interpolation (LCOMP) signal is synchronized with the timing of the EN signal upon PAL system so as to coincide the portion of the lines to be compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system with the portion to be thinned out at a rate of 1 line per 7 lines in the liquid crystal display.

Abstract: An architecture for multi-format video processing of both high definition and standard definition television signals has a pair of processing paths. For HDTV one path processes the luminance component signal and the other path processes an interleaved color difference signal that is the combination of a pair of color difference component signals. For SDTV only a single path is used. The luminance and color difference component signals are interleaved together and optionally stuffed with filler bits to provide an interleaved signal at a high data rate, such as the HDTV data rate or one-half the HDTV data rate, for processing. After processing the SDTV components are deinterleaved from the processed interleaved signal. The color difference component signals may be upsampled prior to interleaving and subsampled after deinterleaving to simplify control signals. Thus the architecture provides a single processor for processing either an HDTV signal or two SDTV signals, one on each of the two HDTV paths.

Abstract: A video signal processing apparatus which can perform a liquid crystal display without a deterioration of a picture quality even when a CCD sensor of the NTSC system is used at the time of the PAL system is provided. The video signal processing apparatus has a 1H delay circuit and a selecting circuit. Upon PAL system, by switching the selecting circuit once every seven lines and performing a pre-interpolation, the lines are compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system. In case of performing the liquid crystal display, the timing of an interpolation (LCOMP) signal is synchronized with the timing of the EN signal upon PAL system so as to coincide the portion of the lines to be compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system with the portion to be thinned out at a rate of 1 line per 7 lines in the liquid crystal display.

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: An image signal processor is provided which accurately detects duplicate fields of a telecinema signal. The image signal processor includes a duplicate field detecting means for detecting duplicate fields of the telecinema signal and a duplicate field removing means for removing the duplicate fields. The duplicate field detecting means uses a threshold value for detecting a duplicate field and a threshold value for detecting a non-duplicate field to improve the accuracy of detection.

Abstract: An image processing apparatus includes a decoding circuit block decoding a coded image input signal specified by NTSC system with a frame rate of the NTSC system and writing a decoded image signal in an image memory as image data, and a display-image producing circuit block producing a display image data by reading the image data from the image memory with a frame rate specified by PAL system, thereby achieving the frame rate transformation from the NTSC system to PAL system, and at this time, carrying out the skipping for display at every one extent field.

Abstract: When a video signal is double-speed processed by the first device, a slight vertical deflection process is performed for redundant similar scan lines by the second device, and any slight deflection in the second device is controlled by the first device to enable setting so as to display images with excellent resolution. The first device generates a discrimination signal to designate interlaced scanning and flag a need for vertical scan-line deflection, and such signal is provided to the second device such that the second device can always appropriately determine need for vertical scan-line deflection. Through monitoring for the discrimination signal, an image display apparatus can prevent vertical resolution from deteriorating when video signals possibly requiring vertical line-shifting are inputted from an external source, and can prevent vertical resolution from deteriorating when displaying images of video signals having different systems within different areas on the same screen.

Abstract: A video signal of an interlaced scanning system having 525 scanning lines and a vertical scanning frequency of 60 Hz is converted to a video signal having 1050 scanning lines and a vertical scanning frequency of 120 Hz, for displaying an image by bidirectional scanning. A vertical synchronizing signal is subjected to offset processing by a ¼ horizontal scanning period when an odd field is started, thereby keeping interlaced relation between odd and even fields. The vertical synchronizing signal is subjected to offset processing by a ½ horizontal scanning period every frame, so that the scanning direction for each scanning line is reversed every frame.

Abstract: Film frames, or other images in which fields are captured at the same point in time, may be processed as a sequence of temporally coherent image fields or as progressive images. Such images may be obtained, for example, by digitizing signals from a telecine and dropping redundant fields inserted by the telecine. These fields may be stored in a buffer. Two fields of a given frame are read from the buffer by a resizer in accordance with read instructions, which may be determined according to any specified pulldown sequence, an output image size, and resize instructions, such as pan and scan or letterbox instructions. The resizer also may be informed of the input image size if it is not presumed. Thus, the full input image from which an output image may be generated is used by the resizer to generate output image. The resizer uses data in the input image received at one rate to generate one output image at the output rate.

Abstract: A letter-box filtering circuit and a method of using the same that includes a preprocessing filter circuit and a filtering circuit to reduce or correct the round-off errors generated when displaying an image of 16:9 on a screen of 4:3 in a digital image processing. The letter-box filtering circuit can display the down sampled image based on the 16:9 image without any distortion or reduced distortion.

Abstract: An image signal reproduction device, provided in an electronic still camera, comprises a CPU, an image signal processing circuit, a memory card, in which a compressed image signal is recorded, and a display device having a liquid crystal display (LCD) and a resolution recognition unit. A clock pulse, outputted from the CPU, is received by the resolution recognition unit, so that a recognition pulse, corresponding to the inherent resolution of the LCD, is outputted from the resolution recognition unit to the image signal processing circuit. The compressed image signal is read from the memory card, and reproduced to some extent corresponding to the resolution of the LCD.

Abstract: A data rate conversion apparatus of the present invention is a data rate conversion apparatus, comprising: an information input device for receiving frame information at a first data rate; an information storage memory including a plurality of buffers for storing the frame information; a write control device for selecting one of the buffers to which the frame information is to be written, and writing the frame information to the selected buffer; a read control device for selecting one of the buffers from which the frame information is to be read, and reading the frame information from the selected buffer; and an information output device for outputting the frame information, which is read by the read control device, at a second data rate which is different from the first data rate.

Abstract: The invention provides a method for filtering motion effects from a de-interlaced image and an apparatus associated therewith. The method assumes that the de-interlaced image is formed by a combination of a first interlaced image and a second interlaced image. A first step in the method is to interpolate an interpolated line between two lines in a region of the first interlaced image. A variance value is then determined between the interpolated line and a corresponding line in a corresponding region of the second interlaced image. A threshold value will have been predetermined in the system and the variance value is compared against that threshold value. If the variance value is less than the threshold value then the correlation is strong and the corresponding line is displayed in the de-interlaced image. Otherwise if the variance value exceeds the threshold value then the interpolated line is displayed. This process is repeated for each pixel until the entire image is displayed.

Abstract: A method for converting frame data at a slower rate into field data at a faster rate in a video decoder comprises determining a basic field repetition rate such that a field is repeated an integer number of times in a frame period, calculating a ratio differential of the repetition rate by subtracting from the speed-up ratio of the faster to the slower rate, the ratio of the fields per frame period to the slower rate, comparing the ratio differential with the differential of the field repetition rate and adding or subtracting extra fields when the two are substantially at variance.

Abstract: A scanning line number converting apparatus using a linear array type multi-parallel processor constructed by an input image data storing unit, a plurality of element processors which has a data memory section and an ALU array section and are provided in parallel and operate in accordance with the same command for a plurality of data, and an output image data storing unit, wherein one of the element processors is used as an FIFO and image data is transferred to the other element processors, and an interpolation arithmetic operation for a scanning line number conversion is executed by the element processor on the transfer destination side, so that the scanning line number conversion can be performed without using any image memory and memory controller.

Abstract: A classified adaptive spatio-temporal creation process is utilized to translate data from one format to another. This process creates new pixels by applying a filter selected on an output pixel by pixel basis which has been adaptively chosen from an application-specific set of three-dimensional filters. In one embodiment, a standard orientation is chosen, which is defined according to each output data position. Input data is flipped to align the output data position with the output position of the standard orientation. A classification is performed using the flipped input data and an appropriate filter is selected according to the classification. The filter is then executed to generate the value of the output data point.

Abstract: When a video signal is double-speed processed by the first device, a slight vertical deflection process is performed for redundant similar scan lines by the second device, and any slight deflection in the second device is controlled by the first device to thereby enable setting so as to always display images with excellent resolution. More particularly, a discrimination signal is generated by the first device to designate interlaced scanning and flag a need for vertical scan-line deflection, and such discrimination signal is provided to the second device such that the second device can always appropriately determine the need for vertical scan-line deflection. Through monitoring for the discrimination signal, an image display apparatus is capable of preventing vertical resolution from being deteriorated when video signals possibly requiring vertical line-shifting are inputted from an external source.

Abstract: A video display apparatus includes a display device, resolution conversion unit, and display position setting unit. The resolution conversion unit converts the resolution of an input video signal into that of the display device. The display position setting unit sets the display position of a first video signal in each field to be displayed on the display device on the basis of the temporal relationship between a time from generation of a vertical sync signal to input of the first video signal and the generation timing of a horizontal sync signal.

Abstract: A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.

Abstract: An ultrasonic imaging system includes an ultrasonic transducer having an image data array and a tracking array at each end of the image data array. The tracking arrays are oriented transversely to the image data array. Images from the image data array are used to reconstruct a three-dimensional representation of the target. The relative movement between respective frames of the image data is automatically estimated by a motion estimator, based on frames of data from the tracking arrays. As the transducer is rotated about the azimuthal axis of the image data array, features of the target remain within the image planes of the tracking arrays. Movements of these features in the image planes of the tracking arrays are used to estimate motion as required for the three-dimensional reconstruction. Similar techniques estimate motion within the plane of an image to create an extended field of view.

Abstract: Method and apparatus are disclosed for receiving an interlaced color video signal, and processing the signal to produce a progressively scanned video signal. An embodiment of the method of the invention includes the following steps: scan converting, by field combining and high pass filtering, the luminance component of the received signal, to obtain a progressively scanned high pass luminance component; deriving, from the luminance component of the received signal, a low pass luminance component; scan converting, by line rate conversion, to progressively scanned format, the chrominance components of the received signal and the low pass luminance component; and combining the progressively scanned low and high pass luminance components.

Abstract: A filter for downsampling input video having a first chrominance sampling to a second chrominance sampling. The input video has a Bitstream of data representing a sequence of picture frames, where each picture frame has a plurality of video lines. The filter has a means for choosing a downsampling mode from a list of available downsampling modes for the downsampling of the first chrominance sampling. The filter also has a means for dividing each picture frame into video line sets according to predetermined criteria for the particular downsampling mode chosen, where each video line set has at least two video lines. A means for assigning default downsampling coefficients for each of the video lines in the video line sets based upon the downsampling mode chosen is also provided in the filter. Lastly, the filter has a means for downsampling each video line set to a single video line having the second chrominance sampling.

Abstract: An electronic apparatus for converting a standard video signal having 59.94 fields per second into an HDTV video signal having 60.00 fields per second, by adding a number of video fields into each sequence of 1000 video fields. The apparatus detects the best moment for adding the new video field, so that the human eye does not perceive an abrupt change in the video image, by detecting the best motion conditions which occurs either when the image motion is high or very low. For adding the new video field, the apparatus uses an interpolation technique for creating two interpolated video fields which are inserted in place of one existing video field which is deleted. The apparatus also comprises a de-interlacer module for deinterlacing the 60 Hz video image, by using an advanced interpolation technique for calculating the missing video lines.

Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps. The other steps include receiving a next field, compensating the field in the input buffer, deinterlacing the received field with the compensated field in the input buffer, temporarily storing the received field, merging the received field and the compensated field into a video frame of the second sequence, and providing the video frame of the second sequence to a subsequent device.

Abstract: A video processing unit (13) that decodes compressed video data and resizes the image represented by the video data. The video processing unit (13) has two processing engines--a decoding engine (24) and a scaling engine (25), which share a memory (23). A memory manager (22) handles data requests from the two engines, and handles reading and writing of the memory (22).

Abstract: Telecine signal conversion method for converting an interlaced scan telecine signal generated by 2-3 pull-down system, wherein a picture of the first frame is converted into an interlaced signal of the first and second fields and a picture in the following second frame is converted into an interlaced signal in the third, fourth and fifth fields, into a progressively scanned telecine signal comprising steps of detecting a pull-down phase of the interlaced scan telecine signal, specifying the first and second fields based on the detected pull-down phase, composing picture signals of the specified first and second fields and generating progressively scanned telecine signals from the picture signals of the first and second frames, and specifying the third and fourth fields based on the detected pull-down phase, composing picture signals of the specified third and fourth fields and generating progressively scanned telecine signals from the picture signals of the third, fourth and fifth frames.

Abstract: A image displaying and controlling apparatus for displaying a computer graphics image in square-shaped pixels in an MPEG2 image format in rectangular-shaped pixels at a regular roundness. A graphics processor block produces the data of 640.times.480 pixels, two-line data of which are stored in two 1H buffers, and are multiplied respectively by weights output by a weight control circuit through a line conversion circuit. As a result, data of 640.times.432 are produced. A delay circuit delays a vertical synchronizing signal output by the graphics processor block by 14H. A phase comparator circuit compares the 14H delayed vertical synchronizing signal in phase with a vertical synchronizing signal output by an MPEG2 video decoder. The timing of the generation of the vertical synchronizing signal at the graphics processor block is set to be earlier by 14H than the timing of the generation of the vertical synchronization signal of the MPEG2 video decoder.

Abstract: For compatible transmission of a television picture having an aspect ratio of 16:9 within a 4:3 system, transmission is effected in the letterbox format in accordance with the PALplus system specification. The receiver reconstructs the original picture with the aid of vertical filters and is able, furthermore, to suppress crosstalk interference from the luminance signals in the chrominance signals. To further improve the picture quality, the picture is displayed at a frame frequency of 100 Hz. For this purpose, the picture supplied at 50 Hz with line interlacing must be converted to a frame frequency of 100 Hz. Known concepts for PALplus decoding and 100 Hz conversion carry out these processes separately and in doing so require a great deal of memory space.

Abstract: In arrangements for the frame rate upconversion of motion-picture-source video, a 60 Hz (interlaced field rate or progressive scan frame rate) television signal is converted to a form suitable for display on a variable-frame-rate high-resolution progressively-scanned monitor of the type typically associated with a computer or with a television set employing an increased frame rate. The inherent 3-2 motion picture film pulldown pattern in the source signal is changed to an equal time frame pattern, such as 3-3, 4-4, or 5-5, when the source signal is converted to a higher frame rate. This may be accomplished when the increased progressively-scanned video display frame rate is an integral multiple of the motion picture frame rate, namely 72 Hz, 96 Hz and 120 Hz.

Abstract: A digital signal converting method and device for converting an input image rate into an output image rate, is applied to input images which are formed by a plurality of input data frames. The method storing the input frames, calculating a sliding average over a plurality of stored frames, and deriving the averages for producing output images with a timing fixed by the output image rate.

Abstract: A video processing method and system for motion compensated filtering of interlaced television signals comprising a motion estimation device for producing motion vectors corresponding to each output sampling site, a vector processor generating a set of input coordinates for each output sampling site depending on its corresponding motion vector, a data store in memory for storing input pixel values and providing a variable delay, a plurality of multipliers and corresponding coefficient stores, and an adder to sum the partial result from each multiplier, the multipliers multiply an input pixel value, selected from the data store depending on part of the input coordinate, by a coefficient selected from the coefficient store depending on another part of the input coordinate, the filter aperture (set of filter coefficients) is selected depending on the vertical velocity component of the motion vector supplied by the motion estimation device.

Abstract: A method of display unconversion wherein each output field line is interpolated from at least three input field lines from each of at least three input fields. By increasing the field rate by 1.5 (instead of simple field doubling) and by increasing the line rate by 1.5 (instead of simple line doubling) a substantial increase in picture quality can be achieved while maintaining data flow rates within manageable limits.

Abstract: A process and system for synchronizing a video signal to the sampling period of a client system. The synchronization may be suitably implemented by adding or deleting trailing lines from each frame of video data to adjust the frame to match the sampling period of the client system. The synchronization system minimizes the lag between the time a video signal is delivered to the client system and the time the client system responds. The low lag time enhances the responsiveness of the client system to human inputs, and improves the suitability of the overall system to human use. The synchronization system can be achieved using suitable low-cost hardware and is therefore particularly well suited for video game or virtual reality systems designed for home use, increasing the feasibility of employing video inputs in such systems.

Abstract: A communication system (100) employs a method and apparatus for communicating video information therein. A first communication device (e.g., 101) preferably includes a video compressor (203), a memory device (205) containing a computer program, and a modem (207). The first device receives video information from a video device (116) via the video compressor and executes the computer program to determine a priority between transmission frame rate and resolution per frame. When transmission frame rate is of higher priority, the first device transmits the video information at a first transmission frame rate via the modem to a second communication device (e.g., 102). When resolution per frame is of higher priority, the first device transmits the video information at a second transmission frame rate that is less than the first rate. The second device, upon receiving the video information, may display (113) the information or process the information for retransmission (e.g.

Abstract: A graphics controller circuit in a computer system for generating display signals to a television. The graphics controller circuit may downscale a display image to generate a downscaled image. While downscaling, the graphics controller circuit may generate each horizontal line of a downscaled image from a different number of horizontal lines of a display image. In addition, the graphics controller circuit uses clock signals with different frequencies so as to generate each horizontal line of the downscaled image in the same amount of time. The clock frequencies are designed to generate downscaled image horizontal lines at an input rate required for a television. In effect, the graphics controller circuit may avoid dropping display image horizontal lines while downscaling, and also reduce flicker while displaying the downscaled image on a television.

Abstract: A vertical compression circuit of an image playback system displaying an image through interlaced scanning includes: a mode counter for counting horizontal lines within one section of vertical lines based on a compression mode signal and outputting a count; a coefficient selection signal generating unit for outputting a coefficient selection signal for selecting first and second filtering coefficients and for outputting a feedback control signal, based on the compression mode signal; a first coefficient selecting unit for generating first coefficients corresponding to various compression modes and outputting one of the first coefficients based on the first coefficient selection signal; a second coefficient selecting unit for generating second coefficients corresponding to various compression modes and outputting one of the second coefficients based on the second coefficient selection signal; an adder for adding the second coefficient output from the second coefficient selecting unit to one of zero and a feedb

Abstract: There is provided an image processing apparatus which comprises an input unit for inputting image data at a first frame rate, and a processing unit for providing a residual image effect to the image data input by the input unit using adjacent image data adjacent to the image data, and in which the processing unit comprises an output unit for outputting the processed image data at a second frame rate.There is also provided an image processing apparatus which comprises an input unit for inputting image data, a processing unit for providing a residual image effect to the image data input by the input unit using adjacent image data adjacent to the image data, and a display unit for displaying the image data processed by the processing unit, and in which the display frequency of the display unit is lower than the frequency of the image data input by the input unit.

Abstract: An apparatus and method for enabling a flat panel display terminal to simulate operations of a multifrequency cathode-ray tube monitor. The synchronization signals included in the input analog video signals are analyzed to identify a display protocol. The predetermined parameters for the identified display protocol are used to program the analog liquid crystal display panel and phase-locked loop of the flat panel display terminal.

Abstract: A television receiver has a main body and a remote-control transmitter. A display having an aspect ratio of 16:9 visualizes an incoming video signal. A picture analysis circuit is operative for analyzing the incoming video signal, An aspect converting circuit is operative for changing an aspect condition of indication of the incoming video signal on the display. A button is provided on one of the main body and the remote-control transmitter for commanding automatic aspect conversion when being operated. A decision is made as to whether or not the button is operated to command automatic aspect conversion. When the button is decided to be operated, the picture analysis circuit is activated to analyze the incoming video signal and the aspect converting circuit is controlled to automatically control the aspect condition of indication of the incoming video signal on the display in response to a result of the analysis by the picture analysis circuit.

Abstract: A programmable filter is provided for filtering image or texture map data. A weighting RAM stores weighting data for filtering data in both x and y directions. Different weighting values may be programmed into weighting RAMs to provide different weighting functions and also enable or disable a number of taps within the filter. A weighting value of zero, for example, may disable a particular tap for the filter. In the preferred embodiment, a number of lines in the x direction may be simultaneously weighted and then weighted and combined in the y direction to produce a filtered value within one clock cycle.

Abstract: A display device for information signals which performs highly efficient image display of a standard television signal, a high definition television signal, a progressive scanning television signal or a stereoscopic television signal on the same screen has a first signal input unit applied with the standard television signal, a second signal input unit applied with the high definition television signal, progressive scanning television signal or stereoscopic television signal, a mode designation unit for designating a mode for display of one of the signals, a signal conversion unit including a write unit for writing the first signal, at a frequency thereof, to memories and a read unit for reading the memories at a frequency which is nearly twice that of the first signal, a signal switching unit, a signal processing unit and a deflection switching unit, whereby a first display signal from the signal conversion unit or a second display signal from the second input terminal is selected and image-displayed on the

Abstract: In this invention, the duplicate field included in a telecine signal that is produced from a movie film or the like by 2-3 pull down system is detected without failure, and completely removed before being encoded or transmitted. The result of the accumulation of the duplicate field in the telecine signal is regarded as an amount of noise resulting from the conversion of a film into the telecine signal. Then, a threshold is used as a reference for detecting the duplicate field and changed in accordance with the noise. In addition, a memory is provided to store the location of the duplicate field in the telecine signal, thus making it possible to surely eliminate the duplicate field at the same location even when the same video signal is received again.

Abstract: A digital video signal reception apparatus comprising a multiplexer selection controller for outputting a plurality of control signals according to a format of a compressed input digital video signal, a decoder for decoding the compressed input digital video signal, a frame rate conversion circuit for convening a frame rate of the decoded digital video signal from the decoder into a desired value under the control of the multiplexer selection controller, a multiplexer for selecting one of the decoded digital video signal from the decoder and an output video signal from the frame rate conversion circuit under the control of the multiplexer selection controller, a decimation circuit for performing a decimation operation to convert the number of horizontal scanning lines of an output video signal from the multiplexer into a desired value, a display mode conversion circuit for performing a display mode conversion operation so that an output video signal from the decimation circuit can be displayed in a desired di