Progressive To Interlace Patents (Class 348/446)
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Patent number: 6975362Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.Type: GrantFiled: May 13, 2002Date of Patent: December 13, 2005Assignee: Fairchild Semiconductor CorporationInventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
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Patent number: 6900845Abstract: A video decoder transcodes video data from various input formats to a predetermined output format. Input data may be standard definition data or MPEG2 compressed data. Standard definition data are rearranged into block format to be compatible with the decoder's single display processor. The display processor selectively processes and conveys either MPEG2 format data or non-MPEG2 format data to a display device. A block based frame memory stores MPEG2 and non-MPEG2 pixel block data, as well as standard definition data in raster line format during processing.Type: GrantFiled: December 15, 1997Date of Patent: May 31, 2005Assignee: Thomson Licensing S.A.Inventors: Todd Christopher, Barth Alan Canfield, Steven Wayne Patton
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Patent number: 6895172Abstract: In a video signal reproducing apparatus, the changing time of a sub-video signal is adjusted, by a time-adjusting circuit, so as to be synchronized with the changing of a frame of a main video signal from the output of an interlace-scan-video-signal converter. And the sub-signal is added to the output of an interlace-scan converter by an adder. The output of the adder is converted into a progressive-scan video signal in synchronism with the boundary of frames of main video signal by the progressive-scan video signal converter. In the reproducing apparatus, even in the case that the sub-video signal is recorded without synchronism with the frames of the main video signal, an irregular frame is not generated even when the sub-video changes. And a single field of the sub-video does not leave or is not visible.Type: GrantFiled: February 7, 2001Date of Patent: May 17, 2005Assignee: Matsushita Electric Industries Co., Ltd.Inventors: Tetsuya Itani, Satoshi Kondo
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Patent number: 6891572Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.Type: GrantFiled: May 8, 2001Date of Patent: May 10, 2005Assignee: Sony CorporationInventor: Nobuo Ueki
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Patent number: 6876395Abstract: Video data of a field necessary for I/P conversion and scanning line conversion is stored in a field memory part (7), vertical frequency conversion is performed by a memory control processing part (2), I/P conversion is performed by an I/P conversion processing part (3), scanning line conversion is performed by a scanning line conversion part (4) and horizontal pixel conversion is performed by a horizontal pixel conversion processing part (5) with the data stored in the field memory part, and a synchronous processing part (6) supplies a prescribed clock, a horizontal synchronizing signal and a vertical synchronizing signal to each block. A single system performs vertical frequency conversion, I/P conversion, scanning line conversion and horizontal pixel conversion.Type: GrantFiled: November 24, 2000Date of Patent: April 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuaki Muto, Toshio Wakahara, Akio Niwa, Takuma Higashi, Tomoko Morita, Yuji Sekiguchi
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Patent number: 6870543Abstract: The present invention provides a system, method and computer program product for reducing fill and improving quality of interlaced displays using multi-sampling. In an embodiment of the invention, a frame buffer for a interlaced display is filled. Initially, a first multi-sample of the first line of the first field is calculated. The bottom sub-pixels of the first multi-sample are the top sub-pixels of a multi-sample of the first line of the second field. The first multi-sample is written into the frame buffer. Then, a second multi-sample of the second line of the first field is calculated. The top sub-pixels of the second multi-sample are the bottom sub-pixels of a multi-sample of the first line of the second field. Also, the bottom sub-pixels of the second multi-sample are the top sub-pixels of the second line of the second field. The second multi-sample is written into the frame buffer.Type: GrantFiled: June 6, 2002Date of Patent: March 22, 2005Assignee: Microsoft CorporationInventor: Gregory M. Eitzmann
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Patent number: 6842195Abstract: A transforming device for transforming computer graphics signals to television signals is provided. The transforming device includes a scaled-down line generating unit that receives the computer vertical line and generates the scaled-down vertical line, a controller that receives the scaled-down vertical line, and a scaled-down buffer that stores the scaled-down vertical line or the value of the scaled-down vertical line performed by the weighted-averages method. The content of the scaled-down buffer is transmitted to a weighted-averages operation unit, and then it is performed by the weighted-averages method with the next scaled-down vertical line. When a TV line is generated, it is the output of the transforming device. The present invention has the advantage of reducing the needed buffers in the transforming process and thereby reducing the cost.Type: GrantFiled: September 28, 2001Date of Patent: January 11, 2005Assignee: VIA Technologies, Inc.Inventors: Yi-Chieh Huang, Chun-An Lin
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Patent number: 6831700Abstract: The present invention provides a video processor which has a simple circuit configuration and can scale up and down image resolution freely. A video signal processor includes a plurality of line memories, each storing one horizontal scanning line of video data series, a controller for controlling writing and reading operations of input video data series in the line memories for every horizontal scanning line, and an arithmetical unit for generating a new horizontal scanning line of video data series based on video data series from two line memories. The controller selects the vertical scaling power of the resolution, and generates a horizontal scanning synchronizing signal having a period depending on the selected scaling power. The arithmetical unit is triggered by the horizontal scanning synchronizing signal and generates a new video data series.Type: GrantFiled: December 4, 2000Date of Patent: December 14, 2004Assignee: Pioneer CorporationInventor: Masanori Hoshikawa
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Patent number: 6831701Abstract: A method of optimizing the display of an up-converted interlaced video frame signal from a received progressive video frame signal (11) comprises the steps of receiving a progressive video frame signal, decoding (12) the progressive video frame signal using an interpolation function (18) to provide an interpolated interlaced video signal, deinterlacing (14) the interpolated interlaced video signal, and de-interpolating (16) the deinterlaced interpolated interlaced video signal to provide an optimized progressive video frame signal (17).Type: GrantFiled: June 27, 2001Date of Patent: December 14, 2004Assignee: Thomson Licensing S.A.Inventor: Donald Henry Willis
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Publication number: 20040239802Abstract: In the scanning conversion apparatus, a first converter converts input interlaced scan data into progressive scan data, and a second converter converting the progressive scan data output from the first converter to interlaced scan data.Type: ApplicationFiled: March 30, 2004Publication date: December 2, 2004Inventors: Tae-Sun Kim, Dong-Suk Shin, Seh-Woong Jeong, Kee-Yong Kim, Tae-Hee Lee, Jae-Hong Park, Hyung-Jun Im, Kyung-Mook Lim
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Publication number: 20040227852Abstract: A system and method for detecting the presence and location of pull-down fields in a video field stream. Various aspects of the present invention may comprise method steps and circuit structure for generating an array of variance indications, each of which represents a degree of variance between two video fields in the video field stream. Various aspects may comprise comparing the array of variance indications to a pattern to detect a pull-down field in the video field stream. Various aspects may comprise comparing corresponding portions of video fields and generating a histogram of differences between the corresponding portions. Various aspects may comprise generating an indication of variance of the histogram and analyzing the indication of variance. Various aspects may comprise analyzing an array of such indications of variance and may comprise comparing the array of such indications to a pattern or plurality of patterns.Type: ApplicationFiled: February 12, 2004Publication date: November 18, 2004Inventors: Darren Neuman, Joseph Del Rio, Vadim Kochubievski, Craig Zinkievich, Shannon Posniewski, Alexander G. MacInnis
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Patent number: 6806914Abstract: An image size changing apparatus has a relatively smaller circuitry arrangement for producing a size changed image which exhibits minimum artifacts such as foldover. The image size changing apparatus of the present invention allows image data to be interpolated with a ratio between a visual area determined by pixel data DS0, DS1, and DS2 of an original image and a visual area determined by pixel data DD0 and DD1 of its size changed image, hence yielding the size changed image with less artifacts such as foldover in its relatively smaller circuitry arrangement.Type: GrantFiled: October 25, 2000Date of Patent: October 19, 2004Assignee: NEC CorporationInventor: Seiki Onagawa
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Publication number: 20040160460Abstract: Systems and methods are described for delivering a data stream to a video appliance. The data stream may have a computer video signal, such as provided by the output of a computational device. The data stream is received from the computational device. The computer video signal is converted to a converted television video signal, which is combined with television video signals received from an external source. The combined television video signals are transmitted to the video appliance.Type: ApplicationFiled: February 14, 2003Publication date: August 19, 2004Applicant: Qwest Communications International Inc.Inventors: Steven M. Casey, Bruce A. Phillips, Donald Brodigan, Kurt A. Campbell
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Patent number: 6727958Abstract: In a method and apparatus for displaying resized pictures on an interlaced target display system, the contents of an input video source are initially read and decoded to obtain original input picture data and title format information that indicates scan format of the original input picture data. According to the scan format of the original picture data and the identified television system specification of the interlaced target display system, a resizing operation is then performed to resize the original input picture data and obtain resized frames having a frame size sufficient for division into even and odd fields with field size characteristics that comply with the television system specification of the interlaced target display system.Type: GrantFiled: August 20, 1999Date of Patent: April 27, 2004Assignee: Winbond Electronics Corp.Inventor: Rong-Fuh Shyu
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Publication number: 20040075764Abstract: Aspects of the invention for converting interlace formatted video to progressive scan video, may include a color edge detector block (306) adapted to determined edges in interlaced formatted video. A threshold and gain processor block (308) coupled to the color edge detector block (306) may be adapted to quantify a likelihood of motion for each pixel comprising at least a portion of the interlaced scanned video using a motion value. A binder block (310) coupled to the threshold and gain processor block (308) may be configured to combine the motion value for each component of a luminance and chrominance of each of the pixels. A resampler block (314) may be coupled to the binder to determine an actual pixel value. The resampler block (314) may include at least one of a vertical and a horizontal filter adapted to determine an actual value of each of the pixels in at least a portion of the interlaced scanned video.Type: ApplicationFiled: November 6, 2002Publication date: April 22, 2004Inventors: Patrick Law, Darren Neuman
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Patent number: 6697122Abstract: An apparatus for processing a signal in a digital television, and more particularly, an apparatus for adaptively processing an externally-input video signal in a digital television, in which a signal processing route is controlled to automatically determine the type of a video signal, which is input to an external input terminal, and to adaptively process the video signal regardless of whether the signal is an interlaced scanned video signal or a progressive scanned video signal, is provided.Type: GrantFiled: February 23, 2001Date of Patent: February 24, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Byung-hee Kim
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Patent number: 6690426Abstract: The present invention relates to an apparatus and method for converting scanning mode.Type: GrantFiled: August 21, 2000Date of Patent: February 10, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Sung-Soo Kim
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Patent number: 6690427Abstract: The television system for displaying images on a television display has a source of a series of video fields. An active de-interlacer receives first field data from a first field of the series of video fields and second field data from a second field of the series of video fields, and produces de-interlaced data and control data. A format converter has a vertical scaler then directly receives the de-interlaced data and produces vertically scaled data therefrom. The format converter also has a re-interlacer that receives the vertically scaled data and the control data, and produces a re-interlaced frame. A horizontal scaler is connected to receive the re-interlaced frame and to produce therefrom a horizontally scaled re-interlaced frame. Display drivers receive the horizontally scaled re-interlaced fame and produce therefrom television display signals for forming images on a television, a high definition television of other type of television display.Type: GrantFiled: January 29, 2001Date of Patent: February 10, 2004Assignee: ATI International SRLInventor: Philip L. Swan
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Patent number: 6674478Abstract: The invention provides an image processing apparatus and method as well as a providing medium by which deterioration of the vertical resolution is prevented and conspicuous appearance of line flickering is suppressed. In order to convert an interlaced video signal having 525 scanning lines into another progressive video signal having 525 scanning lines while maintaining the image size, in an odd-numbered field, a line after conversion is offset by 0.5 H (H is the distance between horizontal scanning lines of the inputted video signal). Consequently, pixel data of each line Oi are produced from pixel data of two lines Ii and Ii+1 before conversion. As a result, pixels of a line on the boundary between white pixels and black pixels have a gray color. In an odd-numbered field, no offset is given, and pixel data of each line I1 of the field before conversion are set as they are as pixel data of each line Oi of the field after conversion.Type: GrantFiled: August 2, 1999Date of Patent: January 6, 2004Assignee: Sony CorporationInventors: Shinichiro Miyazaki, Akira Shirahama, Takeshi Ohno
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Publication number: 20040001159Abstract: A method for converting video data in a first video format to video data in a second interlaced video format comprising: determining a number of frames of the first video format to map into a frame of the second video format, the frame of the second video format having four fields; determining a number of lines from each of the number of frames of the first video format to be mapped into each of the four fields of the frame of the second video format; selecting the determined number of lines from each of the number of frames of the first video format; determining a sequence for mapping the number of selected lines into the fields of the frame of the second video format; and mapping the selected lines from each of the number frames of the first video format into the four fields of the frame of the second video format according to the determined sequence.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Koninklijke Philips Electronics N.V.Inventors: Richard Chi-Te Shen, Sheau-Bao Ng
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Patent number: 6667773Abstract: An apparatus and a method for format converting a video are provided, in which an input video is format converted in a horizontal direction according to a horizontal output size to store in a line memory and the image stored in the line memory is format converted in a vertical direction according to a vertical output size, such that the amount of line memory required for converting various kinds of videos including the high resolution video to videos of the NTSC or the standard screen quality video are minimized. An input video is format converted in the horizontal direction and a plurality of the divided lines are temporarily format converted by using a single horizontal format converting unit, so that the required hardware becomes reduced.Type: GrantFiled: October 11, 2000Date of Patent: December 23, 2003Assignee: LG Electronics Inc.Inventor: Dong Il Han
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Patent number: 6657674Abstract: An image pickup apparatus operated in mode-1 in which signal-charge that is charged in a CCD imaging device is read out as the output signal of the CCD imaging device once in each field of progressive-scanning, or in mode-2 in which the signal-charge is read out once (viz. during one field) in every two fields of progressive-scanning. And the output signal of the CCD imaging device is written into a memory according to a progressive-scanning synchronizing signal during the intervals when the signal-charge is read out. Then the signal written in the memory is read out, in the mode-1, according to the progressive-scanning synchronizing signal, and, in the mode-2, in such a manner that odd lines are read out in each odd field and even lines are read out in each even field according to an interlaced-scanning synchronizing signal. The above structure enables the image pickup apparatus to have simple circuit, good performance, and to be usable for at least the two modes of the 525/60P mode and the 525/30P mode.Type: GrantFiled: April 1, 1999Date of Patent: December 2, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryoji Asada, Shoji Nishikawa
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Publication number: 20030218692Abstract: A video signal processing device of the invention includes an IP conversion means for converting an interlaced video signal that has been input into a progressive video signal and outputting it, a synthesis means for synthesizing the progressive video signal and a sub-picture or OSD that has been input and outputting the result as a progressive video signal, and a PI conversion means for converting the progressive video signal into an interlaced video signal and outputting it. The progressive video signal and the interlaced video signal are both output. Thus, the picture quality of synthetic sub-pictures or OSDs is not deteriorated and the progressive video signal and the interlaced video signal can be output simultaneously.Type: ApplicationFiled: April 14, 2003Publication date: November 27, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kunihiro Kaida, Koso Takeuchi
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Patent number: 6636187Abstract: A display has a panel, and first and second electrodes. The first and second electrodes define a matrix of cells on the panel. The second electrodes, which correspond to lines of the cells, are scanned to select the cell lines one by one. The first electrodes are driven to set display data for a selected one of the cell lines. The display also has a sequence setting unit for setting sequences of scanning the second electrodes, and a sequence selection unit for selecting one of the sequences that minimizes the current and power consumption of a first-electrode driver without deteriorating the quality of the displayed images.Type: GrantFiled: October 29, 1998Date of Patent: October 21, 2003Assignee: Fujitsu LimitedInventors: Masaya Tajima, Junichi Okayasu, Kiyoshi Takata, Katsuhiro Ishida, Takashi Fujisaki, Yoshimasa Awata, Nobuyoshi Kondo, Shinsuke Tanaka, Naoki Matsui, Fumitaka Asami
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Publication number: 20030174246Abstract: A method for processing an image to convert a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, the non-interlacing scan data including plural pixels, replacing a color space value of a selected one of the pixels in the non-interlacing scan data with a combination of color space values of the selected one pixel and at least one adjacent pixel to obtain a blurringly filtered non-interlacing scan data, scaling the blurringly filtered non-interlacing scan data according to a specific algorithm, and converting the blurringly filtered non-interlacing scan data into an interlacing scan data. An image-processing device for converting a non-interlacing scan data into an interlacing scan data is also disclosed. The device includes a blurring filter, a scaler and a converter.Type: ApplicationFiled: September 3, 2002Publication date: September 18, 2003Applicant: VIA Technologies, Inc.Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
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Publication number: 20030174245Abstract: A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1×N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1×N, respectively, to output a first output clock signal with a frequency F1×N/P1 and a second output clock signal with a frequency F1×N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.Type: ApplicationFiled: August 30, 2002Publication date: September 18, 2003Applicant: VIA TECHNOLOGIES, INC.Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
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Publication number: 20030174247Abstract: An adaptive deflicker method for use in converting a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, wherein the non-interlacing scan data includes plural scan lines, proceeding a deflicker operation on an edge line of the non-interlacing scan data, exempting a non-edge line of the non-interlacing scan data from the deflicker operation, and converting the non-interlacing scan data into an interlacing scan data. In addition, an adaptive deflicker filter for use in converting a non-interlacing scan data into an interlacing scan data is also disclosed. The adaptive deflicker filter includes an edge-line detector and a deflicker filter.Type: ApplicationFiled: November 12, 2002Publication date: September 18, 2003Applicant: VIA Technologies, Inc.Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
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Patent number: 6611286Abstract: In an image sensing apparatus using a non-interlace scanning type image sensing element, in reproducing image signals from a recording medium, in a case where the recorded image signals are sensed in a frame image sensing mode and a moving image output is required, an interpolation filter controller controls an interpolation filter to generate and output field images interpolated between consecutive frame images on the basis of the reproduced even or odd line field image data of the two consecutive frame images, thereby obtaining a smooth moving image.Type: GrantFiled: October 24, 1996Date of Patent: August 26, 2003Assignee: Canon Kabushiki KaishaInventors: Ken Terasawa, Toshihiko Suzuki
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System and method of transmission and display of progressive video with hints for interlaced display
Publication number: 20030137601Abstract: Systems and methods that transmit and display progressive video with hints for interlaced display are provided. The systems and methods may find use in, for example, digital video compression systems. In one embodiment, a system or a method encodes video by following the native frame rate of the source material and, if desirable, embeds hint information for interlaced display into the coded bitstream. Presentation times for coded pictures may be generated using the hint information. The hint information may be used or ignored.Type: ApplicationFiled: January 22, 2003Publication date: July 24, 2003Inventors: Sherman (Xuernin) Chen, Alexander G. Maclnnis -
Publication number: 20030137600Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).Type: ApplicationFiled: January 22, 2003Publication date: July 24, 2003Inventors: Sherman (Xuemin) Chen, Alexander G. MacInnis
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Publication number: 20030112367Abstract: Disclosed is a digital broadcast signal reception set-top box facilitating resolution settings for a digital broadcast signal. The set-top box has a receiver for receiving a digital broadcast signal, a resolution converter for converting the digital broadcast signal to a signal having a predetermined resolution value, an output part for outputting to an external display device the digital broadcast signal having the resolution value converted by the resolution converter, and a controller for controlling the resolution converter and the output part to sequentially output at predetermined time intervals the digital broadcast signal having the different resolution values and to output, in case that a selection command is inputted for the resolution value from external, the digital broadcast signal converted to a resolution value corresponding to the selection command.Type: ApplicationFiled: November 25, 2002Publication date: June 19, 2003Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Gu Kang, Young-Soo Do
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Patent number: 6573941Abstract: A method for format conversion includes providing a first interlaced video signal including non-progressive video of a first resolution, downconverting fields of the first resolution to fields of a second resolution, and combining and interlacing the fields at a third resolution. The video signal is transmitted at the third resolution. The video signal of the third resolution is deinterlaced to form a progressive format video. The progressive format video is converted to the first non-progressive resolution by alternately adjusting position of the progressive format of the third resolution up and down to make upper and lower fields, respectively, of the first resolution for display.Type: GrantFiled: April 22, 2002Date of Patent: June 3, 2003Assignee: Thomson Licensing SAInventors: Donald Henry Willis, Shu Lin
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Patent number: 6570624Abstract: Two images are analyzed to compute a set of motion vectors that describes motion between the first and second images. A motion vector is computed for each pixel in an image at a time between the first and second images. This set of motion vectors may be defined at any time between the first and second images, such as the midpoint. The motion vectors may be computed using any of several techniques. An example technique is based on the constant brightness constraint, also referred to as optical flow. Each vector is specified at a pixel center in an image defined at the time between the first and second images. The vectors may point to points in the first and second images that are not on pixel centers. The motion vectors are used to warp the first and second images to a point in time of an output image between the first and second images using a factor that represents the time between the first and second image at which the output image occurs.Type: GrantFiled: April 20, 2001Date of Patent: May 27, 2003Assignee: Avid Technology, Inc.Inventors: Katherine H. Cornog, Garth A. Dickie, Peter J. Fasciano, Randy M. Fayan, Robert A. Gonsalves, Michael Laird
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Publication number: 20030095204Abstract: An image data conversion processing device including an issue unit, plural line storing units, and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.Type: ApplicationFiled: December 31, 2002Publication date: May 22, 2003Applicant: Fujitsu LimitedInventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
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Patent number: 6567097Abstract: When video data is odd field data, interlaced data for an even field consisting of all black even line data is appended to that video data by an interlaced data appending circuit. On the other hand, when video data is even field data, interlaced data for an odd field consisting of all black odd line data is appended to that video data by the interlaced data appending circuit. Noninterlaced data generated in this way is noninterlaced-displayed on a display monitor such as an LCD, CRT, or the like.Type: GrantFiled: May 24, 1999Date of Patent: May 20, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Tsutomu Iwaki
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Patent number: 6563544Abstract: An apparatus and method for converting computer graphics images into a format suitable for display on a TV. A flicker filter is combined with a vertical scaling filter and/or vertical overscan compensation filter to produce an interlaced image formatted for display on a TV, more efficiently than if the processes occurred sequentially. The apparatus and method are not limited to any particular filter sizes or set of filter coefficient values. The apparatus and method may be used as part of a multimedia computer system.Type: GrantFiled: September 10, 1999Date of Patent: May 13, 2003Assignee: Intel CorporationInventor: Maximino Vasquez
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Patent number: 6563511Abstract: The present invention is a method and apparatus to generate an anti-flickered pixel from a source pixel having a source pixel value in a display memory. The apparatus comprises a plurality of storage elements, a filter, a comparator, and an output selector. The plurality of storage elements store a sequence of pixels in the display memory which includes the source pixel. The filter is coupled to the plurality of storage elements to filter the sequence of pixels. The filter generates a filtered pixel corresponding to the source pixel. The comparator is coupled to the plurality of storage elements to compare the source pixel value with a threshold value. The comparator generates a comparison result. The output selector is coupled to the filter and the storage elements to select one of the source and filtered pixels according to the comparison result. The selected one of the source and filtered pixels is the anti-flickered pixel.Type: GrantFiled: March 5, 1999Date of Patent: May 13, 2003Assignee: Teralogic, Inc.Inventors: Gerard K. Yeh, Anoush Khazeni
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Patent number: 6559839Abstract: A matrix display panel has scan lines that are selected in consecutive order. An interlaced image signal is displayed by the use of one or more output enable signals that enable only every second selected scan line to be driven. A progressively scanned image signal having a frame rate too high to be handled by the matrix display panel is displayed as an interlaced image, by use of the same output enable signals. Consequently, no frame memory is needed for scanning conversion or frame-rate conversion.Type: GrantFiled: March 22, 2000Date of Patent: May 6, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Advanced Display Inc.Inventors: Hiroshi Ueno, Jun Someya, Masaru Nishimura
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Patent number: 6545653Abstract: Signals of odd lines in progressive scanning image signals in a first frame are extracted and displayed along odd lines on a matrix-type display device such as a liquid crystal display panel. Further, signals of even lines in progressive scanning image signals in a second frame successive to the first frame are extracted and displayed along even lines on the display device. Thus, one image of a frame is displayed on the display device in two frame periods so that one of the first and second steps is performed after the other thereof is performed. Alternatively, one of the signals of odd lines are displayed along two successive odd and even lines, while one of the signals of even lines are displayed along two successive even and odd lines. The display methods can be applied to a display panel having a larger number of scanning lines than a number of signal lines.Type: GrantFiled: July 13, 1995Date of Patent: April 8, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Takahara, Tsutomu Muraji
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Publication number: 20030058365Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.Type: ApplicationFiled: September 19, 2002Publication date: March 27, 2003Inventors: Alexander G. MacInnis, Sheng Zhong, Jose R. Alvarez
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Patent number: 6538696Abstract: A CCD converts an optical image of an object formed on its image sensing surface into electrical charges, and sequentially outputs the electrical charges of all of the light receiving pixels in one scanning operation in non-interlaced form. The outputs from the CCD are converted to the digital image signals by an analog-digital converter. A camera signal processing unit processes the digital image signals, thereby generating two streams of signals; one is digital video signals SV1 which are standard digital video signals in interlaced form, and the other is signals SV2 which are not outputted as the digital video signals SV1 out of the digital image signals of all of the light receiving pixels. These two streams of signals, SV1 and SV2, are processed differently depending upon a mode selected by a switch.Type: GrantFiled: November 24, 1999Date of Patent: March 25, 2003Assignee: Canon Kabushiki KaishaInventors: Teruo Hieda, Kousuke Nobuoka, Izumi Matsui, Yukinori Yamamoto
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Patent number: 6538694Abstract: A frame/field converter circuit addition-processes image data constituting respective fields in a ratio corresponding to an image pickup mode or the like and outputs the resulting image data. As a result of this, it is possible to perform addition processing on image data constituting respective fields in an optimum ratio corresponding to an image pickup mode or the like and output the resulting image data. This makes it possible to improve the frequency characteristic and S/N ratio of the image and thereby enhance the quality of the displayed image. A contour compensation circuit performs contour compensation processing with respect to the frequency band of the image data in correspondence with the zoom magnification. As a result of this, it is possible to mitigate the level of the return noises generated in correspondence with the zoom magnification and thereby prevent the deterioration of the frequency characteristic and S/N ratio of the image to thereby enhance the quality of the image.Type: GrantFiled: December 2, 1998Date of Patent: March 25, 2003Assignee: Victor Company of Japan, LimitedInventors: Hiroyuki Miyahara, Kenji Taguchi
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Patent number: 6539109Abstract: An imaging system includes an imager outputting an analog green signal, an analog blue signal, and an analog red signal in a predetermined progressive-scanning format. The analog green, blue, and red signals are converted into parallel-form digital green, blue, and red signals, respectively. A set of the parallel-form digital green, blue, and red signals is converted into a set of a parallel-form digital luminance signal, a first parallel-form digital color-difference signal, and a second parallel-form digital color-difference signal. A signal divider separates the parallel-form digital luminance signal into a first sub parallel-form digital luminance signal and a second sub parallel-form digital luminance signal. The first and second sub parallel-form digital luminance signals are converted into a serial-form digital luminance signal. The first and second parallel-form digital color-difference signals are converted into a serial-form digital color-difference signal.Type: GrantFiled: October 26, 1999Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial, Inc.Inventor: Yoichi Hirose
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Patent number: 6522362Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the line number of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.Type: GrantFiled: July 22, 1999Date of Patent: February 18, 2003Assignee: Fujitsu LimitedInventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
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Publication number: 20030020830Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.Type: ApplicationFiled: May 13, 2002Publication date: January 30, 2003Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
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Patent number: 6489997Abstract: A versatile video transformation device and adaptive image processing methodology thereof to digitally scan convert, that is, reformat TV raster scan video and particularly high definition (HD) and/or digital DTV (particularly those for example in 1920×1080i or 1280×720p format) video data and associated synchronizing signals, for the purpose of making present standard television sets compatible at low cost with the latest advancements in free HD whilst allowing a multitude of other DTV programs and ancillary data to fill to a greater extent the remaining channel allocations by FCC to TV broadcasters.Type: GrantFiled: August 15, 2000Date of Patent: December 3, 2002Inventor: John J. Stapleton
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Patent number: 6459453Abstract: An apparatus and method for displaying a television signal on a computer monitor first receives a selected first field data block of the television signal for display by the monitor. The television signal preferably includes a stream of first field data blocks and second field data blocks that are intended for display by respective first and second sets of lines on the computer monitor. After receipt of the first field data block, an immediately preceding second field data block is faded to produce a faded second block. The faded second block then is displayed on the second set of lines of the monitor, and the first field data block is displayed on the first set of lines of the monitor.Type: GrantFiled: July 15, 1999Date of Patent: October 1, 2002Assignee: 3Dlabs Inc. Ltd.Inventors: James Deming, Jeff S. Ford, Michael Potter
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Publication number: 20020136540Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.Type: ApplicationFiled: December 21, 2001Publication date: September 26, 2002Applicant: DVDO, INC.Inventors: Dale R. Adams, Laurence A. Thompson, Jano D. Banks, David C. Buuck, Cheng Hwee Chee
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Publication number: 20020135696Abstract: A method for properly rendering various types of graphical and video content is disclosed comprising: determining whether a display on which the content is to be displayed is a progressive or an interlaced display; for a progressive display, de-interlacing any interlaced source content, transforming any bitmapped source content to fit the progressive display's resolution and/or scaling factors, and geometrically rendering any source content in a geometric description format into a bitmap image to fit the progressive display's resolution and/or scaling factors; and for an interlaced display, if the interlaced source content is not provided at the interlaced display's resolution and/or scaling factors, de-interlacing the interlaced source content to produce de-interlaced source content, and transforming the de-interlaced source content to fit the interlaced display's resolution and/or scaling factors.Type: ApplicationFiled: February 20, 2001Publication date: September 26, 2002Inventor: Stephen G. Perlman
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Patent number: 6441858Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.Type: GrantFiled: July 22, 1999Date of Patent: August 27, 2002Assignee: Fujitsu LimitedInventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki