Abstract: A method of recording and processing a digital motion image sequence, includes the steps of: recording a digital motion image sequence at a capture frame rate; determining different effective image content change rates as a function of the scene content changes in different portions of the image sequence; and processing the digital motion image sequence to produce a processed digital motion image sequence having portions with the selected effective change rates.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: The present invention provides an image signal processing apparatus and a method thereof which perform double-speed conversion on images subjected to telecine conversion and in which a first field is specified based on difference values between pixel signal levels calculated with respect to respective detected pixels, write pixel positions which are shifted from the positions of the detected pixels in the vector directions of motion vectors are calculated in a field following the first field, the calculated write pixel positions are stored in correspondence with the motion vectors, interpolation pixel data is calculated from pixel data read from the first field in correspondence with the stored write pixel positions and motion vectors, and the calculated interpolation pixel data is written into the write pixel positions.

Abstract: The present invention provides an image signal processing apparatus and a method thereof in which each of the fields forming the unit-frame is specified, with respect to the inputted image signal, based on a difference value calculated in signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field, a motion vector for a field which comes two frames behind the current field is detected, with respect to the detected pixel in the current field, the detected pixel is shifted, with respect to the specified first field, in a direction opposite to the motion vector within the range of the detected motion vector, the detected pixel is shifted, with respect to the specified fourth field, in a direction along the motion vector, and the detected pixels is shifted, with respect to the specified second and third fields, so as to make the pixels gradually closer to the pixel position shifted with respect to the fourth field, in

Abstract: Device and method for converting a format of a video signal in a digital TV receiver is provided. Format conversion can be carried out at one chip of a format converting device, inclusive of conversion of resolution, frame rate, scanning method, aspect ratio, color space, chroma format, and gamma correction. Therefore, the digital TV receiver is made to convert a wide range of video signals inclusive of, not only a digital TV broadcasting signal, but also analog TV broadcasting signal, and computer video signal, at one chip of system block. Moreover, the digital TV receiver is made to provide a variety of standards of format converted video signals, not only to the connected display, but also to other general video signal processing devices.

Abstract: In motion compensated standards conversion, an output video field is constructed from four input fields (two inner fields and two outer fields) by shifting pixel information from an outer field to the output field position in two stages, the first stage using a first motion vector between the outer field and the adjacent inner field and the second stage using a second motion vector being derived from a motion vector pointing from one inner field to the other inner field.

Abstract: An apparatus comprising a de-interlacer circuit, a rate converter circuit and a zoom circuit. The de-interlacer circuit may be configured to generate a first progressive signal having a first rate in response to an interlaced signal. The rate converter circuit may be configured to generate a second progressive signal having a second rate in response to the first progressive signal. The zoom circuit may be configured to generate an output video signal in response to the second progressive signal. The output video signal may represent a portion of the second progressive signal having a frame size equal to a frame size of the interlaced signal.

Abstract: A video signal processing apparatus which performs a frame-rate conversion of a progressive line-scan video signal based on a film source of M film frames per second (wherein M is a natural number) into a video signal in which a same film frame is repeated N times for each 1/M second, and mixes, frame by frame, a video signal of a preceding frame and a video signal of a following frame of the converted progressive line-scan video signal. Thus, the display quality of telecine-converted images can be improved.

Abstract: A digital TV system and a method for supporting a film mode in a digital TV system include generating an original frame from two fields except for repeated fields among 60 fields inputted in an interlaced scanning method if the film mode is detected, and converting the generated frames into 60 frames of a progressive scanning type by repeatedly outputting the generated frames three times or twice by a specified rule, setting an input audio signal to match the film mode in consideration of the number of speakers provided in the digital TV and the number of channels of the input audio signal, and displaying an icon for indicating the film mode on a predetermined position of a TV screen. Thus, a viewer can view the film with a higher picture quality and with reality through the DTV.

Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.

Abstract: A video apparatus is provided with automatic deinterlacing and inverse telecine pre-filtering capability to automatically analyze the frames of the video to determine at least whether the video is one of telecine, non-telecine progressive and non-telecine interlaced formatted, and to automatically reformat the video into a non-telecine progressive format if the video is determined to be one of telecine and non-telecine interlaced formatted.

Abstract: An output stream of the de-interlaced image frames is produced from an incoming stream of interlaced image fields, where the interlaced image fields include complementary pairs of fields, which together comprise a frame. An input buffer includes field buffers storing the incoming stream of interlaced image fields. Field match detection logic is coupled to the input buffer, and detects matching fields in field buffers storing fields from the incoming stream separated by one other field. De-interlace logic is coupled to the input buffer and reads complementary pairs of fields from the input buffer and outputs de-interlaced frames. Control logic causes the current field from one of the field buffers to be paired with a complementary field selected from one of two fields stored in adjacent field buffers. The control logic sets a mode for the de-interlace sequence, including a standard mode and a 3:2 pulldown mode.

Abstract: A video signal processing apparatus in which an input video signal is written in a frame memory on a line sequential scanning frame unit base in synchronism with a first vertical synchronizing signal and which the line sequential scanning video signal written in the frame memory is read out in synchronism with a second vertical synchronizing signal. The second vertical synchronizing signal having a frequency different from a frequency of a first vertical synchronizing signal is generated in synchronism with the first vertical synchronizing signal of a starting frame of five frames forming a pattern after the conversion in the 2-3 pulldown conversion system when it is judged that the input video signal is based on a telecine-converted video signal.

Abstract: Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

Abstract: A method for multiplying the frame rate of an input video signal having a line rate fHin and a frame rate fVin, comprising the steps of: propagating the input video signal through just enough memory to delay the input video signal by a fraction of a frame period 1/fVin; speeding up the delayed video signal to a first line rate faster than fHin; speeding up the input video signal to a second line rate faster than fHin; supplying the speeded up video signal and the delayed speeded up video signal sequentially, one line at a time; and, writing the sequentially supplied lines into a liquid crystal display at the faster line rate, thereby writing at least some of the lines multiple times within each the frame period. A corresponding apparatus can comprise: a partial frame memory; two speedup memories; a multiplexer; and, a source of clock and control signals.

Abstract: A data processing apparatus for data processing an audio signal includes an input terminal (1) for receiving the audio signal, a 1-bit A/D converter (4) for A/D converting the audio signal to for a bitstream signal, a prediction unit (10) for carrying out a prediction step on the bitstream signal to form a predicted bitstream signal, a signal combination unit (42) for combining the bitstream signal and the predicted bitstream signal to form a residue bitstream signal, and an output terminal (14) for supplying the residual bitstream signal.

Abstract: A first motion vector is estimated by using a first frame and a second frame that follows the first frame. A support frame is generated from at least either the first or the second frame by using the first motion vector. The support frame is divided into a plurality of small blocks. Motion vector candidates are estimated by using the first and second frames, in relation to each of the small blocks. A small block on the first frame, a small block on the second frame and the small blocks on the support frame are examined. The small block on the first frame and the small block on the second frame correspond to each of the motion vector candidates. A second motion vector is selected from the motion vector candidates, and points the small block on the first frame and the small block on the second frame which have the highest correlation with each of the small blocks on the support frame. An interpolated frame is generated from at least either the first or the second frame by using the second motion vector.

Abstract: A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.

Abstract: It is determined whether each block (51) including a plurality of pixels extracted from a basic field (30) has an edge or not, and then which state, stationary or non-stationary, each of the pixels forming together the block (51) determined to have an edge is. There is calculated an absolute value of a difference between a pixel determined to be non-stationary and a pixel (91 or 92) in each pixel position in a reference field (40) or pixels (82 to 85) included in the reference field and adjacent to the non-stationary pixel, and a correlation is found between such pixels in consideration according to the calculated difference absolute-value. A motion vector is determined by the block matching method according to results of the determination, and allocated to each of the pixels. Thus, the motion vector of each block is corrected to an accurate one of each of the pixels.

Abstract: A method and apparatus for automatically tuning the output line rate thereof and a display controller provided with the same. The display controller of the present invention provides a display controller having a line buffer, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

Abstract: A signal processing unit for a digital TV system comprises a first device which acts on a video signal with graphical picture elements and text characters. A second device performs frame-rate conversion on the output of the first device. The output of the second device drives a display driver.

Abstract: A source original HD video signal S1 of 24-frame rate is subjected to 2-3 pull-down process, thereby generating a 30-frame rate SD video signal S5. The 24-frame rate time code added to the source video signal S1 is described in the user area of the VITC data (201) inserted into the 30-frame rate video signal. The sequence number 301 indicating the order of fields in one sequence of the pull-down process is described in the user area of the VITC data (201) inserted in the 30-frame rate video signal. Inverse 2-3 pull-down process is performed on the 30-frame rate video signal recorded on tape, by using the sequence number 301 described in the user area of the VITC data, thereby generating a 24-frame rate video signal. The 24-frame rate video signal is recorded on a hard disc. A nonlinear editing device (19) uses the 24-frame rate time code inserted in the user area of the VITC data, thereby generating an edition list that will be supplied to an on-line editing system.

Abstract: Provided are a method and apparatus for performing frame rate conversion. With the apparatus, current video data and previous video data are compared with each other and a motion vector is detected based on the compared result; an error in the detected motion vector is compensated for based on adjacent motion vectors; and one of the detected motion vector and a compensated motion vector is selected as a final motion vector, based on errors in the detected and compensated motion vectors. Accordingly, a more reliable motion vector can be selected to perform frame rate conversion, thereby more naturally depicting an image.

Abstract: An image display method including dividing an original image for one frame period into a plurality of subfield images, arranging the subfield images in a direction of a time axis in an order of brightness of the subfield images, and displaying the arranged subfield images in the order of the brightness.

Abstract: A telecine conversion method detecting apparatus which determines that an input video signal is a telecine converted video signal generated from a movie film in accordance with a 2-3 pull-down method when detecting that an inter-frame difference accumulated value of a current field of the input video signal is equal to or less than a threshold value for still field determination, that each inter-frame difference accumulated value of four fields preceding the current field is equal to or greater than a threshold value for motion field determination, and that the inter-frame difference accumulated value of the current field is less than each corrected value calculated by multiplying each of the inter-frame difference accumulated values of the four preceding fields by a predetermined coefficient.

Abstract: The invention relates to a method for encoding video signals corresponding to a sequence of frames constituted either from video-type images or film-type images. These film-type images are obtained by means of the 3:2 pull-down technique involving a subdivision of each film frame into two fields and a duplication of two fields within each group of four subdivided frames. The encoding step of the signals is preceded by a preprocessing step that includes thresholding the eight absolute values of the successive pixel-to-pixel differences between fields of the same parity. Measuring the density of “1” (resp. “0”) per block of m×n pixels of the field structure leading to mark each pixel as 1 or 0. Detecting in any group of ten successive fields within the preprocessed signals thus obtained, the film pattern formed by the duplicated fields.

Abstract: An image signal processing apparatus according to the present invention receives an image signal inputted thereto that is generated by subjecting a telecine-converted image to double speed conversion, in which signal one film frame is formed by four fields, identifies a first field on the basis of a difference value calculated between pixel signal levels, and shifts the position of a detected pixel in a vector direction of a motion vector such that an amount of shift is progressively increased as transition is made from the identified first field to the subsequent fields.

Abstract: An apparatus and a method for converting image signals from an interlaced scanning format to a progressive scanning format are disclosed. Additionally, an apparatus and a method for changing a vertical scanning rate of progressively scanned image signals are also disclosed. Field motion estimator estimates field motions between a current field and reference fields to find an optimal reference field. Then a field motion compensator restores a missing line of the current field using information given from the optimal reference if the optimal reference field unevenly matches to the current field. Otherwise, a linear interpolator restores the missing line of the current field by linearly interpolating lines located adjacent to the missing line in the current field. Furthermore, a frame motion estimator estimates frame motions between adjacent frames using the progressively scanned image signals and field motions estimated in the field motions estimator.

Abstract: The circuit includes a motion detector including a first device for producing pixel motion signals, which have a first state for each pixel which is found to have moved and a second state for each pixel which is found to have been stationary, and a second device for correcting the pixel motion signals in order to produce motion values in such a manner that a state of a pixel which differs from matching states of adjacent pixels is ignored.

Abstract: A format converter which performs frame rate conversion and de-interlacing using a bi-directional motion vector and a method thereof are provided. The method includes the steps of (a) estimating a bi-directional motion vector between the current frame and the previous frame from a frame to be interpolated; setting the motion vector of a neighboring block that has the minimum error distortion, among motion vectors estimated in step (a), as the motion vector of the current block; and (c) forming a frame to be interpolated with the motion vector set in step (b).

Abstract: Disclosed is a video restoring apparatus and method thereof enabling to improve a video mode by interpolating field data. The present invention includes the steps of: identifying whether a scene on an image sequence is changed by receiving field data; detecting whether a 3:2 pull-down mode exists in the image sequence; generating a first interpolated frame by interleaving a field to be interpolated and adjacent fields each other when there is the 3:2 pull-down mode; generating a second interpolated frame by de-interlacing the field to be interpolated and the adjacent fields each other when there is not the 3:2 pull-down mode, and selectively outputting one of the first and second interpolated frames.

Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Abstract: A deinterlacing system which converts an interlaced video stream into a progressive video stream is disclosed. The deinterlacing system includes a field assembly responsive to a last field, a next field, a current field and progressive source phase and operative to develop a progressive output frame, a source detection module responsive to last, next and current fields and operative to develop a progressive source phase and a progressive source detected and an intra-frame deinterlacer responsive to the progressive output frame and the progressive source detected and operative to develop a progressive frame output.

Abstract: An inverse telecine conversion arrangement and methodology that accurately judges whether entered moving television picture information is originally a television material or a cinematic material, and performs inverse telecine conversion based on a result of the judgement. The apparatus includes a structure judging portion which judges whether a structure is a frame structure or a field structure based on adjacent pieces of field image information in the received moving television picture information which are adjacent to each other in terms of time; and a pattern judging portion which determines that the received moving television picture information has a predetermined pattern based on a pattern in which a field structure and a frame structure judged by the structure judging portion are successive to each other, and when the pattern judging portion recognizes the predetermined pattern, a corresponding piece of the received moving television picture information is inverse telecine converted.

Abstract: There is provided a signal processing device in which its structure is simplified and a source subjected to a pull-down processing is detected at high precision. The signal processing device includes a comparison portion and a detection portion in which fields constituting a signal source are successively inputted, two fields are compared with each other, and it is judged whether or not there is a motion between the two fields, and a logic block for shifting a state on the basis of a judgement result as to whether or not there is a motion in the detection portion and for controlling judgement characteristics of the detection portion on the basis of the shifted state.

Abstract: A method of generating an interpolation image includes inputting a first reference image, a second reference image and a third reference image of a video signal that continue in terms of time, generating a first interpolation image corresponding to a position of the second reference image from the first reference image and the third reference image, computing a correlation value expressing a correlation level between the second reference image and the first interpolation image, generating a second interpolation image corresponding to an interpolation position between the second reference image and the third reference image, and interposing the second interpolation image in the interpolation position when the correlation value is more than a threshold.

Abstract: A cost-efficient digital parallel processor to improve throughput and offer a variety of output formats in film conversion is described. Image pixels on film are translated into electrical signals by photosensitive detectors. The electrical signals are digitized by analog-to-digital converters and thereafter provided to a digital parallel processor for film conversion functions. The digital parallel processor includes two or more groups of circuit elements to facilitate parallel processing. Each group of circuit elements can process a different set of image pixels simultaneously. In addition, image pixels belonging to the same set can be processed in parallel. This two-dimensional parallel processing structure facilitates faster than real-time film conversion sessions. A supervisor control circuit monitors and controls the sequence of film conversion functions. The output of the digital parallel processor is provided to a formatter which manipulates the data to conform to one or more standard formats.

Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.

Abstract: Disclosed is a frame interpolating apparatus and a method thereof used at a frame rate conversion. The frame interpolating apparatus includes a calculation unit for performing a SAD Map calculation among inputted video signals with respect to a previous frame and a next frame and performing block matching, a determination unit for determining from the block-matched frame whether a video is repeated periodically and is changing fast, and an interpolation unit for selectively calculating a pixel value of an interpolated frame according to a determination result of the determination unit. Accordingly, the interpolated frame is vivid and clear, hence, removing the conventional blurring problem.

Abstract: Nowadays, continuous media data processing is performed more and more by programmable components, rather than dedicated single-function components. To handle such data appropriately, a system must guarantee sufficient system resources for processing. The method according to the invention proposes scalable motion compensated up-conversion of the frame rate of video sequences. By computing suitable quality measures for the algorithms (404) that perform the up-conversion (402), the method according to the invention allows to predict the required resources given an input video (406). Furthermore, the visual quality of the output video sequence is predicted. Based upon these predictions, the method selects the best algorithm to perform the up-conversion thereby allowing an optimal resource utilization of the system, for example a programmable platform for media processing.

Abstract: Disclosed is an image processor with frame-rate conversion that can perform frame-rate conversion of a video signal with a single frame memory. In this image processor with frame-rate conversion, input digital video signals are successively written on the frame memory with a timing synchronized with a vertical synchronization signal included in the input digital video signals. During this time, a frequency signal that mainly consists of a train of N pulses for every M cycles of the vertical synchronization signal is generated as a vertical synchronization signal being rate-converted, and the input digital video signals stored in the frame memory are read out in the order in which they were written with a timing synchronized with the vertical synchronization signal being rate-converted. Such a configuration makes it possible to convert the input digital video signals to video signals having a desired vertical synchronization frequency with use of a single frame memory, thereby converting frame-rate.

Abstract: A video signal processing apparatus in which an input video signal is written in a frame memory on a line sequential scanning frame unit base in synchronism with a first vertical synchronizing signal and which the line sequential scanning video signal written in the frame memory is read out in synchronism with a second vertical synchronizing signal. The second vertical synchronizing signal having a frequency different from a frequency of a first vertical synchronizing signal is generated in synchronism with the first vertical synchronizing signal of a starting frame of five frames forming a pattern after the conversion in the 2-3 pulldown conversion system when it is judged that the input video signal is based on a telecine-converted video signal.

Abstract: Displaying a subject image on a browser in accordance with the aspect ratio of the subject image, with reduced scan line interference at a time exposure, as well as transmitting a high-quality image with easy compression processing.

Abstract: A film mode detection method using a periodic pattern of a video sequence comprises the steps of: computing every absolute value of differences between every pair of corresponding pixels in two fields which are arranged within a predetermined distance on a time line; comparing a sum of the absolute value of differences between every corresponding pixels in two fields with the first predetermined threshold value M1 and limiting the sum to the first threshold value if the sum is greater than the first threshold value; filtering the video sequence and calculating a power of the filtered sum; and comparing the calculated power with the second predetermined threshold value M2 so as to determine the signal as a film mode if the power of the sum is greater than the second threshold value.

Abstract: A method and apparatus for converting between different video formats, which provide smooth video motion by eliminating unnatural effects which could be introduced in the process of video format conversion. A frame interpolator produces interpolated frames from a first video signal given in a first video format by using motion vectors of the first video signal. From the interpolated frames, a video signal generator produces a second video signal in a second video format that is incompatible with the first video format.

Abstract: A method and system for edge-adaptive frame rate up-conversion are disclosed.

Abstract: An image format conversion apparatus including a 3:2 pull-down detection part determining whether a current field out of plural fields continuous in time is an image of a 3:2 pull-down format produced by a 3:2 pull-down process; a scroll text/graphic data detection part determining whether scroll motions exist on the current field; a 3:2 pull-down compensation part calculating interpolation values for pixels of the current field to be interpolated by using a 3:2 pull-down interpolation method; an IPC part calculating interpolation values for pixels of the current field to be interpolated by using a second interpolation method; and an output selection part for selectively outputting either the interpolation values of the 3:2 pull-down compensation part or the interpolation values of the IPC part based on results of the determinations of the scroll text/graphic detection part and the 3:2 pull-down detection part.

Abstract: The invention relates to a method and a device for movement vector assisted conversion of a first video signal containing a first image sequence at a first frequency into a second video signal containing a second image sequence at a second frequency. At least some of the images in the second image sequence, which are phase shifted in relation to the first image sequence, are formed by a interpolation of images in the first image sequence in such a manner that, pixel points of at least one first image and a second image are filtered by means of a median filter, for a pixel of an image in the second image sequence median. The median filter is an adoptively weighted median filter.

Abstract: Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

Abstract: In an audio-video production system, frame rate transformation is performed so as to simplify editing and/or compression. In the preferred embodiments, the frames surrounding the selected edit points at a scene change are buffered to permit reconstruction, if necessary, to produce “pure” rather than mixed frames. The frames then are intelligently selected or constructed using techniques such as field or frame dropping, frame repeating, and so forth, as necessary. This technique may be applied both to the series of frames leading up to an edit point, and also to the series of frames which follow the edit point.