Abstract: An apparatus and a method of controlling image display in an image display apparatus having a panel and wherein an image output is synchronized to a frame synchronization signal of an input signal. The method includes determining whether or not an input synchronization signal is an abnormal synchronization signal, processing the abnormal synchronization signal if the input synchronization is the abnormal synchronization signal, and removing damaged frame data if the abnormal synchronization signal is processed.

Abstract: The present invention intends to provide a display position control apparatus which can prevent a position control signal to control a display position of an image from being unstable and can display the image with high image quality. A delay signal having a phase difference in a match state with reference to a vertical sync signal is generated. Whether a phase relation between the vertical sync signal and a horizontal sync signal is in a mismatch state is detected. When it is detected that the phase relation is in the mismatch state, a display position control signal is generated on the basis of the vertical sync signal and the delay signal. When it is not detected that the phase relation is in the mismatch state, the display position control signal is generated on the basis of the vertical sync signal and the horizontal sync signal.

Abstract: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: An object is to provide a frame number detecting device having a frame counter which is less apt to output a wrong frame number even if a sync signal type was erroneously detected from a DVD etc. and the combination of variation of the sync signal types corresponds to an existing frame number. A sync number encoding portion (6) specifies a read frame number and provides it as an output. First and second frame counters (7) and (13) run by themselves and output their count numbers. A state detecting counter (9) causes a state variable to go up/down according to whether a signal (S5) and a signal (S7) agree with each other. When the state variable is at its lowest value and the sync number encoding portion (6) was able to specify the frame number, the signal (S5) is reflected in the signal (S7). When the state variable has reached its highest value, the signal (S7) is reflected in a signal (S13).

Abstract: A method for detecting a synchronous signal contained in an input image signal is provided. In the method, horizontal and vertical periods are established during which horizontal and vertical synchronous signal pulses contained in the input image signal are counted, respectively. Then, minimum and maximum horizontal values which correspond to the horizontal synchronous signal pulses contained in the horizontal period are established, and minimum and maximum vertical values which correspond the vertical synchronous signal pulses contained in the vertical period are established. Afterwards, the horizontal and vertical synchronous signal pulses are counted during the horizontal and vertical periods to respectively obtain first and second counted values.

Abstract: Writing of a second field is started at a time point when writing of a first field has been completed, while information written in the first field is held. Writing of a first field of the next frame is started at a time point when the writing of the second field has been completed, while information written in the second field is held. This driving method can attain high vertical resolution.

Abstract: The invention provides a synchronizing conversion apparatus wherein outpacing compensation can be executed with a circuit construction including a comparatively small number of components. A read control circuit produces a read control signal including a read address and a read timing based on an outpacing detection signal from a phase comparison circuit, which is generated taking a time required for processing of a memory access arbitration circuit into consideration, and a scene change detection signal from a scene change detection circuit. The read control signal is outputted to the memory access arbitration circuit. The memory access arbitration circuit arbitrates requests from a write control circuit and the read control circuit to control writing into and reading out from a frame memory.

Abstract: According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Abstract: An image frame synchronizing apparatus and a method thereof which receive image signals from a plurality of image signal sources, detect a synchronous signal from the image signal of one image signal source among the plurality of image signal sources, and synchronize the image frames of image signals from the image signal sources according to the frame synchronous signal, in order to display the images in one frame unit.

Abstract: The inventive system mainly includes a synchronization marker at a transmitting site and a synchronization forcer at a receiving site connecting to each other via computer networks. The synchronization marker performs the sequential mark marking of frames per every marking interval. The synchronization forcer regulates the play time of the audio signals and their corresponding video signals according to their sequential marks. The inventive system can determine precisely about the minimum marking interval yielding a bounded skew requirement. Consequently, the invention satisfies any given skew requirement under various buffer size and traffic arrivals while imposing minimal overhead.

Abstract: This invention enables coded audio data to be reliably decoded even if an audio signal coded in blocks not in synchronism with the frames or fields of a video signal is decoded on the basis of these frames of fields. By filling an integral number of coded audio blocks in the period of time corresponding to one frame or field of the video signal, this invention forms an array of coded audio blocks in synchronism with the frames or fields of the video signal before transmission. This avoids separating a coded block in transmitted data at a frame or field boundary, and enables the coded audio data to be reliably decoded so as to prevent the occurrence of a period of time in which decoded data is missing even if a switching operation is carried out on the basis of the frames or fields of the video signal.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: The frame synchronizer outputs, when reading out each of the video signals stored in a plurality of frame memories provided in a frame synchronizing circuit one by one, a read control signal from a video signal read control circuit for controlling the frame synchronizing circuit in such a manner as to read out a video signal of a frame other than that of a target frame which was to be read out otherwise, in case the input/output frame phase difference output from an input/output frame phase difference detecter comes up to an amount of one frame.

Abstract: Isochronous data packets transmitted within a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus are stamped with a presentation time stamp value determined according to a computed packet rate for the data. For the case where the presentation time stamp field of a first packet of a second frame of data for transmission in the digital network is set with the presentation time value, the packet rate may be computed by measuring a difference between a desired presentation time value of a first packet in a first frame of the data and an actual transmission time of the first packet of the first frame. The first frame preceding the second frame in time of transmission within the network.

Abstract: A digital video logging system including a logging apparatus able to synchronize at least two digitally formatted video input and digital storage apparatus to store the digitally formatted input is provided.

Abstract: A technique is provided for calculating the time offsets between different video cameras and re-synchronizing the captured frames in a post-processing manner, thus eliminating the necessity of an explicit common clock for synchronization. This approach allows effective synchronization of frames from different cameras so that a multi-camera system can be used to more accurately analyze a subject under observation.

Abstract: A delay tracker for a signal processing system, which delay tracker utilizes a special code or pulse on the active portion of the tracked signal with the system including a pulse detector later in the system subsequently recognizing the special code or pulse in order to identify such signal and ascertain any delays associated with the signal for use by the system including possible resynchronization of the tracked signal with another signal associated therewith.

Abstract: This invention is an apparatus and method for processing television signals and in particular high quality video type signals in analog or digital form. The preferred embodiments utilizes digital storage along with oversampling, interpolation and various filtering in recursive and nonrecursive form to provide fixed or variably delayed output video signals wherein the artifacts and distortion of the video is kept to low levels.

Abstract: A coded signal synchronizing device includes a first and a second signal synchronizing circuit. The first and second signal synchronizing circuits respectively feed a first and a second coded signal to a coded signal processor while synchronizing them to each other in accordance with a reference synchronizing signal. A synchronization control circuit compares the phases of frame synchronizing signals output by the decoding of the coded signals and the phase of the reference synchronizing signal. So long as a phase difference between either one of the frame synchronizing signals and the reference synchronizing signal lies in a preselected range, the synchronization control circuit reads the coded signal sequentially stored. If the phase difference is smaller than a first preselected value, the synchronization control circuit repeatedly reads an I (Intra-coded) picture two times.

Abstract: A system for dynamically determining and introducing time delay values for synchronizing different data signals. For transmitting the data signals, encoding time delay is measured in one encoder, a target encoder time delay value is determined, and the target encoder time delay value is utilized in another encoder to delay transmission of one data signal relative to the transmission of the other data signal. When encoded data signals are received and processed for presentation, the time required to decode a first data signal in a first decoder is measured, a target decoder time delay value is determined based on the time required to decode the first data signal, and the target decoder time delay value is utilized to delay presentation of a second data signal relative to the presentation of the first data signal.

Abstract: NTSC signals have a frame rate of 29.97 frames per second. In SDI, audio data is sampled at a rate 30n where n is an integer, e.g. 48K samples per second. Thus there are 1601.6 samples per frame. Although there are an integer number 8008 samples per five frame sequence, two frames have 1601 samples and 3 frames have 1602 samples. This creates a variable storage requirements from frame to frame and causes problems in editing. The SDI audio data is separated from associated video and decimated by a factor h, where h=4 for example in a signal processor 2, 3, 4, 5 and 6. The decimated data is written into a FIFO circuit at the rate 30n/h synchronously with frame timing under the control of a frame reference generator 10, 9. A fixed integer number n/h of samples is written into the FIFO 7 in each frame under the control of a write control circuit 8. n/h=400 for example, where n=1600 and h=4. Any additional sample in each frame is dropped. The 400 sample frames are stored on a disc 14.

Abstract: Methods and systems are provided for generating a real time multimedia data stream with accurate time stamps for decoding. Time stamps are provided which compensate for a difference between a video frame rate corresponding to a video frame within the real time multimedia data stream and the oscillator clock. The video frame is then stamped with the time stamp which compensates for the difference between the theoretical presentation time stamp corresponding to the video frame and the oscillator clock.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: A system and method for obtaining and maintaining synchronization to a digital signal containing framing. The method searches for a synchronizing pattern and maintains a confidence counter indicative of the success in finding the synchronization pattern where expected. The confidence counter can be used to indicate when the system is locked to the framing of the digital signal and when resynchronization needs to occur.

Abstract: An image and sound synchronizing reproduction apparatus includes a reference time calculation circuit for calculating a reference time in response to a data amount of decoded sound data, a delay detecting circuit calculating number of image frames to be processed practically in the decoding process in response to the reference time and comparing the number of image frames with number of frames practically processed in the decoding process, for detecting a delay of image decoding process, a frame-removing control circuit for performing a discriminating process of frames to be omitted the decoding process in response to the number of delay frames detected by the delay detecting circuit, and an image data input control circuit for performing an omission to read compressed image data corresponding to the frames discriminated by the frame-removing control circuit, controlling finely the image and sound synchronizing reproduction regardless of the structure of compressing coded data.

Abstract: The invention is a method and apparatus for processing an MPEG-like bitstream comprising information frames having associated timing parameters. The method and apparatus identify one or more non-referential information frames containing at least a threshold number of bits, remove one or more of the identified non-referential information frames and modify the timing information associated with each information frame following the one or more removed information frames.

Abstract: Writing of a second field is started at a time point when writing of a first field has been completed, while information written in the first field is held. Writing of a first field of the next frame is started at a time point when the writing of the second field has been completed, while information written in the second field is held. This driving method can attain high vertical resolution.

Abstract: A system and method for a generating a data stream for encoding by combining data from a multiple of sources. In order to maintain a continuous phase in the combined data stream, any phase differentials between the data supplied from the multiple sources are eliminated upon combination of the source data. The phase differential between the data from any two different sources is eliminated by trimming data from one of the sources such that when the trimmed data is combined with the data from the other source the resulting combined stream has a continuous phase.

Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.

Abstract: In an error data removing apparatus and method by decoding delay in a DTV system which employs a decoder of the VSB standard, respective segments or respective fields are divided into area 1 and area 2 using a starting point of decoded data as a reference to provide the decoded data of said area 1 section without involving delay and provide the decoded data of said area 2 section by delaying as long as a sync signal. A memory is utilized as the decoded data delay apparatus, and at this time, a value of a counter used for generating an address for reading/writing of the memory is utilized to delay the segment sync signal and field sync signal as required without separately using flip-flop or memory.

Abstract: A digital pulse filtering circuit for processing composite sync signals is provided. The digital pulse filtering circuit can determine the polarity of an input composite sync signal composed of a horizontal sync signal and a vertical sync signal. The horizontal sync signal is a first periodic pulse train having a first pulse width, while the vertical sync signal is a second periodic pulse train having a second pulse width. The digital pulse filtering circuit includes a horizontal sync filter for filtering out all pulses in the input composite sync signal that have a pulse width less than the pulse width of the horizontal sync signal; and a vertical sync filter, coupled to receive the output of said horizontal sync filter, for filtering out all pulses in the output of said horizontal sync filter that have a pulse width less than the pulse width of the vertical sync signal. The output of said indicating the polarity of the input composite sync signal.

Abstract: This invention is a method and apparatus for synchronization high quality video like signals. The preferred embodiment is described to synchronize a plurality of mutually unsynchronized video signals as well as passing one or more associated secondary signal with each video signal with a corresponding delay. The selection of one of a plurality of reference signal candidates is shown along with the use of the input signal to provide a fixed delay.

Abstract: Vertical and horizontal sync signals are separated from an NTSC signal inputted from an outside by an external input circuit and a luminance signal (Y) and chrominance signals (B-Y, R-Y) are extracted and converted into RGB data. External RGB data and RGB data formed by a software are processed and the resultant data is supplied to an output converting circuit. The RGB data is converted into analog signals of the luminance signal and chrominance signals of a television signal by using individual system clock signals and outputted. A clock generating circuit generates two kinds of dot clocks which are used for the output converting circuit. The dot clock which is generated from the clock generating circuit and is used for conversion of the luminance signal is phase matched so as to follow a jitter of a horizontal sync signal (H) separated by an external video input circuit.

Abstract: A click noise is prevented from being generated in audio signals when reading of memory jumps. Separated audio data is supplied to a sampling rate converter and converted into an audio signal of a baseband by a D/A converter. This audio signal passes through a low-path filter and is reconverted into a digital audio signal by an A/D converter in accordance with a sampling signal of the rate of the self system. As a result, audio data which is transformed into the rate of another system can be converted into audio data of the rate of the self system.

Abstract: An input video signal is written into alternate field memories M1 and M2, according to a timing clock from an input video clock generator. A display video signal is alternately read from those field memories, according to a timing clock from a display video clock generator. In switching a read memory, an address observation circuit judges whether or not a read/write address passes by a write/read address, referring to the condition of reading and writing operations. In this event, the circuit makes a judgement, based on the lag between a vertical synchronizing signals of an input video signal and of a display video signal, and a change of the lag with time. If it is judged that one address will pass by the other, the same read/write memory is again accessed for reading/writing. With this arrangement, there is provided a circuit having a relatively simple structure for preventing a match of read and write addresses.

Abstract: A delay tracker utilizes a special code on the tracked signal in order to recognize such signal and ascertain any delays associated therewith.

Abstract: A subpicture image signal vertical compression circuit for vertically compressing subpictures operating at respective synchronous timings different from that of the main picture when a plurality of image signals having respectively different synchronizations are displayed on an image display device. Depending on whether the field polarities of main and sub pictures are the same or not, the subpicture image signal vertical compression circuit generates suitable offsets for the first and the second fields to adjust the phases and prevent the inversion of the scan order in the vertical direction, at the first field and the second field of subpicture signal, after the phase adjustment to obtain a subpicture image with natural motion in the vertical direction.

Abstract: A device for storing picture information displayed on a television screen consists of a storage medium made of a photosensitive material which may be secured to the surface of the screen by an active adhesive layer on the screen.

Abstract: The present invention is a means and method for synchronizing closed free-running systems, such as graphics systems, with no external synchronization signals required. Video games and most computer display controllers are closed free-running systems. Because most such systems have the means to switch between an interlaced and non-interlaced operation, and because interlaced and non-interlaced modes have a relative timing variation, the timing between two or more such closed free-running systems can be synchronized. This method allows synchronization with an imprecise timing reference. The vertical display timing is the free-running oscillator and the interlaced/non-interlaced mode transition is used as the timing adjustment means. The actual arrival time of data in a communication medium connecting two systems being synchronized is used in relation to an expected arrival time to provide the clock reference.

Abstract: Input image data and audio data divided into a plurality of portions are continuously recorded in a solid-state memory. When the audio data is to be reproduced in units of the portions, a reproducing start address of each portion of the audio data is changed in an order different from that in recording, thereby reproducing the audio data. The image data is divided into a plurality of portions corresponding to the plurality of portions of the audio data. The image data is reproduced in units of the portions. At this time, the reproducing start address of each portion of the image data is changed in an order different from that in recording, thereby reproducing the image data. With this arrangement, even when the image and audio data are reproduced in an order different from that in recording, the reproduced audio data can be confirmed.

Abstract: The disclosure relates to a synchronization device that includes two parallel memory areas, a unit for determination of write states that depends on the phase deviation between the input video signal and the synchronization signal, a write management unit that determines, when it receives a write image pulse, the memory (or memories) to be used for the next write depending on the write state and the memory that is currently being read. The two memories are read sequentially and alternately, whereas the memory(ies) used for each write is variable and determined automatically. The invention enables video signals to be synchronized with respect to a synchronization signal with a frequency deviation tolerance of up to 33%.

Abstract: A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal.

Abstract: This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

Abstract: A portable and economical telecine machine for rapidly converting images recorded on motion picture film to electronically available and manipulable video signals with extremely high frame accuracy and temporal correspondence. On a commercially-available flatbed editing table, motion picture film passes through a light-tight enclosure surrounding a strobe, the film, a mirror, and a video camera. When the film is centered between the strobe and the camera, the strobe flashes to optically transmit the film image to the video camera. The film is then advanced exactly one single film frame to record the next image. In this way, film images are recorded frame by frame by a video camera, converting the film images into video signals. Passage of the film is monitored by a film sprocket coupled to a bi-phase encoder. When the image is optically transmitted to the camera, it is recorded in the two next available video fields by the video camera.

Abstract: In a Video processor, an analog composite video signal is converted by an A/D converter (10) to a digital bit sequence in response to a system clock pulse. By using the system clock pulse and horizontal and vertical synchronizing pulses separated from the composite signal, a horizontal blanking interval and a vertical blanking interval are detected by control circuitry (21.about.24) and the read/write operations of a field memory (12) are disabled during the horizontal and vertical blanking intervals and enabled at other times. The picture information from the memory is converted by a D/A converter (13) to analog form in response to the system clock pulse. A multiplex of a digital pedestal level signal and a digital synchronization level signal is supplied to the D/A converter (13) when the memory is disabled.

Abstract: A display apparatus wherein a video signal of a child picture read out at a double speed is inserted accurately with a high resolution into a parent picture of another video signal having a double frequency. Control signals for designating a write area and a read-out area of a four field sequence memory provided for forming a double speed field frequency is formed in accordance with odd/even number field discrimination signals for write and read-out video signals, a vertical synchronizing signal prior to double speed conversion and a double speed synchronizing signal for a parent picture so that, even when the parent picture is scrolled, passing of the read-out side memory area does not take place. Where the parent picture is formed from a video signal of the interlace system by a line double speed, the double speed child picture video signal is delayed, upon reading out in an even-numbered field, by one horizontal scanning period so that lines may be overlapped between the parent and child pictures.

Abstract: Before transmission of moving image data, the period of a frame of the moving image data is counted using a clock signal used for the transmission to produce a frame count. The moving image data is then transmitted along with the frame count so that it can correctly be timed in frames at receiver.

Abstract: This invention is a method and apparatus for synchronization of high quality video like signals. Full sync tip to peak white video is digitized in the preferred embodiment along with oversampling and interpolation so that errors are kept to unexpected low levels. The preferred embodiment is described to pass one or more secondary signal with the video signal in a separate parallel but time related path. The use of the input signal for a reference to allow a fixed delay is also shown.