Abstract: In monitor circuitry, a simple circuit separates out the horizontal synchronization pulses from the composite synchronization signal and removes undesired horizontal synchronization pulses during the vertical blanking period. By using a pulse-width modulated signal having the same frequency as the horizontal rate but not necessarily with the same phase, and having at least a 50% duty cycle, the undesired pulses are gated out before being coupled to the horizontal synchronization circuit of the monitor, thus, the monitor system will not attempt to lock at a double frequency, nor cause visible distortion of the raster. The effect of the pulse width modulated signal is inhibited when a user changes the horizontal synchronization frequency and until the monitor achieves lock on the new frequency.

Abstract: A system for synchronizing input video signals from a plurality of video sources includes a plurality of buffering units (B1 . . . BN) each coupled to receive a respective one of the input video signals. The buffering units have mutually independent read and write operations. Each buffer write operation is locked to the corresponding video input signal. Each buffer read operation is locked to a system clock. The buffering units are substantially smaller than required to store a video signal field. The system further includes a storage arrangement (DRAM-1 . . . DRAM-M) for storing a composite signal composed from the input video signals, and a communication network (110) for communicating data from the buffering units to the storage arrangement, pixel (X) and line (Y) addresses of the buffering units and of the storage arrangement being coupled.

Abstract: A process for synchronizing a scanning circuit of a device for the display of images acquired by a camera having a scanning circuit controlled by a given acquisition clock. The device comprises an input buffer, a processor making it possible to reconstitute each image entering the buffer, a display store in which the images are recorded after processing and a controller able to control the reading or writing of the images in the display store. The process is characterized in that it consists of applying to the scanning circuit an arbitrary clock signal independent of the image synchronization of the signal received. Also, the reading and writing of the display store is controlled in order to obtain repetitions or suppressions of images on display thus absorbing any delay or advance. Further, the processor should have a faster than necessary image compression (average time of one image).

Abstract: A video signal processing apparatus for processing a video signal having: a memory circuit for receiving a video signal and storing received video signal; a synchronization signal separation circuit for separating a synchronization signal included by the received video signal, and transmitting the synchronization signal; a first counter for transmitting count data by performing a counting operation in synchonization with the synchronization signal transmitted from the synchronization signal separation circuit or by spontaneously performing the counting operation; a second counter for transmitting count data by spontaneously performing the counting operation; a memory control circuit for controlling writing or reading of the video signal to and from the memory circuit in accordance with the count data transmitted from the first counter; a first decoder for resetting the second counter in accordance with a value denoted by the count data transmitted from the first counter; and a second decoder for resetting the

Abstract: Audio frame synchronization for embedded audio demultiplexers counts the number of audio samples for each video frame of a digital video signal. The pattern of audio samples per video frame for an audio frame is detected to identify an audio frame boundary, the pattern being a function of the respective video and audio standards for the digital video signal. For example in one embodiment the number of audio samples for consecutive video frames are compared, and when there is equality between consecutive video frames the audio frame boundary is detected.

Abstract: An image signal processing device is arranged to receive an input image signal including horizontal and vertical synchronizing signals; to make a discrimination on the basis of the horizontal and vertical synchronizing signals, as to whether a period of the input image signal is less than a predetermined period or not; then, in accordance with information on the result of the discrimination, to cause a memory to store only a part of the input image signal corresponding to the predetermined period if the period of the input image signal is not less than the predetermined period; and if the period of the input image signal is less than the predetermined period, to cause the memory to complement the input image signal with a predetermined signal for a period by which the period of the input image signal is less than the predetermined period and store the complemented image signal.

Abstract: First and second field type detectors for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory and an asynchronous multiple line memory. The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit, which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type.

Abstract: An image coding apparatus for sequentially coding an input image signal that is supplied at a predetermined frame rate at a rate that is independent of such a frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out.

Abstract: Disclosed is a video camera apparatus including a video camera for generating a video signal and a camera control unit for generating a control signal for controlling the video camera. The camera control unit includes a video signal receiver, a video/reference signal phase comparator, a phase difference signal transmitter, a video signal memory, and write and read clock signal generators. The video camera comprises a phase difference signal receiver, a synchronizing signal generator, a synchronizing signal phase controller, an image pickup device and a video signal transmitter. In this setup, the output video signal is generated under stable genlock control for radio communication between video camera and camera control unit.

Abstract: In a method and apparatus for converting a synchronizing signal received from a controller for controlling a TV camera into a new synchronizing signal, a single frame synchronizing pulse for every two field pulses is generated on the basis of at least a vertical drive signal of the synchronizing signal received from the controller. The new synchronizing pulse which has a level higher than the white level and lower than the black level of a composite video signal generated by the TV camera is injected into a video transmission line connected to the TV camera for synchronizing the latter on the basis of the injected synchronizing pulse.