Abstract: This disclosure provides methods, devices, and systems for transmitting and receiving image data. The present implementations more specifically relate to repurposing non-video interfaces to receive image data. In some aspects, an image processing device may be coupled to an image source via an audio interface. For example, the audio interface may be an inter-IC sound (I2S) serial bus interface having at least a serial data input and a word select (WS) input. In some implementations, the serial data input may be coupled to receive image data from the image source and the WS input may be coupled to receive a WS signal that tracks a horizontal synchronization (HSYNC) signal associated with the image data. Accordingly, the image processing device may capture (or store) frames of received image data, where the beginning of each frame is aligned with an edge of the WS signal (and thus, the HSYNC signal).

Abstract: An AV amplifier detects combinations of resolutions and vertical frequencies of input video data, and reads information about combinations of resolutions and vertical frequencies stored in a display device in advance. The AV amplifier sets values, that are a combination of an output resolution and an output vertical frequency in which a value obtained by dividing a vertical frequency of the video data detected by a video detecting section by the output vertical frequency is an integer number and are present in the combinations of the resolutions and the vertical frequencies read by the reading section, as the combination of the output resolution and the output vertical frequency.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: Vertical sync signal separation apparatus and method are provided. The vertical sync signal separation apparatus includes a parameter detecting unit, a threshold generating unit and a vertical sync signal generating unit. The parameter detecting unit measures a composite sync signal to obtain a maximum and a second maximum positive pulse width, and a maximum and a second maximum negative pulse width. The threshold generating unit outputs a positive pulse threshold based on the maximum and second maximum positive pulse width, and outputs a negative pulse threshold based on the maximum and second maximum negative pulse width. The vertical sync signal generating unit outputs a vertical sync signal by comparing the composite sync signal against the positive pulse threshold and the negative pulse threshold. As such, this apparatus can correctly separate a vertical sync signal from composite sync signals with different standards, thus increasing its supportability.

Abstract: An AV amplifier detects combinations of resolutions and vertical frequencies of input video data, and reads information about combinations of resolutions and vertical frequencies stored in a display device in advance. The AV amplifier sets values, that are a combination of an output resolution and an output vertical frequency in which a value obtained by dividing a vertical frequency of the video data detected by a video detecting section by the output vertical frequency is an integer number and are present in the combinations of the resolutions and the vertical frequencies read by the reading section, as the combination of the output resolution and the output vertical frequency.

Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: A method for detecting SECAM-L signals is disclosed. First, a SECAM-L signal is received and demodulated into a demodulation signal. Then high frequency components of the demodulation signal are filtered out and a low frequency signal, including many sync pulses and many data pulses, is obtained. Next, the low frequency signal is inversion into an inversion signal, having many inversion sync pulses and many inversion data pulses. Afterwards a voltage level of the inversion signal is detected continuously whether it is a lowest level. After that, the lowest level is determined whether belonging to the inversion sync pulses when the voltage level of the inversion signal is the lowest level, and a detection signal is outputted. When the lowest level belongs to the inversion sync pulses, a voltage level of the detection signal is high, and the demodulation signal is an inversion SECAM-L demodulation signal.

Abstract: A method of transferring a deferred vertical synchronous signal and an image signal processor executing the method thereof are disclosed. Once the vertical synchronous signal for a kth frame is inputted from an encoding unit after a capture command is inputted, the method transmits a defer control command for a (k+1)th frame to an image sensor. Then, a return control command is transmitted to the image sensor if encoding of the kth frame is completed. With the present invention, complete encoding of image data becomes possible.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A transmitter includes: a transmission data generation section generating transmission data having a format of video field period as a unit including a horizontal blanking period, a vertical blanking period and an active video period which are separated by vertical synchronization signals, the active video period including a main video area and an auxiliary video area; and a transmission data transmitting section transmitting, in a differential signal format, the transmission data generated in the transmission data generation section to an external device through a transmission path and through a plurality of channels. The transmission data generation section allocates picture data to the main video area and allocates, to the auxiliary video area, additional information relating to the picture data allocated to the main video area.

Abstract: A wireless image transferring apparatus includes a free-run transmitter and a free-run receiver. The free-run transmitter includes a marker appending unit for appending a vertical synchronization marker to image data and a nondisplay period adjustment unit for adjusting the length of nondisplay period of image data according to monitoring information supplied, the transmitter transmitting the image data and receiving the monitoring information.

Abstract: An image output/input system includes a phase comparator, an image synchronous signal generator, a sensor timing generator, a sensor, an image/color processing unit, and a video encoder. The phase comparator receives a digital signal and a vertical synchronous signal and compares their period and phase to generate a clock correction signal. The image synchronous signal generator receives the clock correction signal and adjusts a subsequent period of the vertical synchronous signal according to the clock correction signal. The sensor timing generator receives the vertical synchronous signal and generates the sensor control timing, and the sensor receives the sensor control timing and generates raw image data. The image/color processing unit receives the raw image data and deals with the image and color process of the raw image data to generate target image data. The video encoder receives the vertical synchronous signal and the target image data and encodes them to generate analog encoded image data.

Abstract: A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal.

Abstract: A video signal judgment circuit for judging the condition of a video signal compounded of a picture signal and a synchronization signal is provided. The video signal judgment circuit is adapted to first filter the video signal by a low-pass filter (LPF) having an adjustable cutoff frequency and then separate the synchronization signal from the filtered signal to provide a pulsed synchronization detection signal. Upon comparison of a detection signal formed on the basis of the synchronization detection signal with an adjustable judgment reference value, the video signal judgment circuit outputs a video signal judgment signal indicative of the condition of the video signal as to whether or not the video signal is nullified or deteriorated.

Abstract: A method for detecting SECAM-L signals is disclosed. First, a SECAM-L signal is received and demodulated into a demodulation signal. Then high frequency components of the demodulation signal are filtered out and a low frequency signal, including many sync pulses and many data pulses, is obtained. Next, the low frequency signal is inversion into an inversion signal, having many inversion sync pulses and many inversion data pulses. Afterwards a voltage level of the inversion signal is detected continuously whether it is a lowest level. After that, the lowest level is determined whether belonging to the inversion sync pulses when the voltage level of the inversion signal is the lowest level, and a detection signal is outputted. When the lowest level belongs to the inversion sync pulses, a voltage level of the detection signal is high, and the demodulation signal is an inversion SECAM-L demodulation signal.

Abstract: The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).

Abstract: A method and an arrangement are disclosed for synchronizing on-screen display functions during analog signal reception in a terminal arrangement that is capable of receiving both digital and analog video signals. There are provided means (312, 313) for generating on-screen display objects. Coupled to said means for generating on-screen display objects, there are synchronization pulse generation means (314) for controlling the generation of on-screen display objects. Comparison means (322) are used for comparing synchronization pulses generated by said synchronization pulse generation means (314) with a synchronization signal obtained (320) from an analog video signal. The result of said comparing as a controlling signal is conveyed (323, 324) to a process (314, 325) of generating said synchronization pulses.

Abstract: A vertical synchronous signal detection circuit includes an analog-digital converter, an average calculation circuit and a compare circuit. The analog-digital converter receives a composite video signal and converts the video signal into a digital signal having a vertical synchronizing pulse. The average calculation circuit is coupled to receive the digital signal. The average calculation circuit calculates an average level of the vertical synchronizing pulse within a predetermined period. The compare circuit is connected to the average calculation circuit. The compare circuit compares a threshold level received thereto with the average level and outputs a synchronous detect signal when the average level falls below the threshold level.

Abstract: A video signal detecting circuit includes a synchronization detector for detecting a vertical synchronous signal in an input video signal. A counter starts counting pixel clock pulses in response to every vertical synchronous signal thus detected, and outputs a first signal when the count of pixel clock pulses reaches a preselected value. A comparator compares the vertical synchronous signal detected with the first signal for outputting a second signal representative of a difference between them. A mean circuit produces a mean value of the second signals over a plurality of pictures of the input video signal. An adjusting circuit adjusts the vertical synchronous signal with the mean value to output the resultant adjusted signal as a vertical synchronous signal. The preselected number is substantially equal to the standard number of pixels included in a single picture.

Abstract: A video code processing method includes (a), (b), (c) and (d). The (a) step includes providing a first original bit stream including a video code which is a digitized video signal. The (b) step includes generating a second original bit stream at a first timing by delaying the first original bit stream by a specific time interval. The (c) step includes generating a converted bit stream at a second timing. The first original bit stream is code-converted into the converted bit stream. The (d) step includes switching between the second original bit stream and the converted bit stream to output. The specific time interval is adjusted such that the first timing is substantially equal to the second timing.

Abstract: An integrated circuit with a signal demultiplexor for separating out two signals of different magnitudes from within a multiplexed signal without requiring a large capacitance for signal filtering. A multiple-threshold input comparator stage separates the multiplexed input signal into a first fully demultiplexed signal and a first partially demultiplexed signal. The first fully and partially demultiplexed signals are logically processed in an Exclusive-OR gate to produce a second partially demultiplexed signal which is then time-delayed and gated by the first fully demultiplexed signal. The resultant gated signal is low pass filtered to produce a second fully demultiplexed signal.

Abstract: A video signal processing apparatus in which an input video signal is written in a frame memory on a line sequential scanning frame unit base in synchronism with a first vertical synchronizing signal and which the line sequential scanning video signal written in the frame memory is read out in synchronism with a second vertical synchronizing signal. The second vertical synchronizing signal having a frequency different from a frequency of a first vertical synchronizing signal is generated in synchronism with the first vertical synchronizing signal of a starting frame of five frames forming a pattern after the conversion in the 2-3 pulldown conversion system when it is judged that the input video signal is based on a telecine-converted video signal.

Abstract: A vertical synchronous signal detection circuit includes an analog-digital converter, an average calculation circuit and a compare circuit. The analog-digital converter receives a composite video signal and converts the video signal into a digital signal having a vertical synchronizing pulse. The average calculation circuit is coupled to receive the digital signal. The average calculation circuit calculates an average level of the vertical synchronizing pulse within a predetermined period. The compare circuit is connected to the average calculation circuit. The compare circuit compares a threshold level received thereto with the average level and outputs a synchronous detect signal when the average level falls below the threshold level.

Abstract: A video signal detecting circuit includes a synchronization detector for detecting a vertical synchronous signal in an input video signal. A counter starts counting pixel clock pulses in response to every vertical synchronous signal thus detected, and outputs a first signal when the count of pixel clock pulses reaches a preselected value. A comparator compares the vertical synchronous signal detected with the first signal for outputting a second signal representative of a difference between them. A mean circuit produces a mean value of the second signals over a plurality of pictures of the input video signal. An adjusting circuit adjusts the vertical synchronous signal with the mean value to output the resultant adjusted signal as a vertical synchronous signal. The preselected number is substantially equal to the standard number of pixels included in a single picture.

Abstract: With the present invention, a synchronous processor circuit can be implemented with a simplified circuit by improving a display's synchronization stability, and by setting a pulse width of a vertical synchronizing signal to be integral multiple of the horizontal synchronizing signal.

Abstract: A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.

Abstract: A vertical synchronization separation circuit eliminates distortion in a television picture produced when the synchronization signal is complex and includes a copy guard signal.

Abstract: A level is preset into a counter. The level held in the counter is compared with the minimum value of the present video signal by a level detecting circuit. When the minimum value of the present video signal is lower than the level of the counter, the intermediate value between the value of the counter so far and the minimum value of the present video signal is obtained by an intermediate value calculating circuit, thereby presetting the counter and updating the level. Thus, the value of the counter gradually approaches a sync chip level. The video signal is sliced by a slice level formed on the basis of the value of the counter by a slice circuit, thereby extracting the sync signal. Further, in a mask signal generating circuit, the updating of the level is inhibited for a predetermined time after the updating of the level was performed for a predetermined period of time, thereby preventing the level from being influenced by the noise for the video period.

Abstract: A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Abstract: The period of an input signal is subdivided into N parts by carrying out a count, during this period, of the pulses delivered by a clock. This number is divided by N and then the remainder of this division is distributed among all the N parts of the period of the input signal. This technique may be applied to the generation of scanning signals in television.

Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: A blanking signal generating control circuit for use in a video apparatus is disclosed. The blanking signal control circuit according to the present invention has structure which makes it easily adaptable for use with different broadcast standards, such as NTSC, PAL, SECAM, etc. The control circuit has an edge detector which generates a front edge detecting signal at the front edge of the vertical sync signal, and a rear edge detecting signal the trailing (or rear) edge of the vertical sync signal. The control circuit also has a field distinction signal generator for detecting odd and even fields in a video signal. A counting controller generates a counting control signal synchronized with the front edge detecting signal in response to the field distinction signal and a broadcasting system select signal. Line counting is performed starting from an initial value which is selected from a first or second initial value in response to the field distinction signal.

Abstract: A digital pulse filtering circuit for processing composite sync signals is provided. The digital pulse filtering circuit can determine the polarity of an input composite sync signal composed of a horizontal sync signal and a vertical sync signal. The horizontal sync signal is a first periodic pulse train having a first pulse width, while the vertical sync signal is a second periodic pulse train having a second pulse width. The digital pulse filtering circuit includes a horizontal sync filter for filtering out all pulses in the input composite sync signal that have a pulse width less than the pulse width of the horizontal sync signal; and a vertical sync filter, coupled to receive the output of said horizontal sync filter, for filtering out all pulses in the output of said horizontal sync filter that have a pulse width less than the pulse width of the vertical sync signal. The output of said indicating the polarity of the input composite sync signal.

Abstract: Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output.

Abstract: In a synchronization stabilizing circuit and a television signal receiver, the follow-up range (TX) of the synchronizing signal (SH) is changed based on the judged result (J1) that it is judged whether or not the synchronizing signal (SH) itself exists and the judged result (J2) that it is judged whether or not the input signal exists in a follow-up range (TX), so that the signal can be synchronized easily in a short period even if the frequency of the synchronizing signal (SH) is deviated.

Abstract: A vertical sync separator circuit that operates with signals that have different arrangements of horizontal equalizing pulses in the vertical interval. The composite signal is integrated and used to operate a Schmidt trigger/inverter that feeds the data input of a D flip/flop. The flip/flop is clocked by the horizontal equalizing pulse that occurs after the beginning of the vertical pulse. In an arrangement that operates without equalizing pulses, a second trigger circuit is operates from a less than one-half line delay and supplies the reset input of the flip/flop. The arrangement provides consistent development of the vertical sync output pulse.

Abstract: A circuit arrangement for deriving horizontal frequency and vertical frequency pulses from a synchronizing signal, in which all clocked components are provided with the same clock during the digital processing of the synchronizing signal. Too derive the horizontal (H) pulse signal, a logic circuit 2 is provided which combines the sync signal with a masking pulse signal derived from the clocked sync signal. To derive the vertical (V) pulse signal in the clock raster, a counting flip-flop 14 is driven by the clocked sync signal after combination with the vertical pulse signal via an interference pulse signal suppression circuit 10. To derive the 2V pulse signal, a logic circuit 17 is provided which combines the V pulse signal with a pulse signal derived from the clocked sync signal.

Abstract: In a vertical synchronizing signal stabilizing circuit, an integrated circuit and a television signal processing device, a vertical synchronizing signal of which period is stabilized can be output with a small number of elements and a simple constitution, without being influenced by the state of the television signal. On the basis of a first distinguish signal which indicates whether there is a separated signal separated from the television signal as the vertical synchronizing signal or not and of a second distinguish signal which indicates whether the period of the separated signal is the standard period or not, the plural states of the separated signal are discriminated, and the processing mode of the separated signal processing circuit is switched on the basis of the result of the discrimination to process the separated signal.

Abstract: The present invention includes a capacitor, a charge/discharge circuit for generating a charging current having a value increasing with the increase of the frequency of the horizontal sync signal to charge the capacitor in a time period of the horizontal sync signal and a time period of the vertical sync signal. The charge/discharge circuit discharges the capacitor in other time periods to reduce a difference of the horizontal sync signal frequency. A comparator compares the voltage of the capacitor with a predetermined reference voltage to detect the vertical sync signal.

Abstract: An oscillation and trigger circuit for a vertical synchronizing signal in a display apparatus, the oscillation and trigger circuit comprising: a pulse generator for generating a single pulse for each active cycle of the vertical synchronizing signal; a first signal detector having an input terminal connected to an output terminal of the pulse generator, for determining a state of no input of the vertical synchronizing signal whose frequency is less than a predetermined frequency and for generating a first predetermined signal indicative of the state; a second signal detector having input terminals connected to respective output terminals of the pulse generator and the first signal detector, for checking a time interval of the vertical synchronizing signal input to the pulse generator so as to output a second predetermined signal when the time interval exceeds a predetermined time period and for outputting the second predetermined signal responsive to the first predetermined signal input from the first signal

Abstract: A vertical synchronization signal detector for detecting a vertical synchronization signal in a composite video signal.

Abstract: A digital video vertical synchronization pulse detector for detecting a vertical synchronization pulse in a video signal is disclosed. The digital video vertical synchronization pulse detector includes a threshold device for comparing a first digital data stream generated from the video signal to a sync threshold. An integration device integrates the video signal in response to the threshold device to generate a second digital data stream. Upper and lower threshold devices compare the second digital data stream to upper and lower thresholds. A detection device responsive to the upper and lower threshold devices detects when the second digital data stream crosses the upper and lower thresholds. When the second digital data stream crosses the upper threshold, the detection device generates a first vertical sync pulse and when the second digital data stream crosses the lower threshold, the detection device is reset to enable generation of subsequent vertical sync pulses.

Abstract: A vertical reset generator monitors a composite video signal and generates a vertical reset pulse which is active during the presence of serration pulses within the composite video signal. The synchronization pulses within the input composite video signal are separated by a sync separator circuit. The output of the sync separator circuit, including horizontal sync pulses, equalizing pulses and serration pulses, is provided to a charging circuit which charges up a capacitor when the output of the sync separator circuit is at a low level and discharges the capacitor when the output of the sync separator circuit is at a high level. The serration pulses are at a low level for a greater time period than the equalizing pulses. The charge built up across the capacitor is therefore greater during a serration pulse than during an equalizing pulse.

Abstract: A pulse separator 110 predicts the start of a vertical synchronizing pulse in a video composite synchronizing signal (VCSS) applied via input 105. At a predicted time, the pulse separator 110 provides a start signal via a first output to the bistable 125, thereby causing a signal at output 130 to vary from a first output level to a second output level. When the end of the vertical synchronizing pulse is detected in the VCSS, a stop signal is provided via a second output to the bistable 125, thereby causing the signal at the output 130 to vary from the second level to the first level. A multiplexer (MUX) 615 switched to couple horizontal synchronizing pulses from input 605 to output 620, when a vertical synchronizing pulse is received from input 625, and, switched to coupled pseudo horizontal synchronizing pulses from pseudo pulse generator 610 to the output 620 when a vertical synchronizing pulse is not received from the input 625.

Abstract: A sync stripper circuit receives from a medical imaging modality a composite video signal with a horizontal sync frequency within one of first, second, third or fourth frequency ranges. The sync stripper circuit includes a circuit for stripping the composite sync signal from the received signal; horizontal sync detection circuit for detecting the horizontal sync signal from the stripped composite sync signal; a vertical sync detection circuit for detecting the vertical sync signal; an F1/F2 field detection circuit for detecting the F1/F2 field from the stripped composite sync signal; and a control circuit for controlling the horizontal sync detection circuit, the vertical sync detection circuit and the F1/F2 field detection circuit to operate in the selected one of said first, second, third or fourth frequency ranges of the received composite video signal. A serrating signal circuit inserts a horizontal signal into the vertical sync signal if serrating signals are absent therein.

Abstract: A vertical sync signal circuit for producing a stable sync signal is disclosed. A first frequency divider and a first window circuit generate a sync output pulse PC having the same period as the vertical sync signal contained in the TV signal and a first window signal W1. A reference signal generator generates a reference signal VR in synchronism with the vertical sync signal VS being input. A second frequency divider and a second window circuit generate a second window signal W2 wider than the first window signal W1. A third frequency divider discriminates the period of the reference signal VR on the basis of the first window signal W1 and the second window signal W2, and selects the sync output pulse PC1 or the reference signal VR. The sync signal CVD having the same period as the sync output pulse PC or the reference signal VR, as the case may be, is produced through an output switching circuit.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.

Abstract: The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.