Abstract: A transceiver of the present inventive concept includes a transmitter and a receiver connected by a first line and a second line, and the transmitter includes a first encoder; a second encoder; and a transmission driver. The first encoder generates a first encoded data different from a first data during a first period and the second encoder generates a second encoded data equal to a second data during the first period, the second encoder generates the second encoded data different from the second data during a second period and the first encoder generates the first encoded data equal to the first data during the second period, and the first period and the second period are arranged to alternate with each other.

Abstract: A sensor device using verification includes a sensor component and a verification component. The sensor component is configured to generate first data and second data. The verification component is configured to analyze the first data and the second data and generate verification data based on the first data and the second data.

Abstract: A clock and data recovery (CDR) circuit and method are disclosed herein. The CDR circuit includes a data analysis module, a loop filter module and a phase adjust module. The data analysis module generates an error signal according to an input data, a first clock signal, and a second clock signal. The loop filter module generates a first corrective signal according to the error signal, a frequency threshold value, and a phase threshold value. The phase adjust module generates the first clock signal and the second clock signal according to the first corrective signal. The loop filter module further accumulates the error signal to generate an accumulated value, and to compare the accumulated value with an accumulated threshold value, so as to dynamically adjust the accumulated threshold value, the frequency threshold value, and the phase threshold value.

Abstract: A projector and an apparatus and method for driving an optical scanner are disclosed. A sensing signal processor receives a sensing signal that represents sensing of operation of the optical scanner and generates a horizontal scan signal corresponding to a horizontal frequency of the optical scanner on the basis of the received sensing signal. A driving signal generator generates at least one of a horizontal reference signal including line information that indicates the number of horizontal lines of a horizontal driving signal of the optical scanner, a reference clock signal and a scanner driving signal for driving the optical scanner on the basis of the generated horizontal scan signal.

Abstract: An input card of video switcher includes a detection block for detecting errors in the timing signals of a digital video signal within a range. For timing signals with errors that fall within the range, the input card implements a correction block to correct the signals to an expected resolution. For timing signals with errors that fall out of the range, the input card does implement the correction block and passes the raw timing signal through.

Abstract: A video signal output device and method are capable of easily displaying moving images while synchronizing transmission-side data and reception-side data even if video data is asynchronously transferred to the reception side from the transmission side. A video signal output device for receiving video data transmitted from a transmitter in sync with a first clock through a communication unit, storing the video data in a storage unit, reading the video data from the storage unit in sync with a second clock, and displaying moving images on a display unit, includes a synchronization adjustment unit for detecting a video data correction amount in accordance with a reference video data amount in one vertical synchronous period and a video data amount of the second clock in one vertical synchronous period to adjust a predetermined horizontal scanning period in accordance with the video data correction amount.

Abstract: A system for edge enhancement includes an input unit to receive an input signal Yin, a vertical enhancement unit to perform a vertical enhancement of an edge of the input signal Yin to generate an output YEV, and a horizontal enhancement unit to perform a horizontal enhancement of the edge of the input signal Yin to generate an output YEH. The system also includes a local gradient analysis unit to generate a local gradient direction GradDir and a local gradient magnitude GradMag based at least partly upon the input signal Yin, and a mixer to generate an output Yout by mixing the output YEV with the output YEH using the local gradient direction GradDir. The system further includes an output unit to output the output Yout.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.

Abstract: An input card of video switcher includes a detection block for detecting errors in the timing signals of a digital video signal within a range. For timing signals with errors that fall within the range, the input card implements a correction block to correct the signals to an expected resolution. For timing signals with errors that fall out of the range, the input card does implement the correction block and passes the raw timing signal through.

Abstract: A projector and an apparatus and method for driving an optical scanner are disclosed. A sensing signal processor receives a sensing signal that represents sensing of operation of the optical scanner and generates a horizontal scan signal corresponding to a horizontal frequency of the optical scanner on the basis of the received sensing signal. A driving signal generator generates at least one of a horizontal reference signal including line information that indicates the number of horizontal lines of a horizontal driving signal of the optical scanner, a reference clock signal and a scanner driving signal for driving the optical scanner on the basis of the generated horizontal scan signal.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A multimedia device generates and outputs video signals to a display component and an external display device, and includes a video output circuit and a load detection circuit. The load detection circuit isolates and buffers the video output circuit and the load detection circuit, and retrieves horizontal sync signals from the video signals. The load detection circuit further amplifies and integrates the retrieved horizontal sync signals to output direct current signals, and finally compares the direct current signals with a predetermined voltage to output a control signal indicating a connection between the video output circuit and the external display device. The multimedia device turns off the display component according to the control signal indicating that the video output circuit has been connected to the external display device.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A device for detecting synchronization pulses in a video signal is disclosed. The device includes a transistor. The base-emitter voltage of the transistor is maintained below a threshold level in response to receiving active video information. The base-emitter voltage is increased above the threshold level in response to receiving synchronization information, whereby the transistor is turned on to generate an asserted synchronization signal. Accordingly, in response to active video information being received and the transistor being off, the magnitude of the synchronization signal is set to a first level and in response to synchronization information being received, and the transistor being on, the magnitude is set to a second level. The synchronization signal generated by the transistor is processed to provide both horizontal and vertical synchronization signals.

Abstract: A vertical synchronization controller includes a vertical synchronization separation unit for taking out a vertical synchronizing signal from a decode video signal; a vertical synchronization generation unit for taking out a horizontal synchronizing signal from the decode video signal and generating an internal vertical synchronizing signal; a noise detection unit for detecting the noise amount of the decode video signal; a control unit for determining the current noise state based on the numeric value indicating the noise detection amount, determining whether or not a period of the external vertical synchronizing signal is normal in response to whether or not the external vertical synchronizing signal having the period close to a period of the internal vertical synchronizing signal is input, counting the successive number of times the external vertical synchronizing signal of the normal period has been input, and giving a command responsive to the numeric value indicating the noise detection amount and the s

Abstract: In one embodiment, a method for synchronizing a plurality of video signals received from one or more video sources is provided. The method includes providing one or more video sources and providing a codec including an internal reference oscillator. The method also includes generating a plurality of horizontal and vertical synchronization pulses based on the reference frequency of the internal reference oscillator, generating a composite synchronization pulse based on the plurality of horizontal and vertical synchronization pulses, and transmitting the composite synchronization pulse to the one or more video sources via a communication link.

Abstract: [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A video signal output device and method are capable of easily displaying moving images while synchronizing transmission-side data and reception-side data even if video data is asynchronously transferred to the reception side from the transmission side. A video signal output device for receiving video data transmitted from a transmitter in sync with a first clock through a communication unit, storing the video data in a storage unit, reading the video data from the storage unit in sync with a second clock, and displaying moving images on a display unit, includes a synchronization adjustment unit for detecting a video data correction amount in accordance with a reference video data amount in one vertical synchronous period and a video data amount of the second clock in one vertical synchronous period to adjust a predetermined horizontal scanning period in accordance with the video data correction amount.

Abstract: The invention provides an image processing circuit having a capability of performing a reduction (resizing) process and an enlargement process on horizontal-scanning-line data inputted in synchronization with an input horizontal synchronization signal, and subsequently adjusting the horizontal synchronization signals so that the input horizontal-scanning-line data is made transferable to external devices in real time, and an image processing method therefor. A reducing unit thins out n-lines of the input horizontal synchronization signals out of m-lines of the input horizontal synchronization signals HD. When an enlarging unit enlarges the image data by an enlargement ratio k (k: natural number) in the vertical direction, the enlarging unit inserts (k?1) lines of the second horizontal synchronization signals for data transmission EHSYNC2 in the transmitting horizontal-synchronization-signal interval time TC1 between adjacent first horizontal synchronization signals for data.

Abstract: A convergence control apparatus for a video display is provided. In the apparatus, a convergence controller receives a vertical synchronization signal and a horizontal synchronization signal and then outputs a vertical convergence correction voltage and a horizontal convergence correction voltage. An amplifier receives and amplifies the vertical convergence correction voltage and the horizontal convergence correction voltage. A correction current generator receives the amplified vertical convergence correction voltage and the amplified horizontal convergence correction voltage and then generates a vertical convergence correction current and a horizontal convergence correction current. A switching unit controls the vertical convergence correction voltage and the horizontal convergence correction voltage according to the horizontal synchronization signal.

Abstract: A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Abstract: An integrated circuit with a signal demultiplexor for separating out two signals of different magnitudes from within a multiplexed signal without requiring a large capacitance for signal filtering. A multiple-threshold input comparator stage separates the multiplexed input signal into a first fully demultiplexed signal and a first partially demultiplexed signal. The first fully and partially demultiplexed signals are logically processed in an Exclusive-OR gate to produce a second partially demultiplexed signal which is then time-delayed and gated by the first fully demultiplexed signal. The resultant gated signal is low pass filtered to produce a second fully demultiplexed signal.

Abstract: An ITU-R BT.656 (or similar) digital video signal is converted to analog at which point a simple 7-state state machine in combination with a 6 bit binary counter generates tri-level synchronized video. The state machine receives vertical and horizontal synchronization signals as well as End-Active-Video and Start-Active-Video signals from the ITU-R BT.656 video. A pixel clock clocks the 6 bit binary counter. Active video is passed directly to the output. Horizontal and vertical sync signals are mirrored at the output with the state machine generating a positive tri-level signal immediately following the horizontal synchronization signal. The high level signal is generated for a period of 44 pixel counts as counted by the 6 bit counter.

Abstract: A device which generates horizontal and vertical sync signals of a composite signal to create a soft picture on a display monitor by preventing a free running effect of a composite signal which is caused by a mode conversion between recorded and unrecorded areas of the picture when a composite signal generated from an alternative source such as a VCR instead of an external input signal is applied to the display monitor. The device includes a microcomputer for generating a sync select signal based on a display mode, and a composite signal analyzing and horizontal/vertical oscillating circuit for generating horizontal and vertical oscillating signals based on a luminance signal separated from a composite signal input. A horizontal sync signal generator processes the horizontal oscillating signal, to generate a composite horizontal sync signal. A vertical sync signal generator processes the vertical oscillating signal, to generate a composite vertical sync signal.

Abstract: A horizontal display size compensation circuit for a monitor prevents a horizontal display size of a monitor screen from being changed when a horizontal frequency varies according to a video mode. A horizontal frequency is generated by a horizontal frequency generation section corresponding to each video mode. A microcomputer generates a predetermined horizontal display size compensation signal according to the horizontal frequency corresponding to each video mode and a horizontal display size adjustment signal corresponding to an input of a key input section, and a horizontal display size control section controls a horizontal display size of the monitor screen by supplying the horizontal display size adjustment signal of the microcomputer and the horizontal display size compensation signal to the horizontal frequency. Therefore, a horizontal display size of a monitor screen is prevented from varying according to a video mode.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: A synchronous signal detection circuit which detect a vertical synchronous signal and a horizontal synchronous signal from composite synchronous signal, including: a reset generation means for receiving an external composite synchronous signal and an external main clock signal to generate a reset signal at falling edge of the composite synchronous signal; a counter means being reset by the reset signal received from the reset generation means and for counting the main clock signal to generate first through fourth output signals; a vertical synchronous signal detection means for receiving the second output signal of the counter means and the composite synchronous signal to detect the vertical synchronous signal of the composite synchronous signal and generating the vertical synchronous signal; and a horizontal synchronous signal detection means for receiving the third and the fourth output signals of the counter means and the reset signal of the reset generation means to detect the horizontal synchronous signa

Abstract: A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses.

Abstract: A field synchronization system of a field detect circuit adaptable for use with non-standard output digital data of forward looking infrared (FLIR) sensors. Timing signals and digital data from a FLIR sensor are utilized and there is outputted a vertical and horizontal signal output. A bypass circuit allows for the optional bypass of frame grabber generated field index circuitry so that an external field index signal is utilized.

Abstract: A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Abstract: A synchronous control device is disclosed which is capable of obtaining stable synchronization regardless of the kind of image source even when the automatic synchronous control circuit cannot operate in the normal manner.The device includes a phase comparator, an integrator, a horizontal oscillation circuit, and a horizontal synchronous control circuit composed of a frequency measuring section consisting of a digital frequency measuring circuit, etc. and a control section consisting of a frequency determining circuit, an oscillation frequency control circuit, etc. The frequency measuring section measures the input horizontal synchronizing frequency and transfers it to the control section as digital data, and the control section determines the true value of the input synchronizing frequency by the frequency determining circuit while monitoring the transition of the frequency data per unit time.

Abstract: In a Sync signal detection circuit for detecting a Sync signal included in a television signal transmitted in a digital mode, pattern check means 2 checks a pattern of a Sync signal which is super imposed on a series of input data with a reference pattern. Based on a check result, Sync detection determination means 5 outputs a Sync detected signal or a Sync non-detected signal. Sync detection initialization means is further provided to this detection circuit for outputting forcibly a Sync non-detected signal when a signal of a series of input data is switched over. As a result, a Sync signal can be detected within a shorter period than the conventional circuit structure.

Abstract: A method for detecting and separating vertical and horizontal synchronous signals from a computer system. The input forms of the vertical and horizontal synchronous signals from the computer system are detected by scanning a vertical synchronous signal terminal, a horizontal/composite synchronous signal terminal and a synchronous-on-green terminal of the computer system. In accordance with the detected input forms, the vertical and horizontal synchronous signals are separated from each other and then adjusted in polarity. Therefore, the present invention requires no separate hardware for the separation and polarity adjustment of the vertical and horizontal synchronous signals, resulting in simplification in circuit construction and reductions in number of used components and size of a printed circuit board.

Abstract: A circuit arrangement for deriving horizontal frequency and vertical frequency pulses from a synchronizing signal, in which all clocked components are provided with the same clock during the digital processing of the synchronizing signal. Too derive the horizontal (H) pulse signal, a logic circuit 2 is provided which combines the sync signal with a masking pulse signal derived from the clocked sync signal. To derive the vertical (V) pulse signal in the clock raster, a counting flip-flop 14 is driven by the clocked sync signal after combination with the vertical pulse signal via an interference pulse signal suppression circuit 10. To derive the 2V pulse signal, a logic circuit 17 is provided which combines the V pulse signal with a pulse signal derived from the clocked sync signal.

Abstract: A sync signal separating circuit of an image output apparatus includes an inversion amplifying section for providing a green video signal supplied from a video signal generator to be output as an output signal that is inverted and amplified, and a clipper receiving the output signal of the inversion amplifying section as an input signal to output a clipped output signal obtained by cutting over or below a prescribed amplitude. Here, the inversion amplifying section has an amplifying device, an input resistor and a feedback resistor, and the clipper has a diode having an anode connected to the output side of the inversion amplifying section and a load resistor having one side connected to a cathode of the diode and the other side grounded. Thus, the sync signal is accurately produced from the cathode of the diode without requiring a conventional horizontal sync signal detecting section.

Abstract: A circuit for removing every other equalizing pulse from a signal representing the sync pulses of a composite video signal, generates an output signal representative of every horizontal synchronization pulse and every other vertical synchronization pulse within the composite video signal. A sync separator circuit separates the synchronization pulses from the composite video signal. An output of the sync separator circuit includes all of the horizontal synchronization pulses and vertical synchronization pulses. The vertical synchronization pulses include equalizing pulses and serration pulses which have a frequency which is twice the frequency of the horizontal synchronization pulses. A capacitor is used to store charge. A current source charges the capacitor. A transistor controlled by the output signal provides a discharge path for the capacitor.

Abstract: It is the object to create a vertical deflection circuit which is suitable, in particular, for a symmetric deflection with a sinusoidal deflection current and a free-running horizontal deflection circuit not synchronised by the input signal.A vertical pulse derived from the received signal and a horizontal pulse (H*) derived from the horizontal deflection circuit are applied to the synchronising inputs of the vertical deflection circuit in such a manner that the vertical deflection in each case begins with the first horizontal pulse following an edge of the vertical pulse (V) derived from the received signal and ends in a wait position preceding the next vertical pulse (V).Suitable, in particular, for television receivers with a symmetric free-running horizontal deflection not synchronised by the input signal.

Abstract: A sync stripper circuit receives from a medical imaging modality a composite video signal with a horizontal sync frequency within one of first, second, third or fourth frequency ranges. The sync stripper circuit includes a circuit for stripping the composite sync signal from the received signal; horizontal sync detection circuit for detecting the horizontal sync signal from the stripped composite sync signal; a vertical sync detection circuit for detecting the vertical sync signal; an F1/F2 field detection circuit for detecting the F1/F2 field from the stripped composite sync signal; and a control circuit for controlling the horizontal sync detection circuit, the vertical sync detection circuit and the F1/F2 field detection circuit to operate in the selected one of said first, second, third or fourth frequency ranges of the received composite video signal. A serrating signal circuit inserts a horizontal signal into the vertical sync signal if serrating signals are absent therein.

Abstract: A vertical sync signal circuit for producing a stable sync signal is disclosed. A first frequency divider and a first window circuit generate a sync output pulse PC having the same period as the vertical sync signal contained in the TV signal and a first window signal W1. A reference signal generator generates a reference signal VR in synchronism with the vertical sync signal VS being input. A second frequency divider and a second window circuit generate a second window signal W2 wider than the first window signal W1. A third frequency divider discriminates the period of the reference signal VR on the basis of the first window signal W1 and the second window signal W2, and selects the sync output pulse PC1 or the reference signal VR. The sync signal CVD having the same period as the sync output pulse PC or the reference signal VR, as the case may be, is produced through an output switching circuit.

Abstract: A self-adjusting window circuit suitable for fabrication as a monolithic integrated circuit. The self-adjusting window circuit comprises an input port, a positive edge detector coupled to the input port, a latch coupled to the output of the edge detector and a charging stage coupled to the latch. The input signal comprises a signal having a sequence of pulses appearing at a predetermined scan rate, for example, a composite video signal. The input port feeds the input signal to the edge detector which produces a pulse output signal in response to detecting a pulse in the input signal. The pulse output from the edge detector is latched and used to generate a charging control signal which controls the charging stage. In response to the charging control signal, the charging stage produces a window control signal for a predetermined period.

Abstract: A receiver is provided for receiving a digital data stream over a communication path. The digital data is arranged as a sequence of frames, each frame including a plurality of lines of data. The beginning of each frame is indicated by a frame synchronization word; the beginning of each line is indicated by a horizontal synchronization byte. The data is interleaved by an encoder prior to transmission. The decoder contains circuitry for locating the horizontal and frame synchronization data and contains circuitry for deinterleaving the digital data. Both the synchronization locating circuitry and the deinterleaving circuitry require access to a memory, but not at the same time. Therefore, a single memory is used with the synchronization recovery circuitry and deinterleaving circuitry alternately addressing the memory.

Abstract: A sync signal generator of a television receiver for use in a vehicle has a phase reset detector for gradually absorbing a phase fluctuation of an input sync signal which occurs due to a ghost phenomenon or a fading phenomenon and reducing a phase fluctuation. The sync signal generator provides a sync signal synchronized with an output signal of the phase reset signal detector. Thus, a stable sync signal without a sudden change in phase can be obtained although it is synchronized with the input sync signal.

Abstract: Signal processing apparatus comprises a chrominance subsampler (10) for sampling the U and V components of a PAL video signal in response to an enable signal. A counter (30) responsive to the horizontal synchronization component of the PAL video signal generates the enable signal upon detection of a predetermined number of horizontal synchronization pulses. Logic (60,70,80) responsive to the vertical synchronization component of the PAL video signal resets and disables the counter (30) upon detection of a vertical synchronization pulse. Logic (50,60,70,80) restarts the counter (30) from a reset state upon detection of a predetermined polarity in the V component of the PAL video signal.

Abstract: A single chip video signal processing circuit capable of performing a sync separation and odd/even field detection using an NTSC mode or a PAL mode video signal, the video signal processing circuit includes a sync signal separator for separating the input video signal into a horizontal sync signal and a composite sync signal, a vertical sync signal detector for detecting a vertical sync signal from the composite sync signal, a window pulse generator for generating a window pulse having a different width according to the selection of either the NTSC mode or the PAL mode by combining the detected vertical sync signal with the horizontal sync signal, an odd/even field detector for receiving the window pulse and the vertical sync signal and for detecting the number of pulses of the vertical sync signal within the window pulse interval, and a vertical blanking interval detector for counting a predetermined number of pulses of the horizontal sync signal, the window pulse being used as a RESET pulse for generating a

Abstract: A method for detecting and separating vertical and horizontal synchronous signals from a computer system. The input forms of the vertical and horizontal synchronous signals from the computer system are detected by scanning a vertical synchronous signal terminal, a horizontal/composite synchronous signal terminal and a synchronous-on-green terminal of the computer system. In accordance with the detected input forms, the vertical and horizontal synchronous signals are separated from each other and then adjusted in polarity. Therefore, the present invention requires no separate hardware for the separation and polarity adjustment of the vertical and horizontal synchronous signals, resulting in simplification in circuit construction and reductions in number of used components and size of a printed circuit board.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.

Abstract: The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.