Abstract: A demodulator of a video demodulation device includes an analog-to-digital converter converting an analog IF signal into a digital IF signal, a luminance gain adjuster performing gain adjustment of a luminance component included in the digital IF signal such that a maximum of the luminance component within a predetermined period becomes equal to a predetermined reference value, and a synchronization corrector receiving as input a result of the gain adjustment, correcting a signal corresponding to a signaling period of the horizontal synchronizing signal, and outputting the signal as a CVBS signal. The synchronization corrector outputs, as the CVBS signal, a composite signal containing the luminance component and a color component included in the gain adjustment result when the composite signal is smaller than the reference value, or the reference value when the composite signal is equal to or greater than the reference value.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.

Abstract: Pulse detection portion detects pulses in a horizontal synchronization signal and acquires the occurrence period and the pulse width of the detected pulses. Synchronization pulse decision portion determines pulses, for which the differences between the occurrence period and the reference period and between the pulse width and the reference pulse width are within their respective error tolerance ranges, as synchronization pulses. Mean period acquisition portion obtains the mean period by averaging occurrence periods of the synchronization pulses. Reference period correction portion carries out either or both of correcting the reference period so as to get closer to the mean period and correcting the error tolerance range of the reference period so as to get narrower, under the condition that the occurrence frequency of the synchronization pulses for which the difference between the occurrence period and the mean period is outside of a predetermined tolerance range exceeds a predetermined threshold.

Abstract: A sync separation circuit separates a synchronizing signal from a video signal containing the synchronizing signal. A minimum level detecting section detects a minimum level of a video signal. A sync tip level detecting section detects a sync tip level in the video signal. A pedestal level detecting section detects a pedestal level in the video signal. Based on both the sync tip level detected by the sync tip level detecting section and the pedestal level control by the pedestal level detecting section, a slice level setting section sets a slice level corresponding to an intermediate value between the sync tip level and the pedestal level. The slice level control section sets the slice level based on the minimum level detected by the minimum level detecting section if the slice level set based on the sync tip level and the pedestal level is inappropriate.

Abstract: The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: The invention relates a method of extracting synchronization signals from an input video signal (Csync) comprising horizontal synchronization pulses at the start of video lines, for generating a horizontal synchronization signal (Hsync), said method comprising:—a calculation step (105) for calculating the duration (D) of the video lines in said input video signal (Csync),—a forcing step (108) for forcing said input video signal (Csync) to an output level, said output level corresponding to the level of said input video signal (Csync) after the horizontal synchronization pulses, said input signal (Csync) being forced between the end of each horizontal synchronization pulse and a moment defined by a first percentage (X1) of said line duration (D), for generating said horizontal synchronization signal (Hsync). Use: Extraction of synchronization signals.

Abstract: We describe and claim a system and method for horizontal and vertical sync detection and processing. A method comprises detecting synchronization information within a video signal, estimating stability of the video signal according to the detected synchronization information, and generating one or more synchronization signals according to the detected synchronization information and the estimated stability of the video signal.

Abstract: A synchronization signal detector includes a horizontal synchronization level detector, a synchronization signal extractor, a first filter circuit, and a synchronous separator. The horizontal synchronization level detector detects a horizontal synchronization detection level HL for detecting a horizontal synchronization signal from a video signal Din. The synchronization signal extractor outputs a limited signal D1 obtained by extracting only a signal within a limit range (HL?n) to (HL+m) that is set based on the horizontal synchronization detection level HL from the video signal Din. The first filter circuit removes a high frequency component of the limited signal D1 and outputs it. The synchronous separator detects a horizontal synchronization signal HS from the output signal of the first filter circuit.

Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A first converter converts the sliced sync signal to a control signal having an amplitude or magnitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A second converter converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude or magnitude of the control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal. These timed intervals produced in accordance with embodiments of the present invention are easily and precisely scalable, allowing them to be used to discriminate various timing features embedded in video signals.

Abstract: A pedestal level of each of the R-Y and B-Y signals (color-difference signals) in a horizontal synchronization time T1 of a horizontal synchronizing signal is detected, and a pedestal level adjustment value for adjustment of the pedestal level of each of the R-Y and B-Y signals is determined based on the pedestal level determined in such a manner that a difference in pedestal level of each of the R-Y and B-Y signals between in the horizontal synchronization time T1 and in a horizontal scanning time T2 of the horizontal synchronizing signal is lessen. The pedestal level adjustment value determined is stored and video amplification-chroma circuit 130 adjusts the pedestal level of each of the R-Y signal and the B-Y signal in the horizontal synchronization time T1 of the horizontal synchronizing signal by an amount of adjustment value stored in.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A technique for the modification of sub-pixels to hide defects for defective sub-pixels.

Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.

Abstract: A microcontroller-based video AGC/sync regulator in which the parameters of various synchronizing signals of several different video formats are incorporated into a user program to generate signals to be processed by other sub circuits that correct and reinforce the AGC levels and sync signals of an incoming video signal is disclosed. The microcontroller-based video AGC/sync regulator is synchronized by the selection and isolation of a reference point of particular qualities that distinguishes itself from any other portion of the video signal. The reference points may be singular or plural in nature and are extracted from the video signal by means of a hybrid and specialized circuit or circuits, an auxiliary microcontroller and/or the system microcontroller. The microcontroller-based AGC/sync regulator is readily adapted for use as a decoder/encoder by altering the user program.

Abstract: The invention provides an image processing circuit having a capability of performing a reduction (resizing) process and an enlargement process on horizontal-scanning-line data inputted in synchronization with an input horizontal synchronization signal, and subsequently adjusting the horizontal synchronization signals so that the input horizontal-scanning-line data is made transferable to external devices in real time, and an image processing method therefor. A reducing unit thins out n-lines of the input horizontal synchronization signals out of m-lines of the input horizontal synchronization signals HD. When an enlarging unit enlarges the image data by an enlargement ratio k (k: natural number) in the vertical direction, the enlarging unit inserts (k?1) lines of the second horizontal synchronization signals for data transmission EHSYNC2 in the transmitting horizontal-synchronization-signal interval time TC1 between adjacent first horizontal synchronization signals for data.

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further processed to determine the time instants of the occurrence of the horizontal sync signals. The time instants are subsequently filtered to generate horizontal pulses. A video line memory allows to utilize subsequent horizontal sync signals for calculating the horizontal sync pulse of a current video line. The invention also relates to an apparatus for carrying out the method.

Abstract: A method and an arrangement are disclosed for synchronizing on-screen display functions during analog signal reception in a terminal arrangement that is capable of receiving both digital and analog video signals. There are provided means (312, 313) for generating on-screen display objects. Coupled to said means for generating on-screen display objects, there are synchronization pulse generation means (314) for controlling the generation of on-screen display objects. Comparison means (322) are used for comparing synchronization pulses generated by said synchronization pulse generation means (314) with a synchronization signal obtained (320) from an analog video signal. The result of said comparing as a controlling signal is conveyed (323, 324) to a process (314, 325) of generating said synchronization pulses.

Abstract: A method for providing a horizontal scan control signal for a TV set from a horizontal synchronization signal contained in a composite video signal, the horizontal synchronization signal containing horizontal synchronization pulses and parasitic pulses, the scan control signal being provided from an oscillating signal generated by an oscillator of a phase-locked loop receiving the horizontal synchronization signal, the oscillating signal having a frequency depending on a driving signal provided from the comparison between the horizontal synchronization signal and a binary phase signal, in which, at each parasitic pulse among successive parasitic pulses between two synchronization pulses, the driving signal is successively varied in the increasing direction or in the decreasing direction.

Abstract: A video signal reproducing apparatus and method for adjusting a change in a horizontal synchronous signal. The video signal reproducing apparatus transforms a format of an input video signal, generates horizontal and vertical synchronous signals, and displays the video. The video signal reproducing apparatus includes a measurer, a comparator, and an adjustor. The measurer measures a period of the horizontal synchronous signal, the comparator compares the measured period of the horizontal synchronous signal with a predetermined reference range, and the adjustor adjusts a period of a clock signal for producing the horizontal synchronous signal, if the measured period of the horizontal synchronous signal fails to fall within the predetermined reference range.

Abstract: A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Abstract: The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).

Abstract: Methods and systems are described for determining a slice level used for detecting an edge of a horizontal sync pulse of a horizontal line of a video signal, where the horizontal line has a plurality of samples. An exemplary method comprises low-pass filtering the video signal to generate a plurality of filtered samples; determining a first level, wherein a predetermined number of the plurality of filtered samples have levels above the first level; determining a second level, wherein the second level is a minimum level of levels for the plurality of filtered samples; and determining the slice level by adding the first level and the second level to generate a summed level, and dividing the summed level by two to determine the slice level.

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

Abstract: Methods and apparatus are described for time-correct combination of two data streams, particularly video data streams. In this case, a sync signal of the first video data stream is a horizontal sync signal. In this case, methods and apparatus are provided to combine the two video data streams in a pixel-precise manner, even though time base error, i.e. discontinuities occur in the second video data stream.

Abstract: A method for estimating a level of a predetermined portion of a video signal comprising the steps of determining a location of the predetermined portion of the video signal, sampling the video signal during the predetermined portion and estimating the level as an average of the samples of the video signal during the predetermined portion.

Abstract: A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip.

Abstract: A synchronous signal separation circuit 2 for separating horizontal synchronous signal HSn is connected to a horizontal synchronous signal detection circuit 3, which includes a switch 4, an oscillator 5 and a window signal generator 6 for generating a window signal WP. The switch 4 passes the separated horizontal synchronous signal HSn during an open-period of the window signal WP and intercepts the separated horizontal synchronous signal HSn during a close-period of the window signal. The oscillator 5 generates a rate signal having a period equal to a horizontal scan period synchronously with a change in an output signal HS from the switch circuit, and adjusts a time duration of the open period of the window signal so as to make a timing of a change in the output signal HS coincide with a generation timing of the rate signal while the open-period of the window signal is synchronized with the generation timing of the rate signal.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: There can be solved a problem in which a lock range is narrowed by using an oscillator such as a ceramic having a high Q and a horizontal deflection frequency generating system compatible with all horizontal deflection frequencies of a variety of television systems cannot be formed without difficulty. This system includes a frequency-fixed oscillator oscillating at a frequency f0 sufficiently higher than a deflection frequency fh in a multi-scan display, a first counter for counting a clock outputted from said oscillator in a descending order, a duration in which an integer n which results from rounding a decimal point of a value obtained by a division of f0 fh is divided by an integer m smaller than n and said first counter counts a value k thus obtained k times is set to one cycle and a duration in which a second counter for counting a value m times repeats the counting m cycles is set to one period and thereby generating a deflection frequency fh.

Abstract: An ITU-R BT.656 (or similar) digital video signal is converted to analog at which point a simple 7-state state machine in combination with a 6 bit binary counter generates tri-level synchronized video. The state machine receives vertical and horizontal synchronization signals as well as End-Active-Video and Start-Active-Video signals from the ITU-R BT.656 video. A pixel clock clocks the 6 bit binary counter. Active video is passed directly to the output. Horizontal and vertical sync signals are mirrored at the output with the state machine generating a positive tri-level signal immediately following the horizontal synchronization signal. The high level signal is generated for a period of 44 pixel counts as counted by the 6 bit counter.

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

Abstract: A horizontal display size compensation circuit for a monitor prevents a horizontal display size of a monitor screen from being changed when a horizontal frequency varies according to a video mode. A horizontal frequency is generated by a horizontal frequency generation section corresponding to each video mode. A microcomputer generates a predetermined horizontal display size compensation signal according to the horizontal frequency corresponding to each video mode and a horizontal display size adjustment signal corresponding to an input of a key input section, and a horizontal display size control section controls a horizontal display size of the monitor screen by supplying the horizontal display size adjustment signal of the microcomputer and the horizontal display size compensation signal to the horizontal frequency. Therefore, a horizontal display size of a monitor screen is prevented from varying according to a video mode.

Abstract: A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. To that end, the following improvement measures are proposed: a) an accurate determination of the position of a line synchronization pulse is effected by carrying out a convolution operation between the video signal for the video line and a pattern function. The exact position is then established by analysis of the result function (&phgr;sv(k)) of the convolution operation. B) time-domain filtering of the established positions of the line synchronization pulses is carried out, in which a linear or non-linear estimation for the purpose of determining the corrected positions of the line synchronization pulses is carried out in each case. The invention also relates to an apparatus for carrying out the method.

Abstract: A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses.

Abstract: A level is preset into a counter. The level held in the counter is compared with the minimum value of the present video signal by a level detecting circuit. When the minimum value of the present video signal is lower than the level of the counter, the intermediate value between the value of the counter so far and the minimum value of the present video signal is obtained by an intermediate value calculating circuit, thereby presetting the counter and updating the level. Thus, the value of the counter gradually approaches a sync chip level. The video signal is sliced by a slice level formed on the basis of the value of the counter by a slice circuit, thereby extracting the sync signal. Further, in a mask signal generating circuit, the updating of the level is inhibited for a predetermined time after the updating of the level was performed for a predetermined period of time, thereby preventing the level from being influenced by the noise for the video period.

Abstract: A signal treatment circuit treats an input signal containing line sync pulses used for displaying data on a screen. The circuit contains a phase locked loop to control horizontal sweeping according to active edges of line sync pulses, and a filter circuit that filters equalizing signals from the input signals and provides a filtered input signal to the phase locked loop.

Abstract: A luminance signal generation circuit with single clamp generates a separate luminance signal Y by combining RGB input signals in a weighted manner within a Y-Matrix circuit. During a burst period the single clamping circuit is enabled. When enabled, the single clamping circuit compares the separate luminance signal Y to a constant reference voltage signal. A difference signal, representing the difference between the separate luminance signal Y and the constant reference voltage signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the constant reference voltage signal. During the non-burst periods the single clamping circuit is disabled and the Y-Matrix circuit combines the RGB input signals into the separate luminance signal Y. Preferably, the single clamping circuit sets the blank level of the separate luminance signal Y to a level equal to two volts.

Abstract: A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Abstract: A horizontal sync separator that is capable of operating with horizontal sync signals of differing durations. A monostable is operated by the leading inverted negative edge of the horizontal sync pulse and generates a minimum duration horizontal pulse. The minimum duration horizontal pulse is applied along with the inverted negative horizontal pulse to an OR gate which outputs the longer of the two pulses. The arrangement assures proper video clamping during the horizontal back porch interval.

Abstract: An apparatus for generating a sync signal of a data segment in a high definition television is disclosed including: a circuit (41) for delaying and integrating received data segment signals in the period of the segment; a delay circuit (42) for delaying the output of the circuit in the period of sync signals, multiplying the delayed sync signals by a correlation value of a corresponding sync signal, and summing the multiplied sync signals, to thereby detect a sync signal having its peak for the period of the sync signal; and a circuit (43) having a predetermined reference value and for comparing the output of the sync detecting circuit with the reference value, to thereby generate the sync signal of data segment. This apparatus is capable of accurately generating segment sync signals in any environment of transmission channel in an HDTV.

Abstract: A field decision unit capable of solving a problem involved in a conventional field decision unit in that an internal synchronizing signal can be erroneously synchronized with the equalizing pulses of a video signal owing to noise because the output halt period of a phase comparator is set rather short considering that this will facilitate the synchronization of the internal synchronizing signal with the video signal when starting the system or the like, and hence an incorrect field decision can be made. The present field decision unit includes an output controller which sets output halt pulses with a longer output halt period in a particular interval consisting of the synchronizing cycles containing the equalizing pulses and a synchronizing cycle previous thereto, and which employs output halt pulses with a shorter output halt period outside the particular interval as in the conventional system.

Abstract: In a Sync signal detection circuit for detecting a Sync signal included in a television signal transmitted in a digital mode, pattern check means 2 checks a pattern of a Sync signal which is super imposed on a series of input data with a reference pattern. Based on a check result, Sync detection determination means 5 outputs a Sync detected signal or a Sync non-detected signal. Sync detection initialization means is further provided to this detection circuit for outputting forcibly a Sync non-detected signal when a signal of a series of input data is switched over. As a result, a Sync signal can be detected within a shorter period than the conventional circuit structure.

Abstract: A horizontal phase detection circuit and system detects the phase of the horizontal synchronization pulse for a horizontal synchronization phase lock loop using positive and negative fractional error compensation. The positive and negative fractional errors are determined to get a more accurate detection of where a horizontal synchronization pulse crosses a synchronization signal slice level. Using both positive and negative fractional compensation, the circuit and method detects the horizontal synchronization pulse width and center of the pulse. In addition, if desired, an adaptive slice level generator generates a variable slice level threshold based on a signal strength of the input video signal to facilitate improved detection in the cases where the video information is weak even after gain control has been applied.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.

Abstract: The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.