Abstract: A video display apparatus comprises a phase-locked loop receiving a horizontal synchronous signal for generating an oscillation signal following the frequency of the horizontal synchronous signal, a tracking circuit for generating a tracking control signal for moving the frequency of the oscillation signal into a predetermined capture range of the phase-locked loop when the frequency of the horizontal synchronous signal changes, so that the frequency of the oscillation signal follows the frequency of the horizontal synchronous signal, and an output circuit receiving and amplifying the oscillation signal to output a horizontal output signal.

Abstract: A digital pulse filtering circuit for processing composite sync signals is provided. The digital pulse filtering circuit can determine the polarity of an input composite sync signal composed of a horizontal sync signal and a vertical sync signal. The horizontal sync signal is a first periodic pulse train having a first pulse width, while the vertical sync signal is a second periodic pulse train having a second pulse width. The digital pulse filtering circuit includes a horizontal sync filter for filtering out all pulses in the input composite sync signal that have a pulse width less than the pulse width of the horizontal sync signal; and a vertical sync filter, coupled to receive the output of said horizontal sync filter, for filtering out all pulses in the output of said horizontal sync filter that have a pulse width less than the pulse width of the vertical sync signal. The output of said indicating the polarity of the input composite sync signal.

Abstract: A horizontal synchronization signal generating circuit self-generates a horizontal synchronization signal if an actual horizontal synchronization signal fails to be detected in a composite video signal. Each time an edge-detection circuit detects an actual horizontal synchronization pulse, a counter and decoder are reset. An actual horizontal synchronization signal has a period of 63.5 .mu.s. If the edge detection circuit fails to detect the actual horizontal synchronization signal, then the decoder outputs a self-generated horizontal synchronization signal at 64 .mu.s and a selector circuit disables the edge detection circuit for approximately 35 .mu.s. In contrast, if the edge-detection circuit detects an actual horizontal synchronization signal, the decoder is reset before it can output the self-generated signal and the selector disables the edge detection circuit for approximately 60 .mu.s. Accordingly, a period of 35 .mu.

Abstract: The invention pertains to a digital video horizontal synchronization pulse detector and processor comprising pulse detector for generating a timing pulse in response to each horizontal synchronization pulse. A sync position error device generates a time position error signal for each timing pulse relative to a corresponding window pulse. A window pulse generator generates the window pulses and limits the time position error signals to a maximum value. An acquisition device tracks when the timing pulses occur inside and outside the corresponding window pulses. An averaging device averages the time position error signals to generate an average error signal.

Abstract: When two projecting units or more project two pictures or more obtained from video signals and luminance levels of projected pictures at an overlapped portion thereof are adjusted, a picture to be adjusted is selected from the projected pictures. One of processings for adjusting a correction start point of a correction data, a correction end point thereof and an inclination of a correction curve thereof to be used for a picture adjustment is selected. When the positions of a correction start point and/or a correction end point of the correction data are adjusted by using a remote controller unit or the like, a mark data is superposed on the correction start point and/or the correction end point of the correction data to display a mark formed based on the mark data on the screen together with the projected pictures. Thus, the picture is adjusted by displaying the marks together with the projected pictures.

Abstract: A circuit for removing every other equalizing pulse from a signal representing the sync pulses of a composite video signal, generates an output signal representative of every horizontal synchronization pulse and every other vertical synchronization pulse within the composite video signal. A sync separator circuit separates the synchronization pulses from the composite video signal. An output of the sync separator circuit includes all of the horizontal synchronization pulses and vertical synchronization pulses. The vertical synchronization pulses include equalizing pulses and serration pulses which have a frequency which is twice the frequency of the horizontal synchronization pulses. A capacitor is used to store charge. A current source charges the capacitor. A transistor controlled by the output signal provides a discharge path for the capacitor.

Abstract: A pulse separator 110 predicts the start of a vertical synchronizing pulse in a video composite synchronizing signal (VCSS) applied via input 105. At a predicted time, the pulse separator 110 provides a start signal via a first output to the bistable 125, thereby causing a signal at output 130 to vary from a first output level to a second output level. When the end of the vertical synchronizing pulse is detected in the VCSS, a stop signal is provided via a second output to the bistable 125, thereby causing the signal at the output 130 to vary from the second level to the first level. A multiplexer (MUX) 615 switched to couple horizontal synchronizing pulses from input 605 to output 620, when a vertical synchronizing pulse is received from input 625, and, switched to coupled pseudo horizontal synchronizing pulses from pseudo pulse generator 610 to the output 620 when a vertical synchronizing pulse is not received from the input 625.

Abstract: A display apparatus for receiving a picture signal having video and synchronizing components includes a matrix of display cells arranged in an array of M columns by N rows. Display cells in the matrix are individually addressable by row and column signals so as to receive the video component of the picture signal in response thereto. A first shift circuit coupled to the matrix provides the column signals in response to a first clocking signal. A second shift circuit coupled to the matrix provides the row signals in response to a second clocking signal. A synchronizing detector or gate circuit coupled to the first and second shift circuits receives the synchronizing component of the picture signal and produces the second clocking signal in response to a preselected pointer signal from the first shift circuit. A phase locked loop circuit coupled to the first shift circuit receives the second clocking signal and produces the first clocking signal in response thereto.

Abstract: A synchronizing arrangement includes a window circuit (WINC1,WINC2) for generating a periodic window signal (LW,RW), and a gate circuit (GC) for supplying a periodic gating pulse (Hp). The gating pulse (Hp) is related to a presented synchronizing pulse (Hs) if the presented synchronizing pulse (Hs) occurs during the window signal (LW,RW). The gate circuit (GC) generates the gating pulse (Hp) related to a leading edge of the window signal (LW) if the presented synchronizing pulse (Hs) occurs before the start of the window signal (LW,RW), and the gate circuit (GC) generates the gating pulse (Hp) related to a trailing edge of the window signal (RW) if the presented synchronizing pulse (Hs) occurs after the end of the window signal (LW,RW).

Abstract: A line sync detector for a digital television receiver receives digital television data including line synchronization code groups of four symbols having successive values of +S, -S, -S and +S at the beginning of each data line, S being a prescribed sample level. A first delay line has an input tap to which the digital television data are supplied, an output tap, first and second intermediate taps, a first symbol latch having an input connection from the input tap and having an output connection to the first intermediate tap, a second symbol latch having an input connection from the first intermediate tap and having an output connection to the second intermediate tap, and a third symbol latch having an input connection from the second intermediate tap and having an output connection to the output tap. The signals at the input tap, the first and second intermediate taps and the output tap of the first delay line are combined in 1:(-1):(-1):1 ratio to generate a combined response.

Abstract: There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.

Abstract: An integrated active filter and sync separator circuit operates on precision internal reference sources to set the filter cut off frequency as a function of resistance of an external resistor. The active filter eliminates the source of sync tip crushing attributable to conventional clamping circuits associated with sync pulse detectors, and also provides sync pulses substantially devoid of time-variant jitter.

Abstract: Apparatus and method are provided which receive and sample an incoming video image signal asynchronously, and then processes the signal to recover the video image, including video format, for conversion into a preselected video format. The apparatus and methods first sample the video signal using a stable (crystal oscillator) time base clock to reconstruct the frequency of the video signal, i.e., to recover the video format and then using a contrast optimization process to determine the video signal pixel clock rate.

Abstract: The apparatus of the invention includes an edge detection circuit, a divide-by-N circuit and a latch. The edge detection circuit, responsive to an edge of the input signal, generates a trigger signal of a first frequency. The divide-by-N circuit inputs the trigger signal and generates a latch signal of a second frequency. The second frequency is equal to the first frequency divided by N. The latch inputs the input signal, and responsive to the latch signal, latches the input signal and outputs a polarity value representative of the polarity of the input signal.

Abstract: A composite synchronizing signal separation circuit in which separation of the composite synchronizing signal by a digital circuit is realized and such trouble as adjusting the time constant is not needed and a phase shift is reduced: a horizontal interruption receiving circuit 1 which is reset by a timing pulse signal at the time point of 3/4 from the starting time point of one horizontal synchronizing period, and separates and outputs a horizontal synchronizing signal HD from a composite synchronizing signal SYNC; a schedule counter circuit 2 which is reset by the horizontal synchronizing signal HD and outputs count value while counting up to a predetermined value in one horizontal synchronizing period; a timing decoding circuit 3 which decodes the count value and respectively outputs timing pulse signals at the time points of 1/4, 1/2 and 3/4 from the starting time point of one horizontal synchronizing period; and a vertical interruption receiving circuit 4 which samples the composite synchronizing signal

Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.