Abstract: A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

Abstract: A method of correcting color imbalance in a captured image includes deriving gradient data from a group of pixels in the captured image, determining a compensation value based on the gradient data, and applying that value to at least one pixel. Apparatus for correcting color imbalance includes a digital image processor that corrects color imbalance, in an image that is output by an image detector, according to the method. Each pixel may represent a color from a set of colors, with one particular color being a selected color, and each pixel to which the compensation value is applied representing the selected color. Where the group of pixels forms a rectangular shape, the gradient data may include horizontal and vertical gradients. The classifying may be performed according to a visual characteristic of a portion of the image, where determining the compensation value is based also on the visual characteristic.

Abstract: An image processing apparatus of the present invention includes: a video input section to which live video obtained by picking up an image of an object is inputted; a frame interpolation processing section which, by inserting an interpolated image between images of frames constituting the live video, performs processing for generating and outputting interpolated video of a frame rate set in advance; and a control section which, when an instruction for freezing video displayed on a display section is made, operates so as to cause a still image of a frame constituting the live video to be displayed on the display section.

Abstract: An image display device includes: an interpolation phase generator that generates an interpolation phase on the basis of downsampling frame information representing a downsampling timing at which at least one frame image of the image signal is thinned, and an interpolation frame generator that generates an interpolation frame image corresponding to the interpolation phase. The interpolation phase generator generates the interpolation phase such that a phase distance between a first interpolation frame image from among a plurality of interpolation frame images within one period of downsampling periods, and a second interpolation frame image that follows the first interpolation frame image becomes equal to a phase distance between mutually adjacent interpolation frame images obtained when phase distances between a plurality of interpolation frame images are equalized within one period of the downsampling periods.

Abstract: A de-interlacing device and method are provided that may be used in a memory based video processor. The de-interlacer mixes the output of a temporal de-interlacer and a spatial de-interlacer. Two separate error values are used; one for the temporal de-interlacer and another for the spatial de-interlacer. The de-interlacing device calculates from the two error values, using a non-linear mapping, a mix factor used to mix between the outputs of the spatial and temporal de-interlacers.

Abstract: Evolution of a scene represented in a video sequence of input frames is analyzed. Output pixels of an output frame having a time position intermediate between time positions of the input frames are computed by combining respective input pixels of the input frames.

Abstract: Disclosed herein is an image processing apparatus including an interlace/progressive conversion section configured to carry out interpolation processing on image data of the current field by making use of the image data of the current field and image data of a field leading ahead of the current field by one field period in order to obtain image data of a progressive system with no delay time.

Abstract: Spatial or temporal interpolation may be performed upon source video content to create interpolated video content. A video signal including the interpolated video content and non-interpolated video content (e.g. the source video content) may be generated. At least one indicator for distinguishing the non-interpolated video content from the interpolated video content may also be generated. The video signal and indicator(s) may be passed from a video source device to a video sink device. The received indicator(s) may be used to distinguish the non-interpolated video content from the interpolated video content in the received video signal. The non-interpolated video content may be used to “redo” the interpolation or may be recorded to a storage medium.

Abstract: An image processing apparatus includes: a normal interpolated image generation unit to generate an image that is interpolated between a plurality of original images reproduced along time series, the image being a normal interpolated image, based on each of the plurality of original images; a high-frequency area extraction unit to extract a high-frequency area having a spatial frequency higher than a predetermined value in each of the plurality of original images; a high-frequency area interpolated image generation unit to generate an image that is interpolated between the plurality of original images, the image being a high-frequency area interpolated image, based on a change in position of the high-frequency area along with an elapse of time on the time series and on each of the plurality of original images; and a combination unit to execute combining processing to combine the normal interpolated image and the high-frequency area interpolated image.

Abstract: A frame rate conversion method includes detecting a plurality of input frames to determine an image mode corresponding to the plurality of input frames; performing motion estimation on the plurality of input frames to generate a motion estimation result; and interpolating a plurality of interpolated frames according to the determined image mode, the motion estimation result and the plurality of input frames to generate a plurality of converted output frames, wherein a frame rate of the outputted frames is different from that of the input frames.

Abstract: An image signal processing apparatus includes: a color-data generator that generates color data of a correction coordinate point by interpolating color data of pixels in the same color line above and below the correction coordinate point; a first luminance generator that generates first luminance data of the correction coordinate point by interpolating the luminance data of the pixels in the same color line above and below the correction coordinate point; a second luminance generator that generates second luminance data of the correction coordinate point by interpolating the luminance data of the pixels above and below the correction coordinate point; and a complementary-color-data generator that generates the complementary-color data of the correction coordinate point based on the generated color data, the first luminance data, and the second luminance data.

Abstract: A method and system for interpolating video pixels is described, in which the value of a first fractional pixel is calculated based on the values of the first set of integer pixels, while the value of a second fractional pixel is calculated based on the values of the second set of integer pixels. The first set of integer pixels is not equal to the second set of integer pixels. For example, the first and second set may contain different integer pixels and may contain different numbers of integer pixels.

Abstract: Automatic recalculation of tuner filter coefficients are made in order to compensate for changes in signal properties due to processing functionality in the tuner. The architecture compensates for processing changes, such as a large continuous range of clock frequency shifts, while not sacrificing bandwidth response characteristics of the channel filter. Embodiments may calculate coefficients in order to obtain response characteristics while utilizing a completely on-chip architecture, which does not require accessing off-chip software driver programs, and does not require complex look-up tables containing filter coefficients stored in onboard memory.

Abstract: A super-resolution processor includes an N enlargement unit that generates an N-enlarged image by enlarging the input image by a factor N; an M enlargement unit that generates an M-enlarged image by enlarging the input image by a factor M; and a high-pass filter unit that extracts a high-frequency component of the M-enlarged image, as an M-enlarged high-frequency image. Additionally, a patch extraction unit extracts an estimated patch of a predetermined size from the M-enlarged high-frequency image, the estimated patch being a part of the M-enlarged high-frequency image; and an addition unit adds the estimated patch to a processing target block of the predetermined size in the N-enlarged image, to generate the output image, where M is smaller than N.

Abstract: There is provided a method of measuring delay variation between first and second elementary streams in a digital audiovisual data stream, comprising detecting and storing digital audiovisual data stream timestamp values, detecting and storing elementary stream timestamp values for the first and second elementary streams, interpolating the digital audiovisual data stream timestamp values and elementary stream timestamp values to form data sets having mutual sampling points, and subtracting the interpolated data set for the first elementary data stream from the interpolated data set for the second elementary data stream to form elementary stream difference values indicative of changes in delay over time between first and second elementary streams.

Abstract: A method and system for interpolating video pixels is described, in which the value of a first fractional pixel is calculated based on the values of the first set of integer pixels, while the value of a second fractional pixel is calculated based on the values of the second set of integer pixels. The first set of integer pixels is not equal to the second set of integer pixels. For example, the first and second set may contain different integer pixels and may contain different numbers of integer pixels.

Abstract: Embodiments of the claimed subject matter provide a system and process for enhancing the display of color in a graphical display. In one embodiment, a process is provided for color enhancement using a detection volume and a shift volume. In one embodiment, input from pixels, as color data, is compared to a detection volume. If the color data of an input is detected in the detection volume, the color data is modified to a corresponding position in the shift volume, the modification consisting of an enhancement to the original color.

Abstract: An information processing device for tracking the image of a tracking point within a moving image wherein contents, of multiple images which are continuous temporally, are discontinuous temporally, includes: a block-matching unit for performing block matching within the moving image, wherein a processed image and an image prior to the processed image are compared to determine the position of the tracking point within the processed image; an interpolation unit for performing interpolation processing wherein the position of the tracking point within an image not subjected to the block matching, which is an image before or after the processed image within the moving image, is determined as the position of the tracking point within the processed image; and a motion-vector calculating unit for obtaining the motion vector of the tracking point based on the position of the tracking point within the processed image determined by the block-matching unit or interpolation unit.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. In one aspect, a frame identifier in a physical layer header of the digitized signal is utilized to estimate a first phase associated with the frame identifier. The remaining portion of the physical layer header is utilized to estimate a second phase associated with the remaining portion. The first phase estimate and the second phase estimate are combined to generate a first combined phase estimate.

Abstract: Disclosed is a scaling process system including a replay apparatus and a video output apparatus which are connected via a HDMI, wherein each of the video output apparatus and the replay apparatus respectively comprises a between-pixel interpolation method table, wherein the video output apparatus including a request signal transmission device to transmit a request signal, a between-pixel interpolation method information receiving device to receive the between-pixel interpolation method information, a determining device to determine which of between-pixel interpolation method information of the replay apparatus or between-pixel interpolation method information of the video output apparatus is more high-performance, a deciding device to decide an apparatus to be used for the scaling process, and a control device to control the apparatus which is decided by the deciding device so as to carry out the scaling process, and wherein the replay apparatus including a request signal receiving device to receive the reque

Abstract: A circuit dithers pixel data on a display, and includes a lookup table module, a dithering parameter decoder, a first adder, a second adder, and an overflow handling module. A lookup table of the lookup table module stores dithering parameters generated by encoding odd and even pixel dithering parameters. The dithering parameter decoder generates second and third dithering parameters corresponding to odd and even pixels from a first dithering parameter. The first adder generates a dithered odd pixel parameter according to the odd pixel parameter and the second dithering parameter. The second adder generates a dithered even pixel parameter according to the even pixel parameter and the third dithering parameter. The overflow handling module checks for overflow, and generates an output odd pixel parameter according to the dithered odd pixel parameter, and generates an output even pixel parameter according to the dithered even pixel parameter.

Abstract: System, method, and computer program product to adaptively blend the interpolation results from an 8-tap Lanczos filter and the interpolation results from a bilinear filter, according to the local transitions of the input content. Artifacts may occur, which may be identified as such and corrected. Pixels that represent artifacts in the blended image may be replaced with the pixel for that location taken from the bilinear interpolation.

Abstract: Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.

Abstract: An imaging apparatus including an imaging function having an imaging section configured such that a plurality of pixels are arrayed in a vertical direction and a horizontal direction, images a subject; a detecting function for detecting whether the imaging apparatus including the imaging section is held vertically or horizontally; a readout function for reading out the pixels information of the plurality of the pixels from the imaging section; a first readout controlling function for controlling a readout process of the pixel information executed by the readout function, in accordance with a detection result from the detecting section; a calculating function for calculating an auto-focus evaluation value in accordance with the pixel information read out by the first readout controlling function; and a focusing function for focusing in accordance with the auto-focus evaluation value calculated by the calculating function.

Abstract: A method for detecting SECAM-L signals is disclosed. First, a SECAM-L signal is received and demodulated into a demodulation signal. Then high frequency components of the demodulation signal are filtered out and a low frequency signal, including many sync pulses and many data pulses, is obtained. Next, the low frequency signal is inversion into an inversion signal, having many inversion sync pulses and many inversion data pulses. Afterwards a voltage level of the inversion signal is detected continuously whether it is a lowest level. After that, the lowest level is determined whether belonging to the inversion sync pulses when the voltage level of the inversion signal is the lowest level, and a detection signal is outputted. When the lowest level belongs to the inversion sync pulses, a voltage level of the detection signal is high, and the demodulation signal is an inversion SECAM-L demodulation signal.

Abstract: A method of converting a frame rate of a video signal includes the steps of: receiving a pulldown film sequence existing in or converted from a sequence of successive-in-time frames of the video signal, in which the pulldown film sequence comprises a plurality of diverse original frames each having a corresponding number of duplicate frames; modifying the original frames; performing estimation of at least one motion vector associated with the modified original frames; and interpolating new frames between the modified original frames in accordance with the motion vector.

Abstract: According to an embodiment of the invention, even if a sample-and-hold circuit samples a signal from a signal processor to a display unit, an image quality reduction is hard to occur. According to an embodiment of the invention, there is provided a flat-panel display device includes a phase control circuit setting a state that a first parallel arrangement RGB pixel signal shifts by 120 degrees, a sample-and-hold circuit sampling a second parallel arrangement RGB pixel signal parallel-output from the phase control circuit to obtain a series arrangement RGB pixel signal, which is three times as much as a single pixel signal, and a driver supplying the series arrangement RGB pixel signal to the corresponding display pixel.

Abstract: Methods and apparatuses provide noise reduction in a demosaiced digital image by processing the digitized signals received from a color pattern pixel array for noise reduction previous to, or as part of, a demosaicing process by using a weight matrix.

Abstract: In a method of mapping data from a source space to a target space, a space transformation look-up table (LUT) that contains a plurality of locations storing information is maintained, wherein each of the plurality of locations includes information specifying a function to be evaluated. First data defined according to a multi-dimensional source space is input, and second data defined according to a multi-dimensional target space is generated, by applying information contained in the LUT to the first data.

Abstract: A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.

Abstract: An image processing circuit inputs pixels of an RGB Bayer array therein. A chroma value calculation circuit calculates a chroma factor (KL) for evaluating the chroma of a surrounding area of a specified pixel. A correlation value calculation circuit calculates correlation values for gray image and color image. If the chroma factor (KL) is larger than a threshold value (TH1), a correlation judgment method for color image and a pixel interpolation method for color image are selected, if the chroma factor (KL) is not larger than a threshold value (TH1) and larger than a threshold value (TH2), a correlation judgment method using a correlation value obtained by overall judgment on the correlation values for gray image and color image and a pixel interpolation method for color image are selected, and if the chroma factor (KL) is not larger than a threshold value (TH2), a correlation judgment method for gray image and a pixel interpolation method for gray image are selected.

Abstract: A method of creating a super-resolved color image from multiple lower-resolution color images is provided by combining a data fidelity penalty term, a spatial luminance penalty term, a spatial chrominance penalty term, and an inter-color dependencies penalty term to create an overall cost function. The data fidelity penalty term is an L1 norm penalty term to enforce similarities between raw data and a high-resolution image estimate, the spatial luminance penalty term is to encourage sharp edges in a luminance component to the high-resolution image, the spatial chrominance penalty term is to encourage smoothness in a chrominance component of the high-resolution image, and the inter-color dependencies penalty term is to encourage homogeneity of an edge location and orientation in different color bands. A steepest descent optimization is applied to the overall cost function for minimization by applying a derivative to each color band while the other color bands constant.

Abstract: Disclosed is a scaling process system including a replay apparatus and a video output apparatus which are connected via a HDMI, wherein each of the video output apparatus and the replay apparatus respectively comprises a between-pixel interpolation method table for deciding a superiority/inferiority of a between-pixel interpolation method which is used when carrying out a scaling process in the scaling process system, wherein the video output apparatus including a version request signal transmission device, a version information receiving device, a determining device, a control device, a between-pixel interpolation method table receiving device and a first update execution device, wherein the replay apparatus including a version request signal receiving device, a version information return device, a receiving device, a between-pixel interpolation method table transmission device and a second update executing device.

Abstract: In a method of mapping data from a source space to a target space, a space transformation look-up table (LUT) that contains a plurality of locations storing information is maintained, wherein each of the plurality of locations includes information specifying a function to be evaluated. First data defined according to a multi-dimensional source space is input, and second data defined according to a multi-dimensional target space is generated, by applying information contained in the LUT to the first data.

Abstract: Methods and apparatus for dynamic correction of data for non-uniformity are disclosed. Feature data are extracted from input video data that include a subject shot against a backing area in a solid color. The feature data may describe characteristics of non-uniformity in input video data. A curve is generated based on the extracted feature data, and correction factors are formed based on the generated curve. At least one of the input video data and alpha data associated with the input video data is corrected based on the correction factors.

Abstract: An imaging device includes a sensor having a cell layout having a plurality of chromatic color pixels and high-sensitivity pixels having higher sensitivity to incident light than the chromatic color pixels arranged in a checkerboard pattern, a white balance block that normalizes the pixel output from the sensor with respect to the chromatic color pixels or the high-sensitivity pixels, a pixel interpolation block that performs interpolation on the phase where a chromatic color pixel is present by interpolating the other lacking colors, and a noise reduction block that is situated between the white balance block and the pixel interpolation block, and performs interpolation on phases of the chromatic color pixels based on the signal component of the high-sensitivity pixels so as to suppress noise in the chromatic color pixels.

Abstract: An image processing apparatus of the present invention comprising (a) a first signal processing circuit for applying gamma correction to an n-bit (n: a natural number) digital signal inputted as a video signal and for converting the n-bit digital signal into an m-bit (m>n, m: a natural number) digital signal, and (b) a second signal processing circuit for adding a noise signal, which is used for pseudo contour reduction, into the m-bit digital signal from the first signal processing circuit and for outputting a Q-bit (Q: a natural number) digital signal, which is obtained from rounding off a less significant (m?Q) bit (Q?n) from the m-bit digital signal, to a display section.

Abstract: Phase trackers (7) for tracking phases of received data are provided with interpolators (20), error detectors (21,22), combiners (25) and indicator generators (26) for generating at least two streams of interpolated samples, for generating error signals per stream, and for generating an indicator signal for adjusting the interpolation, to avoid the use of sync words for phase tracking. The indicator generator (26) converts combined error signals into indicator signals for adjusting the interpolation through shifting sampling phases of interpolated samples.

Abstract: A signal processing circuit includes an interpolation filter for outputting an interpolation value of signal levels at positions of ¼ phase and ¾ phase between two original pixels of the input digital image adjacent in the predetermine direction; a phase shift circuit for outputting signal value of each of the two original pixels by shifting the phases of the signals of the two original pixels in the predetermined direction to ¼ phase and ¾ phase, respectively, between the two original pixels; a edge detection circuit for detecting a edge portion of the image from a signal level change of a plurality of pixels including the two original pixels of the input digital image in the predetermined direction; and a first signal selection circuit for outputting the output of the phase shift circuit when the edge is detected, and outputting the output of the interpolation filter when no edge is detected, based on the result of detection by the edge detection circuit.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wireless signal may be received. A frame identifier in a physical layer header in the signal may be identified by correlating the digitized signal to one or more known frame identifiers. The identified frame identifier may be used to estimate a phase or frequency error.

Abstract: Standard Definition signals are divided into blocks at a tap extracting unit, and pixel data contained in each block is extracted as a class tap. A class classification unit obtains class code based on the pixel data contained in the class tap. An auxiliary data generating unit generates auxiliary data regarding conversion into High Definition signals, based on the class tap extracted by the tap extracting unit. A data generation processing unit performs processing based on the class code and the auxiliary data, thereby yielding excellent High Definition signals.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wireless signal may be received. A frame identifier in a physical layer header in the signal may be identified by correlating the digitized signal to one or more known frame identifiers. The identified frame identifier may be used to estimate a phase or frequency error.

Abstract: A graphics engine includes a setup unit and a rendering unit. The setup unit computes coefficients A, B, and C used for interpolating an attribute v of a triangle to be rendered for a graphics image. The setup unit then derives compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)} based on the coefficients A, B, and C. The compressed coefficients have a fixed-point format with R integer bits left of a binary point and T fractional bits right of the binary point, where R>1 and T?0. R is selected based on the number of bits used for attribute v, T is selected based on the screen dimension, and R+T is much less than the number of bits used to represent the coefficients A, B, and C. The rendering unit performs interpolation for the attribute v using the compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)}, and may be implemented with a simple (R+T)-bit non-saturating accumulator.

Abstract: An active matrix type display panel is a hold type display panel which has a plurality of pixels arranged in a matrix form, and holds and displays an electrical signal pixel by pixel for a predetermined time. A frame rate conversion circuit converts a video signal having a first vertical frequency (60 Hz) into a video signal having a second vertical frequency (120 Hz) which is m/n-fold (wherein m is an integer of 2 or more, n is an integer of 1 or more, and conditions of m>n are satisfied) of the first vertical frequency. A time base emphasizing circuit subjects an output from the frame rate conversion circuit to time base emphasis. A drive circuit displays the video signal having the second vertical frequency in a display panel.

Abstract: An image processing apparatus obtains color image data by performing an interpolation processing for an image signal output from a color image pickup element having color filters arranged like a mosaic, by using a filter. The apparatus includes an interpolation processing unit which selectively modifies an interpolation processing according to a kind of layout pattern of a spatial center position of gravity of each color component signal included the image signal in an image area to be interpolated, so that the spatial center position of gravity of each color component signal after the interpolation processing becomes identical in any layout patter, if there are a plurality of kinds of layout pattern of a spatial center position of gravity of each color component signal included the image signal in an image area to be interpolated.

Abstract: An imager achieves a desired image resolution by successively reproducing partial images which complement each other. The imager assigns pixels from an input image to the respective partial images according to complementing patterns that correspond to the pixel pattern of the imager. The imager reproduces the complementing pattern at different spatial positions, such that the complementing patterns merge. In order to avoid perceived double imaging of moving object s the image signal provided to the imager is assembled from an original image and a motion compensated interpolated image, which is derived from at least two consecutive images. Accordingly, every other partial image that is reproduced is derived from an interpolated image and takes into account movement of objects in the image that takes place between two consecutive images. In one embodiment the partial images are re-combined into one full image in a sequence that anticipates the distribution of the pixels used in the imaging device.

Abstract: An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.

Abstract: A method is directed to recovering a digital data content in a communication system, wherein the digital data content has been converted into an analog signal based on a primary clock, at a transmitter for transmitting to a receiver. The method comprises receiving the analog signal by the receiver. The analog signal is converted into a digital signal, based on a clock of the receiver. The digital signal is interpolated at the desired interpolation point, if digital signal in time has been shifted by an amount equal to or larger than a predetermined time length. The interpolated digital signal is recovered back to the digital data content, with the assist of an estimated channel impulse response. The channel impulse response is retrained every time when the interpolation point is significantly changed.