Abstract: A device implementing a system for displaying an image includes a processor configured to, generate, during a first power state of a device, a data structure specifying image frames and a respective display time for each of the image frames, and retrieve, during a second power state of the device and from the data structure, an image frame based on the respective display time for the image frame. The at least one processor is further configured to display, during a third power state of the device, the retrieved image frame on a display of the device.

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

Abstract: Provided are a device, a differential signal line processing method and a differential signal line processing apparatus. The device includes a first component and a second component; the first component and the second component perform signal transmission via multiple sets of differential signal lines; the device further includes at least one common-mode filter, each common-mode filter of the at least one common-mode filter being serially connected between the first component and the second component via one set of differential signal lines, and a group delay of the each common-mode filter being adopted for adjusting a delay of signal transmission on the one set of differential signal lines connected to the common-mode filter.

Abstract: A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal.

Abstract: The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

Abstract: Provided is a data transmitter including a signal interval determination unit configured to receive a data input signal corresponding to data to be transmitted, determine time intervals between a synchronization signal and a plurality of data signals according to the data input signal, and output interval signals corresponding to the intervals; a trigger generation unit configured to trigger according to an output signal from the signal interval determination unit; and a signal generation unit configured to receive the trigger to generate the synchronization signal and the data signals.

Abstract: This invention discloses a clock generation circuit and a clock generation method for generating a clock. The clock generation circuit includes a reference clock generation circuit, which is installed in a chip for independently generating a reference clock; a temperature sensor for sensing an ambient temperature to generate temperature information; a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient according to the temperature information; and a clock adjusting circuit, coupled to the clock generation circuit, for generating the clock according to the reference clock and the temperature compensation coefficient. The temperature compensation module generates the temperature compensation coefficient dynamically such that the frequency of the clock approaches a target frequency and does not substantially vary with the temperature.

Abstract: A first phase difference between a first image signal output from a first pixel configured to detect a light flux having passed through a first partial area of the exit pupil, and a second image signal output from a third pixel configured to detect a light flux having passed through the entire exit pupil is computed. A second phase difference between a third image signal output from a second pixel configured to detect a light flux having passed through a second partial area of the exit pupil, and a fourth image signal output from a fourth pixel arranged at a position different from the third pixel and configured to detect a light flux having passed through the entire exit pupil is computed. The defocus amount of the imaging optical system is computed by using the sum of the first and second phase differences.

Abstract: Aspects of virtual field buffer based decoding are described. In one embodiment, a current picture field is read from a coded picture buffer comprising coded pictures of video, for example. The current picture may be associated with a top or bottom field polarity. According to decoding and picture output orders, the current picture field is assigned to an available field entry of a virtual field buffer, and an available frame index of a virtual frame map is assigned to the current picture field. The assignment of the available frame index to the current picture field is indicated to a decoder that decodes the current picture field with reference to the assigned frame index. According to aspects of the embodiments described herein, rather than determining complimentary picture fields after decoding, the assignment of complimentary picture fields to virtual frame indexes before decoding provides certain efficiencies.

Abstract: The disclosure provides a synchronous display method of an spliced display screen which comprises at least two spliced display units and at least two timing controllers respectively corresponding to the spliced display units, wherein the method comprises steps of: receiving, by each timing controller, a timing control signal for a current frame of the corresponding spliced display unit, feedback from the spliced display unit corresponding to the timing controller; determining, by each timing controller, a phase difference between the timing control signal for the current frame of the corresponding spliced display unit and a reference timing control signal received by the timing controller; judging, by each timing controller, whether or not the phase difference goes beyond a predetermined threshold range; if it is judged that the phase difference goes beyond the predetermined threshold range, generating a phase adjustment value, by the timing controller, based on the phase difference, wherein the phase adjustm

Abstract: A signal transmission device includes: at least one of a first communication device that transmits a control signal as a wireless signal and a second communication device that receives the wireless signal transmitted from the first communication device to reproduce the control signal, wherein the wireless signal for the control signal is transmitted separately from a wireless signal for a transmission subject signal which is transmitted between a third communication device and a fourth communication device.

Abstract: A high performance, low complexity phase shift network may be created with one or more non-first-order all-pass recursive filters that are built on top of a plurality of first-order and/or second-order all-pass recursive filters and/or delay lines. A target time delay, whether large or small, may be specified as a constraint for a non-first-order all-pass recursive filter. A target phase response may be determined for the non-first-order all-pass recursive filter. Phase errors between the target phase response and a calculated phase response with filter coefficients of the non-first-order all-pass recursive filter may be minimized to yield a set of optimized values for the filter coefficients of the non-first-order all-pass recursive filter.

Abstract: A display apparatus and a method of searching for a channel in the display apparatus includes a plurality of tuners and a plurality of antenna ports respectively connected to the plurality of tuners. The method includes receiving a channel search command; if the channel search command is input, searching for one of the plurality of antenna ports that is connected to a satellite antenna to receive a broadcasting signal, if one of the plurality of antenna ports is connected to the satellite antenna to receive the broadcasting signal, setting one of the plurality of tuners connected to the one antenna port, to a main tuner, and performing a channel search through the tuner set to the main tuner. Therefore, although an antenna port connected to one of the plurality of tuners initially set to a sub tuner, the display apparatus performs a channel search through the corresponding tuner.

Abstract: A method and device regenerating a pixel clock signal, the method comprising, and the device being configured for: determining a first drift value D1 representative of a first time difference between a reference clock signal RC and a local clock signal LC based on a local pixel clock signal LPC; adjusting the local pixel clock signal LPC according to an adjustment command to provide a regenerated pixel clock signal RPC; determining a second drift value D2 representative of a second time difference between the reference clock signal RC and a regenerated clock signal based on the regenerated pixel clock signal RPC; and providing the adjustment command to the adjustable clock generator 32; 132; 316 for adjusting the local pixel clock signal LPC, wherein the adjustment command is based on the difference between the determined first and second drift values.

Abstract: A display apparatus includes an image processor commonly provided to a plurality of channels, and configured to provide processing to an image signal of a selected channel selected by a channel switch in accordance with a parameter, a parameter acquirer commonly provided to the plurality of channels, and configured to obtain the parameter in accordance with a format of the image signal of the selected channel, a memory controller configured to hold the parameter for a first channel in a memory while a detector detects the image signal in the first channel even after the channel switch switches from the first channel to a second channel, and to delete the parameter when the detector detects no image signal in the first channel, and an image processing controller configured to set the parameter to the image processor without acquiring a new parameter from the parameter acquirer.

Abstract: An exemplary embodiment of the present invention provides a latency stabilization system for stabilizing the display latency between a source and a renderer over an IP network. The latency stabilization system comprises a frequency syntonization module, a frequency lock detection module, and a phase correction module. The frequency syntonization module can be configured to syntonize a frequency of a source signal from the source and a frequency of a display signal to be displayed on the renderer. The frequency lock detection module can be configured to detect whether the frequency of the source signal and the frequency of the display signal are locked. The phase correction module can be configured to, synchronize a phase of the source signal and a phase of the display signal, and generate correction data based in part on synchronization of the phase of the source signal and the phase of the display signal.

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.

Abstract: Battery-powered portable scanner, comprising: a scanning unit for scanning documents and forming digital representations thereof; a processor, communicatively connected to the scanning unit and provided for controlling the scanning operation; at least a first embedded storage capabilities, each of which is communicatively connected to the processor and each of which comprises either an internal memory for internally storing the digital representations or a communication link to an external storage medium for externally storing the digital representations. The processor is provided for enabling autonomous operation without connection to a terminal. The processor may be provided with an embedded routing application which is provided for routing the digital representations to a predetermined selection among the embedded storage capabilities.

Abstract: An exemplary embodiment of the present invention provides a latency stabilization system for stabilizing the display latency between a source and a renderer over an IP network. The latency stabilization system comprises a frequency syntonization module, a frequency lock detection module, and a phase correction module. The frequency syntonization module can be configured to syntonize a frequency of a source signal from the source and a frequency of a display signal to be displayed on the renderer. The frequency lock detection module can be configured to detect whether the frequency of the source signal and the frequency of the display signal are locked. The phase correction module can be configured to, synchronize a phase of the source signal and a phase of the display signal, and generate correction data based in part on synchronization of the phase of the source signal and the phase of the display signal.

Abstract: A monitoring apparatus includes a detection circuit, a filter circuit, an amplifying circuit, a regulation circuit, a delay and charging circuit, and a driving circuit. The detection circuit receives a video signal, and performs an operation to obtain an image signal from the video signal. The filter circuit obtains an average intensity of a luminance signal corresponding to the image signal. The delay and charging circuit charges an input capacitor when receiving a low level regulated signal from the amplifying circuit. The driving circuit activates an alarm when a charging voltage of the chargeable capacitor exceeds a predetermined value.

Abstract: An apparatus may include a link component and a display component. The link component may be operative to receive media content via data frames over a display interconnect, the data frames received periodically in succession at a first rate corresponding to a native frame rate of the media content. The display component may be operative to display the data frames in succession at a second rate corresponding to a native refresh rate of the display component, the display component operative to re-display data frames already shown to maintain the second rate when new data frames have not been received over the display interconnect.

Abstract: The display apparatus includes an image display element being driven based on a digital video signal, a quantizing part converting an input analog image signal into the digital video signal based on a quantization phase and a quantization frequency, and a converting part converting an input value into an output value, the input value being a difference value of signal values of pixels adjacent to each other in the digital video signal. The apparatus includes an accumulating part accumulating the output values from the converting part that converts the difference values obtained over entire pixels in one frame of the digital video signal to produce an accumulation evaluation value, and a controller adjusting the quantization phase in the quantizing part such that the accumulation evaluation value becomes maximum. The output values a(m) for the input values k1, k2 and k3 satisfy conditions of a(k1+1)?a(k1)<a(k2+1)?a(k2), a(k2+1)?a(k2)=a(k3+1)?a(k3) and k1<mi-1?k2<k3<mi.

Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: According to embodiments, a synchronization signal generating device includes: a cycle measuring unit configured to measure the vertical synchronization interval of the input video signal; a phase difference detecting unit configured to detect a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal; and a vertical cycle determining unit configured to determine a cycle of the display vertical synchronization signal based on a measurement result of the cycle measuring unit and a detection result of the phase difference detecting unit so that the phase difference is decreased within the range of the compensation interval, and to determine 1/n of the cycle of the display vertical synchronization signal as a cycle of an n-times speed vertical synchronization signal.

Abstract: Disclosed herein is a signal transmission system including: a first signal processing section configured to perform signal processing on a basis of a reference signal; a high-frequency reference signal generating section configured to generate and transmit a high-frequency reference signal having a higher frequency than the reference signal such that the high-frequency reference signal is synchronized with the reference signal; a low-frequency reference signal generating section configured to receive the high-frequency reference signal from the high-frequency reference signal generating section, and generate a low-frequency reference signal having a lower frequency than the high-frequency reference signal such that the low-frequency reference signal is synchronized with the received high-frequency reference signal; and a second signal processing section configured to perform signal processing on a basis of the low-frequency reference signal generated by the low-frequency reference signal generating section.

Abstract: The front-end integrated circuit includes a first clock unit receiving a reference clock signal from an oscillator and generating a first clock signal, a first analog front end module receiving and processing a first broadcast signal using the first clock signal, a second clock unit receiving the reference clock signal and generating a second clock signal, and a second analog front end module receiving and processing a second broadcast signal using the second clock signal.

Abstract: A synchronization signal control circuit according to embodiments includes a phase difference detecting section and a vertical synchronization correction control section. When a vertical synchronization period of an input video signal is within a compensation period range between a minimum vertical synchronization period and a maximum vertical synchronization period, the synchronization signal control circuit outputs a display vertical synchronization signal used for displaying the input video signal to a display section capable of providing a display based on the input video signal. The phase difference detecting section detects a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal. The vertical synchronization correction control section corrects the cycle period of the display vertical synchronization signal within the compensation period range so as to reduce the phase difference.

Abstract: A phase synchronization circuit includes a low-pass filter configured to integrate the pulse signal output from a charge pump, and a line filter configured to be provided on a control voltage supply line for supplying the control voltage from the low-pass filter to a voltage controlled oscillation circuit. Here, one end of a capacitor of the line filter is connected, through resistance of a CP current switching circuit, from an output terminal of the charge pump to the ground in terms of high frequencies.

Abstract: The present invention relates to the domain of video equipment. It relates to a phase-locked loop able to recover the timing of a synchronization signal comprising a temporal discontinuity of amaximum amplitude equal to PCR_Modulus, the loop comprising: a sample comparator comparing the samples and the local samples of a synthesized signal, means for producing the synthesized signal from a corrected signal, a corrector receiving a comparison result delivered by the comparison means and delivering the corrected signal, According to the invention, the comparison means comprises the means to determine a difference in value between the local samples and the samples of the synchronization signal and in that the comparison result has a value that depends on the value ? and on the difference between the value ? and the value PCR_Modulus/2.

Abstract: The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: A method may include receiving, by a user equipment incapable of transmitting and receiving simultaneously, a schedule to transmit data on an uplink, detecting, by the user equipment, whether there is data to be transmitted on the uplink, and receiving, by the user equipment, during a time corresponding to the schedule, data associated with a downlink, when it is determined that there is no data to be transmitted.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Abstract: The present invention relates to a technology of appropriately improving image resolution. According to an image signal processing method of the present invention, an input video signal contains an image signal whose pixel size is converted at a specified magnification scale. The input image signal is used to calculate sampling frequencies for image signals before and after the pixel size conversion. A ratio of sampling frequencies before and after the pixel size conversion is used to determine the specified magnification scale. A sampling phase for the image signal before the pixel size conversion is calculated from the input image signal after the pixel size conversion. A sampling carrier for the image signal before the pixel size conversion is generated from the sampling frequency and the sampling phase both before the pixel size conversion.

Abstract: A timing recovery loop includes a sampler, a narrow band filter, an RMS normalizer, a timing error detector, and a sample controller. The sampler samples a received signal. The narrow band filter filters the sampled received signal so as to pass an upper band edge of the received signal and not a lower band edge of the received signal. The RMS normalizer sets an average power level of an output of the filter to a substantially constant value. The timing error detector detects a timing error with respect to an output of the RMS normalizer. The sample controller controls the sampler in response to the detected timing error.

Abstract: A display apparatus including an analog-to-digital converter (ADC) module, a phase detecting module, and a clock generator is provided. The ADC module is used to receive a first analog video signal, and convert the first analog video signal into a digital signal according to a clock signal. The first analog video signal includes a first synchronous information and a first video information. The phase detecting module is used to receive the digital signal, and output a phase adjustment signal according to a part of the digital signal corresponding to the first synchronous information. The clock generator is used to output the clock signal according to the phase adjustment signal.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A frequency adjusting method comprises steps of: generating a first adjusting signal according to a frequency of a first output signal; adjusting a frequency of an input signal by using the first adjusting signal to generate the first output signal, so as to adjust the frequency of the first output signal into a first range; generating a second adjusting signal according to a frequency of a second output signal; adjusting the frequency of the first output signal by using the second adjusting signal to generate the second output signal, so as to adjust the frequency of the second output signal into a second range; and adjusting the first adjusting signal and the second adjusting signal according to the second adjusting signal.

Abstract: The present invention provides a display apparatus, comprising: an a light source for emitting illumination light for transmitting along illumination light path; a display device includes a plurality of pixels for modulating the illumination light for reflecting the illumination light along a projection light path after said illumination light is modulated by said display device; light path change actuator for changing the projection light paths; and a control circuit for controlling the light source, wherein the control circuit controls the light source in response to changes of the projection light path.

Abstract: A transmitting device in accordance with the present invention includes an encoding unit that converts an input video signal into encoded data and sends out the encoded data to a transmission line, and a synchronization signal generation unit that generates a synchronization signal SYNC for adjusting the phase of an input video signal on the basis of phase information transmitted through the transmission line, wherein the phase information PHS includes information indicating that a timing of a synchronization signal generated by the synchronization signal generation unit is to be advanced by the time necessary for transmission, and the synchronization signal generation unit generates the synchronization signal SYNC so that an input video signal is advanced by the time necessary for transmission.

Abstract: A method of synchronizing the phase of a local image synchronization signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronization signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronization signal generators generating periodic image synchronization signals in synchronism with the reference and local clocks respectively including: frequency synchronizing the local and reference clocks; sending an image timing packet providing reference image synchronization data indicating the difference in timing, measured with respect to the reference processor's clock, between the time at which the image timing packet is launched onto the network and the time of production of a reference image synchronization signal; and controlling the timing of the production of the local image synchronization si

Abstract: A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences as a function of columnar location. The sampling clock frequency is changed by an amount dependent on the period of the columnar differences. A second measure of the difference between successive frames is computed for a sequence of clock phases. The frequency of the clock is verified using a characteristic of the second measure. The characteristic can be the ratio of the maximum to the minimum of the second measure over selected clock phases. Other characteristics can be used such as a difference of a maximum and a minimum measure.

Abstract: A method may include receiving, by a user equipment incapable of transmitting and receiving simultaneously, a schedule to transmit data on an uplink, detecting, by the user equipment, whether there is data to be transmitted on the uplink, and receiving, by the user equipment, during a time corresponding to the schedule, data associated with a downlink, when it is determined that there is no data to be transmitted.

Abstract: A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.