Abstract: Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Abstract: A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods.

Abstract: Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

Abstract: A lift transmitting component (1), particularly for a gas exchange valve train or a fuel pump drive of an internal combustion engine, and a method of manufacturing such a lift transmitting component comprising a housing (2) and a bearing pin (6) fixed in a reception bore (5) of the housing (2) as also a roller (4) rotatable about the bearing pin (6) and optionally mounted on a rolling bearing, said bearing pin (6) being connected to the housing (2) by positive engagement through radially widened front ends (8), the bearing pin (6) is core-hardened over its entire length with a core hardness of at least 58 HRC and its front ends (8) are widened by radial spot riveting.

Abstract: A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods.

Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.

Abstract: Apparatuses and methods are described for performing time base correction and frame rate conversion with respect to signals. An apparatus includes circuitry to synthesize an output video clock. The apparatus has circuitry that receives an input video synchronization signal. The apparatus has circuitry to change a frequency of the output video clock based on an intended number of video clock cycles per input vertical period and a period of the input video synchronization signal.

Abstract: A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the respective input of respective fields/frames of an underlying video data screen in particular on the basis of a time difference which is given by respective counted times and/or temporal changes and/or variations thereof.

Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.

Abstract: There is provided a vertical frequency distinction circuit and a vertical frequency distinction method capable of reducing a chip area, and a video display apparatus having the vertical frequency distinction circuit. A vertical control pulse generating section of the vertical frequency distinction circuit generates a noise eliminating signal for disabling input of noise during a predetermined period until arrival of a vertical synchronization signal. A distinction result latch section samples the noise eliminating signal and an inversion signal of the noise eliminating signal at the timing of input of the vertical synchronization signal, to generate two output signals. An output selecting section selects either one of the two output signals of the distinction result latch section based on a mode setting signal, to output the selected signal as a distinction result signal.

Abstract: A display synchronization signal generation apparatus and method, which make it possible to display a stable image irrespective of changes of horizontal and vertical frequencies of a received analog video signal in an analog video signal receiver. The display synchronization signal generation apparatus includes a detection unit, a change amount conversion unit, and a vertical synchronization signal generation unit. The detection unit detects an amount of change in a vertical period of an input video signal by comparing current and previous vertical periods of the input video signal. The change amount conversion unit converts the detected amount of change into the amount of change in a vertical period of a video signal to be displayed, using the current vertical period and the total number of pixels per frame. The vertical synchronization signal generation unit generates a vertical synchronization signal of the video signal to be displayed.

Abstract: In a phase-locked loop circuit, a vertical synchronous separation circuit separates a vertical sync signal from a composite synchronizing signal to detect part of a vertical synchronizing period. A mask circuit masks the composite synchronizing signal during a predetermined period. A selector selects a reference signal or the composite synchronizing signal in accordance with the detection output from the vertical synchronous separation circuit. A phase comparator detects a phase difference between the output from the selector and the reference signal. A voltage-controlled oscillator changes an oscillation frequency upon receiving the output from the phase comparator through a low-pass filter. A counter counts the oscillation output from the voltage-controlled oscillator. A decoder circuit decodes the output from the counter to generate the reference signal, supplies it to the selector and the phase comparator, and resets the counter at a predetermined period.

Abstract: There is provided a vertical timing signal generating circuit which can operate stably irrespective of the phase relationship between a vertical synchronous signal and a vertical timing signal generated by a counter, and can provide a vertical timing signal having a desired phase. Delay circuit 100 receives vertical synchronous signal Pc 123, outputs as a reset signal a signal which is delayed in phase with respect to input vertical synchronous signal Pc 123 by a predetermined phase, and vertical counter 103 receives horizontal synchronous signal Pb 121 and reset signal Pe 125 outputted from delay circuit 100 and resets the count by using reset signal Pe 125 to count a predetermined number of horizontal synchronous signals 121, thereafter outputting vertical timing signal Pd 127.

Abstract: In a synchronization stabilizing circuit and a television signal receiver, the follow-up range (TX) of the synchronizing signal (SH) is changed based on the judged result (J1) that it is judged whether or not the synchronizing signal (SH) itself exists and the judged result (J2) that it is judged whether or not the input signal exists in a follow-up range (TX), so that the signal can be synchronized easily in a short period even if the frequency of the synchronizing signal (SH) is deviated.

Abstract: A circuit arrangement for automatically recognizing the line number of a video sync signal in accordance with the 525 or 625 line standard, this circuit arrangement automatically generating a control signal corresponding to one of the relevant line numbers. To recognize the line number, a line counter (14) clocked with horizontal frequency pulses is provided, this line counter receiving the frame-frequency sync pulse signal as a reset signal. Moreover, a decoding stage (15) is arranged at the output of the line counter (14), which supplies a signal for changing the line standard hitherto used and a signal characterizing the corresponding line standard. In a subsequent signal evaluation circuit (16), these two signals are checked and a control signal either corresponding to the current line standard or to the new line standard is applied to the output (17).