Abstract: A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K.times.2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.

Abstract: A method for organizing and addressing memory of a digital video image is provided for one and two dimensional image processing using fast page mode accessing of memory, and also for displaying composite digital video images. A DRAM (12) is mapped to address locations storing segmented memory, non-segmented memory, line pointer tables, and horizontal description tables. The lines of a digital image are organized in DRAM (12) in either segmented memory or non-segmented memory. For segmented memory, each line of the image is broken up into equal line segments of pixels. Vertically aligned columns of line segments in the image are then stored in one or more rows of the DRAM (12). For non-segmented memory, each line is stored in a format where rows of DRAM (12) each represent a line of image data.

Abstract: An image coding and decoding apparatus which can produce an improved amount of the effective data per time unit especially in a case where the image data are processed in the field unit.

Abstract: A video imaging system having an image memory for storing a plurality of image frames and a video display having a matrix of pixels. Apparatus generates addresses for accessing pixels stored in the image memory to be displayed on the video display. The address generating apparatus includes a programmable mapping memory for storing a pixel descriptor of each pixel to be displayed on the video display, each pixel descriptor including a pixel group identification field which identifies a group of pixels on the video display, and an address field which includes address information of the image memory of pixels to be displayed. An address manager and a control causes each pixel descriptor read out of the mapping memory to be processed according to its pixel group to effect multiple format display of multiple format source video.

Abstract: An inverse transport processor system for a TDM packet signal TV receiver includes apparatus for selectively extracting desired payloads of program component data and coupling this data to a common buffer memory data input port. A microprocessor associated with the system also couples data to the common buffer memory data input port. The respective component payloads and data generated by the microprocessor are stored in respective blocks of the common buffer memory in response to associated memory address which are applied to a memory address input port by an address multiplexer. A decryption device is included to decrypt payload data according to packet specific decryption keys. In addition a detector is included to detect payloads including entitlement data. Payloads containing entitlement data are directed via the common buffer memory to a smart card which generates the packet specific decryption keys.

Abstract: A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j).

Abstract: The present invention concerns a processing method for a video signal coded in the form of blocks of K words, this signal being written to or read from two frame memories (FM1, FM2) each including an input port, a high speed output port and a low speed output port. According to this method, the input digital video signal is formed by sets of M' blocks with N' block containing luminance data (Y1, Y2 . . . ) and M'-N' blocks containing chrominance data (C1, C2 . . . ), the blocks containing the chrominance data (C1) are written in the first memory (FM1) and the blocks containing luminance data (Y1) are written in the second memory (FM2). Then the blocks containing the luminance data and the blocks containing the chrominance data are read simultaneously on the high speed output port of each memory, the memories being inverted at each frame, and the data eventually being processed to obtain video data in output that presents a compression ratio M/N with M>N.

Abstract: A video image processing system comprises an input cache store for temporarily storing input video data, compressors for compressing image data from the input store and an output store comprising multiple storage areas of known fixed size for storing respective files of compressed data from the compressors. The compressors are arranged to compress each image of the input video data to a given initial degree to produce respective data files. A processor compares the number of bytes in each data file with the known size of one storage area in the output store to determine whether the data file will occupy a predetermined proportion of said storage area. In the event that the data file will not occupy said predetermined portion of said storage area, the processor causes one of the compressors to effect one or more repeat compressions to a different degree in order to produce a data file of a size which will occupy said predetermined proportion of said storage.

Abstract: A memory address and display control apparatus for an high definition television comprising a memory address controller for controlling memory read/write addresses in response to a motion vector and a control signal, the memory address controller having a display read control circuit, a motion compensation read control circuit, and a raster format write control circuit, a memory unit having a previous frame memory for storing a video signal of a previous frame and a present frame memory for storing a video signal of a present frame, a multiplexing circuit for 2 to 1-multiplexing the output addresses from the memory address controller to alternately address the previous frame memory and the present frame memory in the memory unit, an input/output controller for controlling data input/output of the memory unit in response to frame and invert frame signals, a display controller for receiving video data from the memory unit under the control of the input/output controller and displaying the received video data, a

Abstract: A spiral buffer for a non-linear editing system digitizes and stores an input video signal as it is simultaneously being cataloged by an operator. The digitized video signal is stored in a circular buffer of a random access non-linear storage device, such as a disk recorder, with the oldest video being overwritten by the newest video when the buffer is full so long as the oldest video has not been marked by the cataloging process to be kept. The marked video is edited, further pruning the video in the buffer. The pruning of the video in the circular buffer results in a spiral shrinking of the buffer.

Abstract: A video motion compensation apparatus comprising an X-read address generation circuit for generating X-read address components in response to a macro block address and an X-motion vector component, a Y-read address generation circuit for generating a Y-read address component in response to a macro slice address and a Y-motion vector component, a write address generation circuit for generating X and Y-write address components in response to the macro slice address and the macro block address, a multiplexing circuit for multiplexing the Y-read address component, the X-read address components and the X and Y-write address components to generate read and write addresses of first and second frame memories, and a data processing circuit for reading video data from a location of one of the first and second frame memories corresponding to the read address from the multiplexing circuit, adding the read video data to inverse discrete cosine transform video data and writing the resultant video data into a location of th

Abstract: A high speed modular memory adapted for use in a decoding system of motion compensated prediction coded image data, comprises: 2.sup.N memory modules each comprising a two dimensional memory array with an address register for storing different pixels of a frame of the image data, wherein said N is a positive integer; a read/write signal generator for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a horizontal and a vertical addresses for each of the 2.sup.N memory modules in response to a motion vector separated into a horizontal motion vector and a vertical motion vector and the read/write control signal; a data bus for communicating the image data with the 2.sup.N memory modules; and an order changer which changes within the data bus positions of the data simultaneously read from the 2.sup.N memory modules within the data bus in response to the horizontal motion vector.

Abstract: An apparatus for parental control of television use by excluding or including selected programs, channels, and/or times. The apparatus includes a command controller comprising a microprocessor, a read only memory, a memory for authorized identification numbers, and a memory for storing the selected programs, channels, dates and times; a keyboard or similar apparatus for use in entering an identification code into the controller; a clock with an output as a function of time located in the television receiver; apparatus for ordering each program, date, and time into temporal order; and, apparatus for storing the selected program, date, and time in temporal order.

Abstract: If previously stored transmitters allocated to certain program settings in an entertainment electronics appliance are reallocated to the usual program settings, e.g., because of a changed transmitter distribution arrangement due to a change of location, time consuming reprogramming becomes necessary. The present invention concerns obtaining a simple sequencing process for reallocating previously stored channels to the desired program setting number. A microprocessor receives a command, and within a time window determined by the command, reads previously programmed data concerning two selected program settings from a main memory into a first auxiliary memory, and from this auxiliary memory into a second auxiliary memory, interchanging the channel numbers, and from the second auxiliary memory into the main memory again, so as to keep the same program numbers.

Abstract: In an image display method and apparatus for displaying image data, it is determined, based upon a control code contained in received image data, whether the image data is whole image data in one frame or partial image data in one frame. When it is determined that the image data is partial image data, the content of a memory being displayed is transferred to another memory, and the partial image data is stored in the memory which is the destination of the transfer. When the transfer of the data to the memory which is the destination of the transfer ends, the content of this memory is read and displayed.

Abstract: It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual part of the system and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.