Abstract: According to one embodiment, a magnetic disk device includes a disk including a plurality of servo data items, a head including a write head which writes data to the disk, and a first read head and a second read head which read data from the disk, and a controller configured to position the head based on a first signal in which write data positioned between the servo data items of the disk is read by the first read head, and a second signal in which the write data is read by the second read head separated from the first read head in a radial direction of the disk.

Abstract: A computer-implemented method for screening a multichannel head, according to one embodiment, includes measuring a channel signal to noise ratio value for each read transducer over a plurality of sense currents, wherein each transducer is one of a plurality of transducers in a multichannel head. The measured channel signal to noise ratio values are compared to a specification of a pre-defined value. The multichannel head is dispositioned to enable the multichannel head to perform to the specification of the pre-defined value, if possible.

Abstract: A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications.

Abstract: In a magnetic recording scale 41 fixed to an outer periphery of a rotary tube 20 which rotates around an optic axis depending on the movement of a zoom lens, a plurality of recording section 41a and recording section 41b pairs are provided in the rotational direction. A recording section 41b has a width less than a width of a recording section 41a . The recording section 41a is recorded with code information indicating a position in the magnetic recording scale 41, and the recording section 41b is recorded with a magnetic signal for detecting the recording section 41a adjacent thereto. A lens position detecting unit 71 detects a position of the zoom lens based on the code information and then detects a position of the zoom lens based on the detected code information.

Abstract: An apparatus for finding a syncmark in a data sector includes a syncmark detection circuit, decoder, fragment information table and syncmark recovery circuit. The syncmark detection circuit is operable to detect a syncmark in each of a number of fragments of the data sector and to compute a syncmark quality for each of the syncmarks. The decoder is operable to apply a data decoding algorithm to encoded data for the data sector. The encoded data has start points identified by the syncmark in each of the fragments. The fragment information table stores the syncmark quality for each of the syncmarks. The syncmark recovery sweeps the start points over search ranges for selected fragments for which the syncmark detection circuit failed to detect the syncmark and which have a lower syncmark quality than others of the fragments.

Abstract: A method for inhibiting cycle slip in a tape drive having at least three channels that each utilizes a corresponding numerically controlled oscillator includes establishing a reference clock that is based on an output of the numerically controlled oscillators for at least two of the channels, comparing the output of the numerically controlled oscillator for one of the three channels with the reference clock to determine a first channel phase delta value for the one channel, and generating an error signal for the one channel if the channel phase delta value exceeds a threshold phase delta value for the one channel.

Abstract: Misalignment of a transducer head over a bit-patterned media (BPM) may cause a bit to experience conflicting magnetization forces from the writer, resulting in improperly written data and stored data corruption. The likelihood of data corruption is reduced when a write transition is performed when the write sync margin is increased or maximized. Therefore, a write precompensation system may calculate time shift information for adjusting the timing of an individual write current transition at the transducer that compensates for write sync margin degradation due to any or all of skew angle of the transducer, track misregistration, and write field curvature.

Abstract: A servo system includes multiple interpolators operable to interpolate equalized data for multiple signal paths in a two dimensional magnetic recording system to yield interpolated signals at different phases, scaling circuits operable to scale the interpolated signals by adaptive scaling factors, a signal combining circuit operable to combine the scaled signals, a phase tracking circuit operable to select one of the phases of the combined signal, and an error gradient circuit operable to adapt the adaptive scaling factors.

Abstract: A read channel is configured to receive at least part of a data fragment read from a storage media into a register, wherein the data fragment is configured to be formatted with a preamble, a sync mark (e.g., a syncMark), and user data, and wherein the data fragment is missing a sync mark. A position in the data fragment is selected, a sync mark is assumed at the selected position. The data is then processed assuming the sync mark is at the selected position of the data fragment to determine whether the data converges. When a determination is made that the data converges, the data is recovered.

Abstract: A method includes designating a first sampling phase for a signal captured from a magnetic storage medium, where the signal is representative of information stored by the magnetic storage medium. The method further includes capturing a first waveform associated with the signal at the first sampling phase. The method also includes designating a second sampling phase different from the first sampling phase for the signal. The method further includes capturing a second waveform associated with the signal at the second sampling phase. The method also includes interleaving the first waveform and the second waveform to form an oversampled waveform. The first waveform and the second waveform are captured at a rate at least substantially equal to a rate at which the information stored by the magnetic storage medium was written to the magnetic storage medium.

Abstract: An initial phase offset between a center track and a side track is determined. An initial side track pulse shape is determined using the initial phase offset and side track interference. The initial side track pulse shape minimizes a contribution of the side track interference to a center track bit. The contribution of the side track interference is removed from the center track bit using the initial side track pulse shape and the side track interference.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises calibration circuitry configured to vary a phase of a clock signal as a test pattern is written to the storage disk as part of a calibration procedure, and disk locked clock circuitry coupled to the calibration circuitry and configured to obtain phase lock between the clock signal and a timing pattern on a surface of the storage disk. The calibration circuitry is further configured to determine an initial phase update value to be applied by the disk locked clock circuitry in a control loop as the phase of the clock signal is varied as part of the calibration procedure.

Abstract: A media includes a plurality of tracks, a preamble portion including a set of signals, a first servo burst having a first plurality of signals written substantially in phase with the preamble portion, and a second servo burst written out of phase with the preamble and the first servo portion. The media may be housed within a disk drive that includes a transducing head to read information from the media, and a read channel to read information from the disk including the information associated with the first servo burst and the second servo burst.

Abstract: A transceiver comprising a data processing module, a security processing module, a medium access control (MAC) module, a dirty-paper-coding (DPC) module, and a smart antenna processor. The data processing module provides user data streams to the MAC module and channel state information to the smart antenna processor. The security processing module generates security data and provides the security data to the MAC module. The security module also provides security policy data to the smart antenna processor. The MAC module determines data transmission rates for the user data streams and the security data. In addition, the MAC module allocates the data streams and security data to transmission channels for transmission. The DPC module encodes the security data onto the user data streams. The smart antenna processor generates pre-coding coefficients used by the DPC module and transmits the security encoded data streams.

Abstract: Methods and apparatus to for low power hard disk drive servo writers. A disclosed servo writer comprises a distribution circuit to receive one or more pulses from a pulse generator, the distribution circuit having a biasing circuit have one of a first write mode or a second write mode based on an operating condition signal; and a first signal generator to form a first write signal and a second signal generator to form a second write signal, the first and second signal generators being actuated by the distribution circuit, wherein the distribution circuit actuates one of the first and second signal generators in the first write mode and the distribution circuit actuates the first and second signal generators in the second write mode.

Abstract: The method of making a two-layer lap winding (12) for a multiphase electrical machine includes the steps of winding a first coil unit (20) of a first phase winding (14) around a winding bar (10); subsequently laying a coil connector (18) of the first phase winding (14) in a first direction and then winding at least one other coil unit (16) of at least one other phase winding (14) around the winding bar (10) and over the coil connector (18). Subsequently a second coil unit (22) of the first phase winding (14) is wound around the winding bar (10) following all first coil units of all phase windings and after all coil connectors from the first coil units are laid. A method of making a stator from the two-layer lap winding (12) is also described.

Abstract: A correction mechanism for use in a data storage system that allows data to be read even if the recorded data has been phase shifted.

Abstract: In recovering data originally written on a carrier of magnetic media after a catastrophic failure, data may be read without prior knowledge of the write channel by which the data was originally written and in the presence of intersymbol interference of the readback signal. This is accomplished by forming an image of the spatial response function of the magnetoresistive transducer used to recover the data and by forming an image of the raw data read from the carrier of magnetic media by the magnetoresistive transducer for which the response function has been characterized. An image of the distribution of virtual magnetic charge on the carrier of magnetic media is obtained through deconvolution of the image of the response function of the magnetoresistive transducer and the raw readback signal. The readback signal corresponding to the data originally written on the carrier of magnetic media is then recovered by spatial differentiation of the image of virtual magnetic charge.

Abstract: Sampling data with wide bi-phase code symbols includes sampling a wide bi-phase code symbol in the data a number (N) of times to produce samples of data, selecting a subset of the samples, determining which sample in the subset of samples has a largest magnitude, and selecting a subset of samples in a subsequent wide bi-phase code symbol based on a sample in a previous subset that has the largest magnitude.

Abstract: An information medium having digital signals recorded therein includes a disk having first and second recording surfaces. The digital signals are in the form of a data frame including a lead-in block and n data blocks. The lead-in block has a same format as the n data blocks. n block addresses are assigned to the n data blocks. Information identifying an area on the disk in which the n data blocks is recorded is assigned to the n data blocks. m data blocks (0<m<n) are recorded on the first recording surface, and remaining (n−m) data blocks are recorded on the second recording surface. The lead-in block is recorded at the head of the data frame, and includes information identifying an area on the disk in which the lead-in block is recorded, a number of recording surfaces, the block address of one of the m data blocks recorded last on the first recording surface, and the block address of a last one of the n data blocks in the data frame.

Abstract: A method of recording digital signals on a disk having at least a first recording surface and a second recording surface. The digital signals are in the form of a data frame including a lead-in block and n data blocks. The lead-in block has a same format as the n data blocks. The method includes the steps of assigning n block addresses to respective ones of the n data blocks, assigning, to each of the n data blocks, information identifying an area on the disk in which a respective one of the n data blocks is to be recorded, recording m data block (0<m<n) of the n data blocks on the first recording surface of the disk, recording remaining (n-m) data blocks of the n data blocks on the second recording surface of the disk, and recording the lead-in block at the head of the data frame.

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract: A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.

Abstract: An electrical socket includes at least one socket receptacle adapted to connect electrically an electrical appliance to a line power source, and a monitoring unit connected electrically across the socket receptacle for monitoring operating conditions, such as the ambient temperature, the line voltage, the line current and the line power supplied by the line power source, of the electrical socket.

Abstract: Methods and circuitry for generating sector and data cell timing frequencies for banded variable frequency sector disc drive systems with dedicated plus embedded servo positioning systems which have the timing signals synchronized to servo track information written on a dedicated surface of the disc.

Abstract: An improved Manchester code receiver is disclosed which samples the received signal and subtracts from that sample a previous sample of the received signal delayed by a half-bit time interval. A timing extractor selects sample timing from the central zero crossing of the received signal. The sample time is selected to be a quarter-bit time after the zero crossing time of the received signal.

Abstract: A circuit for producing a receive Manchester clock from serially received Manchester encoded data signals. The encoded data signals are differentiated to produce a primary clock pulse for each voltage transition of the applied signals. Each primary clock pulse is delayed a predetermined period of time to produce secondary clock pulse and each secondary clock pulse is delayed for substantially the same period of time to produce a tertiary clock pulse. The primary, secondary and tertiary clock pulses are applied to a gate which produces a receive Manchester clock pulse when a primary, secondary, or tertiary clock pulse is applied to the gate. The frequency of the receive Manchester clock is twice that of the basic frequency of the received Manchester encoded data signals.

Abstract: Digital data recorded in Manchester code in a 1553 MUX bus has the data portion of each word converted into NRZ-L format with the synchronization prefix or portion of each word converted into a corresponding NRZ-L formatted portion according to a predetermined protocol. The NRZ-L formatted word, prefix and data, is then converted into DM-M coded format. The Manchester code NRZ-L coded data is driven at a 1-MHz clock frequency, while the DM-M coded format is driven at a 500 kHz clock frequency. The data in DM-M code is then recorded on magnetic tape in a test recorder. The magnetic tape can be analyzed at a remote site after test by decoding the DM-M word into its corresponding NRZ-L word driven at the 1-MHz clock rate. The synchronization portion of the reconverted NRZ-L word is identified and the NRZ-L word correspondingly assembled into an output register according to a predetermined protocol.

Abstract: A clock pulse is derived from a received biphase modulated signal by feeding the biphase modulated signal and a signal indicative of the time points at which a code ONE of the received signal changes to a code ZERO and vice versa, to an exclusive OR circuit.

Abstract: A decoder is described for a self-clocking code, e.g. a bi-frequency Manchester code. Transitions are detected in the encoded data and are clocked into a shift register by a clock having a frequency equal to a multiple of the data bit rate. A logic network is connected to the shift register so as to detect combinations of transitions representing encoded data bits "0" and "1". The logic network includes OR gate funnels which detect the transitions in a range of possible positions in the shift register, so as to allow for jitter in the input data signal. The circuit allows encoded data to be correctly decoded in the presence of jitter without the necessity for using a phase-locked loop.

Abstract: A digital apparatus for data recovery system wherein data is recorded in FM or MFM code on magnetic media, comprises a measuring unit that in correspondence of a read pulse n as an input, supplies as an output, information related to the actual duration of interval N between pulse n and the previous read pulse n-1. A recovery unit for the magnetic media speed error relative to a nominal speed corrects the duration according to a code representative of the magnetic media speed error and a peak shift recovery unit which, according to the peak shift of pulse n-1, determined on the basis of the time history of the most recent pulses n-2, n-3, n-1 and the corrected duration, supplies as an output, nominal duration information related to this corrected duration and information representative of the direction and the amount of the peak shift of said read out pulse N-7.

Abstract: A decoding circuit is operative to decode a differential Manchester code consisting of four symbols "J", "K", "1" and "0" each composed of two consecutive signal elements. For detection of the symbol "J" and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol "K" immediately follows the symbol "J" and three consecutive signal elements, two of which are included in the symbol "J" and one of which is for a symbol immediately preceding the symbol "J", have the same polarity. To prevent an error that a second occurrence of the symbol "J" is detected after completion of detection of the symbol "J", the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol "J" until the symbol "0" or the symbol "1", for example, is detected.

Abstract: There is provided a method of modulating a data bit series consisting of a first value (e.g., 1) and a second value (e.g., 0) whereby a transition as a state transition is caused so as to satisfy the following conditions of (a) to (d).(a) The transition at the boundary portion of the bit cell which is sandwiched by bits 0.(b) The transition at the central portion of the bit cell of bit 1.(c) Among an even number of the bits of 1 which are sandwiched by bits 0, the transition is inhibited at the central portion of each bit cell of the last two bits of 1 and the transition is caused at the boundary portion of these two bit cells of 1.(d) When at least one bit in a pattern which starts from the two bits of (01) appears at a location next to an even number of the bits of 1 subsequent to bit of 0, the transition is caused at the central portion of the bit cell of bit 0 between these two bits.

Abstract: A short pulse of a small leading phase angle deviation of the carrier frequency at the start of a clock period and a short pulse of a small lagging phase angle deviation of the carrier frequency at the middle of a clock period encodes a digital one, while a short pulse of a lagging phase angle deviation of the carrier frequency at the middle of a clock period encodes a digital zero. Resistances are switched to directly deviate a low level carrier. The digital phase lock loop demodulator has an output digital one pulse derived from the negative pulse response of its phase comparator to the leading phase angle and has coherent clock pulses derived from its positive pulse response to the lagging phase angle at the middle of every bit. Information is contained in the abrupt pulses of phase transitions from an average constant phase carrier frequency. No reference carrier is needed for demodulation.

Abstract: A facility is provided for recovering the clock and data from a data stream transmitted in the bi-phase code even if the data stream contains no sync bits and if the transmission speed varies.For clock recovery, a nonretriggerable monostable multivibrator is triggered at each phase change, so that the inserted phase changes are rendered ineffective. The clock is used to control a memory which receives the valid data of the transmitted data stream at the correct instant and keeps this data constant during one clock period.

Abstract: A wide band constant duty cycle pulse train processing circuit where the pulse train frequency varies is proposed. The circuit serves primarily to obtain the basic clock in decoding signals encoded in the bi-phase mark code and includes a pulse-shaping or wave-shaping circuit, which receives the data signals and is followed by a low-pass filter; a differential amplifier circuit, one input of which is connected to the output of the low-pass filter and the other input of which is connected to a variable voltage source; and a current source, controlled by the differential amplifier circuit, at the input of the wave-shaping circuit determining the pulse length. The closed control loop between the output and the input of the wave-shaping circuit that determines the pulse length causes the duty cycle established at the variable voltage source to be maintained over wide ranges of the incident pulse train frequency.

Abstract: The data communication system includes an encoder to receive nonreturn-to-zero data signals and convert them to biphase signals, a current mode transmitter for transmitting the biphase signals, and a communication link connected to the transmitter. The encoder senses transitions in the nonreturn-to-zero data signals and controls the amplitude of the biphase signals in response to the sensed transitions. These transitions are sensed by inverting and delaying the nonreturn-to-zero data signals and exclusively ORing these delayed and inverted signals with the nonreturn-to-zero data signals.

Abstract: Apparatus for decoding a self-clocking, encoded signal wherein a series of data bits is encoded such that for each data bit, the encoded signal contains a first transition, and, for each data bit for which the succeeding data bit has the same binary value, the encoded signal contains a second transition occurring within a predetermined time interval after the first transition.

Abstract: A method and apparatus are disclosed for recovering data and clock information from high speed self-clocking data streams at rates of up to approximately 50 Mbps. The self-clocking data stream has a predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions. A pulse is generated for each voltage level transition in the coded stream. This pulse is applied to a non-retriggerable one-shot that produces an output pulse that is approximately the duration of one-half of a bit period. After the output pulse of the one-shot terminates, the one-shot is non-retriggerable for a period of time less than the duration of one-half of a bit period. The output pulse from the one-shot provides clock information derived from the coded bit stream. This clock information is provided to the clock input of a bistable storage device and the coded bit stream is applied to a data input to the storage device.

Abstract: A data communication system for transmission of bi-phase signals modulated by data symbols and in which the signals are filtered in accordance with a frequency response which approximates zero at 0 H.sub.z and at and exceeding the frequency 3/(2T) H.sub.z and which has an approximately sinusoidal variation between those frequencies, T being the symbol interval. This filter characteristic minimizes intersymbol interference and improves the signal-to-noise ratio. The requisite filtering may be provided in the receiver or in part in the receiver and in part in the transmitter of the communication system.

Abstract: A data signal is processed to change its form and spectral content without introducing undesirable frequency and amplitude effects. Multiple data signal states, which determine the essential characteristics of the output signal wave configuration, are utilized in conjunction with clock signals at a rate substantially in excess of twice the largest frequency component of the data signal in order to read from a memory a bit-duration waveform sample set representing the desired output signal wave configuration. Predistortion to compensate for anticipated transmission effects is also included in that configuration. In one embodiment, an input data signal is in an NRZ format and is processed for conversion to the biphase, or Manchester, format by a ROM table look-up function addressed jointly by the input signal states and the clock signals.

Abstract: A decoder for Manchester encoded data signals in which the encoded data signals are applied to a first circuit which produces a primary pulse at each voltage transition of the applied signals. The primary pulse enables a delay line oscillator which after a predetermined period of delay produces a decode clock signal of a given frequency. The inverted primary pulse, the decode clock signal, and a constant voltage data input signal are applied to a decoder shift register. The primary pulse and selected outputs of the decoder shift register are applied to a logic circuit which produces a receive clock signal having desired low-to-high voltage transitions occurring substantially in the center of each half-bit cell of a Manchester bit cell. The receive clock signal can be applied to a receive data shift register to which the encoded data signals are also applied so that the binary value of each half-bit cell of a Manchester bit cell can be stored in the data shift register.

Abstract: A circuit for generating a timing signal in a Manchester decoder comprises an oscillator 10, a frequency divider 14 for dividing signals derived from the oscillator, and a comparator 18 for comparing the times of transitions in the output signal of the divider with transitions in input Manchester data. To form a digital phase locked loop, gates 12 and 16 are provided for selectively adding a pulse to and subtracting a pulse from the pulses applied to the divider 14 by the oscillator 10 in dependence upon the relative timing determined by the comparator 18, in such manner as to lock the phase of the output signal of the divider onto the phase of the Manchester data. A squelch circuit is also provided for inhibiting phase control by the comparator 18 in response to a drop in signal strength of the received signal containing the Manchester data.

Abstract: The circuit comprises a differentiator, two nonretriggerable-gated-monoste-multivibrators, a clock decoder, a data flip-flop unit, and a multiphase and frequency logic circuit. The differentiator checks the incoming Manchester encoded signal and divides it into two trigger signals one with data associated with logic "0" transitions within the Manchester signal and the second trigger signal containing data associated with logic "1" transitions within the Manchester data. One trigger signal is fed to one of the nonretriggerable-gated-monostable-multivibrator and the other trigger signal is transmitted to the second similar unit. Within these monostable multivibrator units the signals are gated and delayed by a tapped delay line which outputs a plurality of delayed signals which have waveforms built upon the occurrence of transitions within the Manchester signal associated with the logic "0" and logic "1" occurrences.

Abstract: High information density retrieval method and system which employ the scanning of an optical disk, having a thermally-deformable record layer overlying a reflective support, with a read light beam. The optical disk tracks contain information in the form of variable-width, approximately 0.5.pi. phase-depth, pit regions interleaved between nominal thickness land regions. The pits have varying track lengths within a pit-length range constituting a disk fractional band-width of greater than 4.0 and read light reflected from the tracks is split-detected. The split-detected, electrical analog signal is peak-detected to reconstruct recorded digital data on the disk.

Abstract: In a method for decoding a received biphase-coded signal, a signal edge (2) is detected and its polarity determined in intervals of two periods (2T) for reconstructing the transmitted data. This allows the transmission rate of the signals to be increased up to the maximum frequency limit of the logic family used. By this means data sets (B1-BN), for example in biphase-level code, can be transmitted with start characters (A) optimized for minimum time loss. A decoder can be implemented with very simple monostable multivibrators and a small number of gates. Since sampling controlled by means of a digital counter is not required, the transmission rate can be increased by a factor of 8 to 32.

Abstract: The invention relates to the generation of a digital magnetic recording signal modulated in phase in correspondence with the transitions of the corresponding data signal. According to the invention, the D.C. component of the recording signal is suppressed so that the recording winding can be excited by this signal by means of a transformer. The recording head can include only a single turn.

Abstract: An apparatus and method for decoding input signals on four lines to produce an outgoing information stream of binary bits.

Abstract: A method and apparatus for encoding or decoding data in accordance with a coding format, referred to herein as Y.phi. and which is based on the 3PM coding format. Data encoded in accordance with the Y.phi. format is generated by initially encoding, at a prearranged clocking frequency, binary data in accordance with 3PM format, applying such encoded data to one input terminal of an exclusive OR gate and applying clocking pulses, at the prearranged frequency to the other input terminal. Decoding is similarly achieved by passing the encoded data through an exclusive OR gate. Data encoded according to the Y.phi. format is particularly advantageous on account of the relatively high density of flux transitions which it generates, which may be desirable in certain circumstances particularly if both high and low rate data is to be encoded on the same magnetic tape.

Abstract: There is provided a method of modulating a data bit series consisting of a first value (e.g. 1) and a second value (e.g., 0) whereby a transition as a state transition is caused so as to satisfy the following conditions of (a) to (d).(a) The transition at the boundary portion of the bit cell which is sandwiched by bits 0.(b) The transition at the central portion of the bit cell of bit 1.(c) Among an even number of the bits of 1 which are sandwiched by bits 0, the transition is inhibited at the central portion of each bit cell of the last two bits of 1 and the transition is caused at the boundary portion of these two bit cells of 1.(d) When at least one bit in a pattern which starts from the two bits of (01) appears at a location next to an even number of the bits of 1 subsequent to bit of 0, the transition is caused at the central portion of the bit cell of bit 0 between these two bits.