Abstract: The invention relates to a method and circuit arrangement for magnetic recording of a digital data signal composed of a set of transitions. A recording signal is formed by superposition on the data signal of a high frequency, constant amplitude, magnetic biasing signal S.sub.p. The biasing signal is phase-modulated relative to the data signal transitions. The invention remedies "peak shift" and can be applied to any rectangular or sinusoidal biasing signal.

Abstract: An apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuitry for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed here is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger bandwidth of optical fibers.

Abstract: A circuit for accurately reconstructing the timing information encoded within digital waveforms of the double frequency class includes facilities for restoring the circuit to proper synchronization at start up time or after a burst of noise on an incoming waveform. The circuit first generates three delayed versions of the incoming double frequency waveform. Transitions in the incoming waveform are detected by comparing the incoming waveform with the first delayed waveform and simultaneously comparing the second and third delayed waveforms, the generated transition-event waveforms being identical but out of phase by one half of the bit cell time of the incoming waveform. The two generated transition waveforms are used to form a composite clock which is then used to toggle the state of a D-type flip-flop at one half bit cell intervals.

Abstract: Data, in the form of a sequence of binary bits of frequency F.sub.O, is detected by deriving a clock signal H of frequency F.sub.O in response to the sequence. A level transposing device responsive to the sequence and signal H derives a bi-level signal DEI. An integrating apparatus responds to DEI to derive a signal DEINT. A decision circuit responsive to DEINT determines the polarity of signal DEINT and derives binary data bits having values that are a function of the polarity. The direction and duration of charging current supplied to a pair of capacitors of the integrator are controlled as a function of the polarity and duration of each of the levels of signal DEI, so the capacitors are respectively charged in response to even and odd numbered bits. The integrator is reset to zero at the end of the integrating operation for each level and the capacitive integrating member is supplied with a charging current proportional to F.sub.O.

Abstract: A bar code reader employs a microprocessor for decoding data contained in a bar code record and a logarithmic converter ahead of the microprocessor for providing to the microprocessor signals indicative of the logarithms of the widths of the scanned bars and spaces. The base of the logarithms used by the logarithmic converter is selected in a predetermined manner to maximize the resolution of the system for the particular microprocessor used, and to reduce the complexity of the system.

Abstract: The binary value of coded signals having opposite going transitions normally in the center of a bit cell, wherein the direction of the transition determines the binary value of the bit cell, is detected. The repetition rate of bit cells of a coded signal control the rate which a signal to be integrated is accumulated by an integrator. The integration duration is controlled by the length of the bit cell. The direction of integration is controlled by the direction of the center transition of each bit cell. In response to the amplitude of the accumulated signal at the end of the integration duration being greater or less than a reference amplitude, the binary value of the bit in the bit cell is determined. Integration is performed by first and second integrators respectively activated to accumulate the signal to be integrated during odd and even numbered bit cells. The first and second integrators are reset to zero during even and odd numbered bit cells, respectively.

Abstract: A decoding circuit including an adaptive synchronizing circuit for synchronizing to time-encoded data streams with an explicit output for eliminating non-data flux reversals in certain types of phase-encoded data such as Manchester-coded data. A preferred embodiment of the circuit includes a timer having first and second inputs and an output for producing a first state in response to a first signal at the first input, and also includes a means for producing a second state at the output of the timer in response to a predetermined condition at the second input. The circuit also includes additional circuit paths operatively coupling the output of the timer with the second input thereto whereby each of the first and second states are maintained at a relatively stable percentage of the time between successive first signals to the first input when the frequency of successive first signals varies. One of the first and second states of the timer provides a blanking pulse for eliminating the non-data flux reversals.

Abstract: A circuit is disclosed for use in magnetic card readers to compensate for variations in card speed as a card moves under a read head. The subject circuit decodes two frequency coherent phase encoding. This self clocking binary code incorporates the presence or absence of pulses (or transitions of voltage levels) within periodic intervals or bit cells as a representation of a logic 1 or a logic 0 respectively.

Abstract: A system wherein a magnetic tape is divided into a plurality of data storage blocks, each of which is preceded by a unique block marker. A phase encoder and phase decoder associated with the read/write head are connected by a data control circuit to a computer. As the head scans the block marker, the phase decoder supplies the computer with the block marker data via the data control circuit. Immediately after a predetermined block marker has been read, the computer provides the data control circuit with a write-signal and makes available a byte of parallel data to be written on the tape. The data control circuit includes an erase latch activated by the ongoing transition of the write-signal for providing the phase encoder with an erase-signal which causes the first byte on the magnetic tape following the block marker to be an erased gap.

Abstract: A demodulator for decoding the Manchester code is described in which the bit rate is maximized by using a one shot set up for a pulse width less than one-half the bit period. Control of the one-shot is established so that it is clocked at the bit rate but not at twice the bit rate, in order to receive high data rates serially over a single fiber optic channel.

Abstract: Circuit and method for converting FSK recorded data to NRZ by measuring time intervals between signals transitions of the same polarity.

Abstract: A read amplifier generates pulses in response to the transitions of a phase encoded signal and selectively gates the pulses to an output and to a retriggerable one shot multivibrator under the control of inhibit pulses produced by the multivibrator. During a preamble of the data signal in which a known sequence of zeros is produced, a decade counter prevents generation of pulses in response to the polarity return transitions between the zeros and prevents the inhibit pulses from being applied to gate the pulses produced by the data signal until a predetermined number of zero pulses has been counted. During the preamble the inhibit pulses at the output of the multivibrator are averaged and compared with a reference so as to adjust the duty cycle of the multivibrator to produce inhibit pulses which are 70 percent of the duration of the bit intervals of the data signal.

Abstract: A dual density read circuit for a digital magnetic tape transport selectively responds to information recorded on magnetic tape in either an 800 bpi NRZI format or a 1,600 bpi phase encoded format. The read circuit includes a differentiating circuit coupled to differentiate and square the read head signal, a latch circuit coupled to latch an NRZI output data signal only when the differentiated read head signal has a change of polarity after being at a given polarity for a predetermined minimum period of time, and first and second gating circuits coupled to selectively pass the NRZI output data signal and the differentiated read head signal when enabled by NRZI and phase encoded read signals respectively. The read circuit advantageously uses common circuit components while providing excellent noise immunity for either the NRZI or phase encoded data formats.

Abstract: In a tape drive capable of utilizing various types of magnetic tapes and encoding techniques, there is provided a system of optimally controlling read/write operations under various sets of conditions. Logic circuitry is provided to respond to tape detection means and to pre-selected conditions and/or requirements, and to select electronic circuits either singly or in combination which provide optimum read/write operation for the set of conditions then obtaining.