Data Verification Patents (Class 360/53)
  • Patent number: 11442813
    Abstract: A memory device includes a non-volatile memory to store data, an execution trace buffer, and a media controller. The media controller receives data-modifying commands and adds the data-modifying commands to the execution trace buffer. The media controller executes the data-modifying commands to modify the data stored in the non-volatile memory and detects errors in the data stored in the non-volatile memory. The media controller repeats execution of data-modifying commands from the execution trace buffer in response to detecting an error.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: September 13, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ronaldo Rod Ferreira, Taciano Perez
  • Patent number: 11430471
    Abstract: A disk drive is operable to determine degradation associated with writing to a disk surface by a head which has written existing data at a first areal density. A second areal density less than the first areal density is determined that remediates the degradation. The disk drive performs subsequent writes to the disk surface at the second areal density, and continues to read the existing data at the first areal density.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 30, 2022
    Assignee: Seagate Technology
    Inventors: Drew Allen Cheney, Edward Charles Gage, Praveen Viraraghavan
  • Patent number: 11422710
    Abstract: In a magnetic recording drive that includes a shingled magnetic recording (SMR) region and a conventional magnetic recording (CMR) region, the quantity of validation data that is stored by the CMR region is reduced. In the magnetic recording drive, verification data stored in the CMR region is invalidated under certain circumstances, including when an SMR band is closed, when an SMR band is indicated by a host to be reused, when an SMR band is indicated to be finished, and when a last data track of an SMR has data stored therein.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 23, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Richard M. Ehrlich, Eric R. Dunn, Fernando A. Zayas, Shoichi Aoki
  • Patent number: 11398290
    Abstract: A memory device including a data pad, and first and second data strobe pads, a data strobe signal generation circuit suitable for generating a read data strobe signal, outputting the read data strobe signal to the first data strobe pad, and generating an internal data strobe signal based on the read data strobe signal, during a test read operation, an input circuit suitable for feeding back and receiving data outputted to the data pad, during the test read operation, an alignment circuit suitable for aligning data received by the input circuit, based on the internal data strobe signal, and a test register circuit suitable for performing a preset operation on the data aligned by the alignment circuit and storing data obtained through the preset operation, wherein the test register circuit outputs the stored data to a read path during the test read operation.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Youngjun Park, Youngjun Ku
  • Patent number: 11288201
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 29, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Karin Inbar, Einat Lev, Roi Kirshenbaum, Ofer Sharon, Uri Peltz, Sergey Anatolievich Gorobets, Alan David Bennett, Thomas Hugh Shippey
  • Patent number: 11037598
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving, from a tape drive, a first error location on a magnetic tape where a first error occurred, in addition to determining one or more areas on the magnetic tape to be examined based on the first error location. Independent of a read and/or write operation, the tape drive is instructed to induce relative motion between a tape head and the magnetic tape such that the tape head is positioned adjacent to each of the respective one or more areas in turn. Moreover, each of the one or more areas having a respective number of measured servo errors which exceeds a threshold value is identified as a damaged area of the magnetic tape.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Noriko Yamamoto, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Sosuke Matsui, Shinsuke Mitsuma
  • Patent number: 11031041
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a processor to cause the processor to: determine, by the processor, a first error location on a magnetic tape where a first error occurred. One or more areas on the magnetic tape to be examined are also determined, by the processor, based on the first error location. Independent of a read and/or write operation, relative motion between a tape head and the magnetic tape is induced by the processor, such that the tape head is positioned adjacent to each of the one or more areas in turn. Moreover, each of the one or more areas having a respective number of measured servo errors which exceeds a threshold value are identified, by the processor, as a damaged area of the magnetic tape.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Noriko Yamamoto, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Sosuke Matsui, Shinsuke Mitsuma
  • Patent number: 10997995
    Abstract: The present disclosure generally relates to tape heads for use in a tape drive system. The tape head includes a plurality of servo elements and a plurality of data elements disposed between the servo elements. An electrostrictive material is present in the tape head. Electrodes are coupled to the electrostrictive material to permit a voltage to be distributed across the electrostrictive material. The voltage causes the electrostrictive material to expand, and thus expand the tape head. By expanding the tape head by adding voltage, or contracting the tape head by lowering voltage, the spacing between adjacent data elements can be adjusted to match the spacing between adjacent data tracks on a tape.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 4, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: David J. Seagle
  • Patent number: 10970170
    Abstract: A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan Scott Parry, Giuseppe Cariello
  • Patent number: 10971246
    Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10956246
    Abstract: In response to a first programmatic request, metadata indicating that a first isolated read channel associated with a data stream has been established is stored at a stream management service. A read request that indicates the first isolated read channel and the stream is obtained. In response to the read request, contents of data records of the stream are provided.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Sumeetkumar Bagde, Benjamin Warren Mercier, Sayantan Chakravorty, Rohit Unnikrishnan Nair, Yasemin Avcular, Charlie Paucard
  • Patent number: 10902873
    Abstract: An apparatus, according to one embodiment, includes a module having an array of transducers, and at least two expansion elements positioned proximate the array of transducers. The expansion elements are arranged side by side along a line extending parallel to a longitudinal axis of the array of transducers, wherein the array of transducers includes at least three servo readers. A controller is electrically coupled to the expansion elements, and is configured to individually control an extent of expansion of each expansion element based on feedback from the servo readers.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: David Seagle, Robert G. Biskeborn, Hugo E. Rothuizen
  • Patent number: 10819641
    Abstract: Techniques for maintaining high availability servers are disclosed. For example, a method comprises the following steps. One or more client requests are provided to a first server for execution therein. The one or more client requests are also provided to a second server for storage therein. In response to the first server failing, the second server is configured to execute at least one client request of the one or more client requests provided to the first server and the second server that is not properly executed by the first server.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juan Du, Arun K. Iyengar, Gong Su
  • Patent number: 10810086
    Abstract: A method includes emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board. Emulating the EAM-R system includes detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated with the secondary EAM-R board. The EAM-R system is emulated in an emulation system that includes at least one network connection. The emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 20, 2020
    Assignee: Honeywell International Inc.
    Inventor: Elliott Rachlin
  • Patent number: 10802085
    Abstract: A system determines the data stored on a piece of magnetic media by obtaining an image that represents the magnetic state of the piece of magnetic media using a magneto-optic image sensor. In an example, the image sensor is connected to a mechanism that moves over the piece of magnetic media, and the system takes a plurality of images which are stitched together into a composite image of the state of the piece of magnetic media. The system analyzes the image to identify regions that contain data, extracts the encoded data from the regions. The encoded data is decoded in accordance with an encoding scheme used by the piece of magnetic media. In some examples, a file structure is applied to the data and data files are recovered from the image. In various examples, the piece of magnetic media can be hard disk media, floppy disk media, or magnetic tape.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 13, 2020
    Assignee: Vulcan Inc.
    Inventors: Keith John Perez, Stephen Milton Jones
  • Patent number: 10769011
    Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shinya Takeda, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
  • Patent number: 10762924
    Abstract: The present disclosure generally relates to tape heads for use in a tape drive system. The tape head includes a plurality of servo elements and a plurality of data elements disposed between the servo elements. An electrostrictive material is present in the tape head. Electrodes are coupled to the electrostrictive material to permit a voltage to be distributed across the electrostrictive material. The voltage causes the electrostrictive material to expand, and thus expand the tape head. By expanding the tape head by adding voltage, or contracting the tape head by lowering voltage, the spacing between adjacent data elements can be adjusted to match the spacing between adjacent data tracks on a tape.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 1, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: David J. Seagle
  • Patent number: 10741200
    Abstract: A computer-implemented method may include obtaining position information of a susceptible zone of a tape. The susceptible zone may be a section of the tape where a stress value of the tape exceeds a threshold. The method may further include storing, based on the position information, a block of data to the tape in a first storage zone. The first storage zone may be positioned outside of the susceptible zone.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel James Winarski, Lee Curtis Randall
  • Patent number: 10725146
    Abstract: Radio-frequencies (RF) antennas for use in micro-localization systems are described. The RF antennas described herein may enable localization of objects with high resolutions, such as in the order of one centimeter or less. The RF antennas may be further configured to reduce range error variability across different directions, so that the accuracy of a micro-localization system is substantially the same regardless of the position of the object. An illustrative RF antenna includes an emitting element having first and second conductive traces patterned to reduce the angular impulse delay variability of the RF antenna. The first conductive trace may form a first arm of a spiral and the second conductive trace may form a second arm of the spiral. At least one parameter of the spiral may be selected to reduce the angular impulse delay variability of the RF antenna.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Humatics Corporation
    Inventors: Andrew Habib Zai, Gregory L. Charvat
  • Patent number: 10719392
    Abstract: Systems and methods are disclosed for error recovery in a digital data channel. In an error recovery approach when the hardware fails to recover a sector, the sample for that sector can be saved along with a metric measure that indicates the quality of the sample. This process can begin from a first on-the-fly receiving and decoding of data. During each step of error recovery, a retry attempt may either use samples obtained during a new decoding attempt or may use a sample, or a combination of samples, having the best metric from an earlier attempt, or a combination of earlier attempts, to perform the recovery during a current retry recovery attempt.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 21, 2020
    Assignee: Seagate Technology LLC
    Inventors: Deepak Sridhara, Ara Patapoutian
  • Patent number: 10714142
    Abstract: According to one embodiment, a disk device includes a disk, a head that performs data read/write processing on a recording region of the disk, a controller that performs a media scan processing for detecting the presence or absence of a defect in a sector in the recording region of the disk in track unit. When the controller performs the media scan processing on a first sector and a second sector arranged in the track, and a third sector arranged between the first sector and the second sector, the controller performs skip processing in which the controller scans the first sector and the second sector, and does not scan the third sector.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 14, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Makoto Segawa, Fuyuki Tawada, Osamu Yoshida
  • Patent number: 10649693
    Abstract: A hard disk device accepts logical block addresses (LBAs) from a host. The hard disk device includes a disk having a plurality of physical sectors from which data is read and to which data is written, and a processor configured to perform read and write operations on the disk in response to read and write commands from the host that designate LBAs. The processor, in response to a request for initialization, does not perform any write operations on the disk, and generates a new mapping of LBAs to the physical sectors for a current generation based on unusable sectors detected during a previous generation, and tracks differences in correspondence between LBAs and the physical sectors between the current generation and the previous generation.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: May 12, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kondo, Kana Furuhashi
  • Patent number: 10621023
    Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
  • Patent number: 10567006
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured, during execution of a relocation operation that includes storage of data to a memory buffer of an access device and retrieval of the data including data bits and first error correction code (ECC) parity bits from the memory buffer, to generate second ECC parity bits based on the data bits from the memory buffer and to compare the first ECC parity bits to the second ECC parity bits.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 18, 2020
    Assignee: Sandisk Technologies LLC
    Inventors: Judah Gamliel Hahn, Igor Genshaft, Marina Frid
  • Patent number: 10557000
    Abstract: A method for preparing an oblate polymer particle from a spherical polymer particle includes squeezing a polymer film including spherical polymer particles. A pair of polymer sheets are used to uniformly deform the film. With this method, more uniform oblate particles may be prepared, and a yield rate thereof may be improved.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 11, 2020
    Assignee: UNIVERSITY-INDUSTRY COLLABORATION & CONSULTING FOUNDATION
    Inventors: Seong Jae Lee, Sang Jae Ahn
  • Patent number: 10445171
    Abstract: Technologies are described herein for or enhancing error recovery procedures in a storage device by utilizing on-the-fly error type detection. After a read error has occurred, a number of read retries are performed through an adaptive read channel in the storage device. The current channel parameters of the adaptive read channel are then compared to a number of predetermined channel parameter sets, each associated with an error type, to determine the most probable type of error that occurred. Finally, an error recovery sequence is selected to recover from the read error based on the determined error type.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Seagate Technology LLC
    Inventors: Seung Youl Jeong, Min Gyeong Son, Eun Yeong Hong, Hyunjun Lee
  • Patent number: 10403312
    Abstract: The magnetic tape device includes a TMR head and a magnetic tape, in which the magnetic tape includes fatty acid ester in a magnetic layer, Ra measured regarding a surface of the magnetic layer is 2.0 nm or smaller, full widths at half maximum of spacing distribution measured by optical interferometry regarding a surface of the magnetic layer before and after performing a vacuum heating with respect to the magnetic tape are greater than 0 nm and 7.0 nm or smaller, a difference between spacings before and after the vacuum heating is greater than 0 nm and 8.0 nm or smaller, and a ratio of an average area Sdc of a magnetic cluster of the magnetic tape in a DC demagnetization state and an average area Sac of a magnetic cluster thereof in an AC demagnetization state measured with a magnetic force microscope is 0.80 to 1.30.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Eiki Ozawa, Norihito Kasada
  • Patent number: 10372351
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send control information to a host device. The control information is associated with first parity information. The controller further includes a circuit configured to determine second parity information associated with the control information. The controller is configured to terminate and optionally rollback an operation associated with the control information in response to the first parity information differing from the second parity information. The terminated optionally rolled-back operation associated with the control information may be a non-blocking control sync operation.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marina Frid, Igor Genshaft
  • Patent number: 10353669
    Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10304560
    Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10283149
    Abstract: A Data Storage Device (DSD) includes a magnetic storage medium and a head configured to read and write data using a current default write policy that affects an amount of power output by at least one write-assistive component of the head. One or more experimental writes are performed by writing data on the magnetic storage medium using an experimental write policy for the at least one write-assistive component, and the data is read from the magnetic storage medium. An experimental performance of the one or more experimental writes is evaluated based on the reading of the data. An experimental prediction value is determined indicating a predicted usable life of the head based on the evaluation of the experimental performance. Based on the experimental prediction value, it is determined whether to change the current default write policy for the at least one write-assistive component for future non-experimental writes.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 7, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bernd Lamberts, Classica Jain, Remmelt Pit
  • Patent number: 10277718
    Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jason Vincent Bellorado, Marcus Marrow
  • Patent number: 10242709
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting a first error while accessing a magnetic tape, determining a first error location on the magnetic tape where the first error occurred, determining one or more areas on the magnetic tape to be examined, independent of a read and/or write operation, inducing relative motion between a tape head and the magnetic tape such that the tape head is positioned adjacent to each of the respective one or more areas in turn, using the tape head to measure a number of servo errors that occur in each of the respective one or more areas, and identifying each of the one or more areas having a respective number of measured servo errors which exceeds a threshold value as a damaged area of the magnetic tape. The one or more areas are determined using a predetermined algorithm which incorporates the first error location.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Noriko Yamamoto, Tsuyoshi Miyamura, Hiroshi Itagaki, Tohru Hasegawa, Sosuke Matsui, Shinsuke Mitsuma
  • Patent number: 10199059
    Abstract: A computer-implemented method, according to one embodiment, includes: collecting performance data corresponding to a tape drive and/or a magnetic tape head, storing the performance data in memory, and using the data to perform problem analysis. The performance data includes a resistance of the tape drive and/or magnetic tape head and a resolution of the tape drive and/or the magnetic tape head. Moreover, performing the problem analysis includes: determining a condition of the tape drive and/or the magnetic tape head, wherein the condition is selected from a group consisting of: wear, corrosion, defective leads and wire bonds. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Said A. Ahmad, W. Stanley Czarnecki, Ernest S. Gale, Icko E. T. Iben, Josephine F. Kubista
  • Patent number: 10142408
    Abstract: A hardware loading adjusting method includes performing a first thread for receiving and decompressing the compressed data, to generate and to store decompressed data to a first storage module by a first speed; performing a second thread for storing the decompressed data to a second storage module by a second speed; and adjusting a ratio between the size of the compressed data and the decompressed data stored in the first storage module and the size of the first storage module according to the relationship between the first speed and the second speed.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 27, 2018
    Assignee: Winstron Corporation
    Inventor: Chong Zhang
  • Patent number: 10069591
    Abstract: Methods and apparatus for determining if a signal of interest, for example, a licensed signal having or exceeding a predetermined field strength, is present in a wireless spectrum and/or which facilitates such a determination are described. The signal of interest maybe, e.g., a television signal or a wireless microphone signal using licensed television spectrum. The predetermined field strength may be specified or by a government regulation or rule.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: September 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Stephen J. Shellhammer
  • Patent number: 10067825
    Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zig-zag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Im, Sang-Hyun Joo
  • Patent number: 10061640
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guangming Lu, Kent D. Anderson, Anantha Raman Krishnan, Shafa Dahandeh
  • Patent number: 10037271
    Abstract: A database system may include a memory device that includes a least a portion to serve as a buffer cache and an array of persistent storage devices configured to store data of a database. The database system may monitor a frequency of data value associated with a first portion of data of the database stored in the buffer cache. The database system may maintain the first portion of data in the buffer cache in response to the frequency of data value associated with the first portion of data being greater than a frequency of data value associated with at least a portion of the data of the database stored in the array of persistent storage devices.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: July 31, 2018
    Assignee: Teradata US, Inc.
    Inventor: Brian M. Andersen
  • Patent number: 10031863
    Abstract: A first component associated with an access controlled memory region receives a transaction request including a protocol header from a second component. The first component sends, to the second component, a negative acknowledgment in response to determining that the second component is not authorized to access the access controlled memory region, based on information in the protocol header.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: July 24, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Michael R. Krause
  • Patent number: 10008286
    Abstract: Systems and methods for self-testing archival memory devices are described. The memory device includes a data storage component capable of being coded with data. The memory device further includes a read-write mechanism configured to read, write, and delete data stored on the data storage component. The memory device includes a read-write controller configured to control the read-write mechanism based on input received through a device interface of the memory device, wherein the device interface of the memory device is configured to connect to an external computing device. The memory device further includes a diagnostic controller configured to perform a test on at least one of the data stored on the data storage component, the data storage component, and the read-write mechanism. The memory device includes a power source configured to provide operational power to the diagnostic controller when the memory device is not connected to an external power source.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: June 26, 2018
    Assignee: Elwha LLC
    Inventors: Jeffrey A. Bowers, Peter L. Hagelstein, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Patent number: 9952924
    Abstract: A memory device has a plurality of memory units, an error correction processor, and a memory controller. The memory units include semiconductor memories, and read and write in parallel. The error correction processor converts input content data into recording data which includes the content data and an error correction code. The error correction processor decodes the content data by performing conversion including error correction of recording data read out of the memory units. The memory controller writes recording data divided into a number of data into an area of areas extending over the memory units. The memory controller reads the divided recording data from the area. The memory controller determines that writing into the area has been completed normally if the number of the semiconductor memories of which abnormality has been detected is less than or equal to a number of abnormalities correctable by the error correction processor.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichiro Hanafusa
  • Patent number: 9946512
    Abstract: Systems and methods for sorting a data set stored on an external device. A plurality of smaller radix sizes are determined, based on a first radix size and performance characteristics of an external data storage device, whose sizes add up to a first radix size for an in-place radix sort. The smaller radix sizes reduce a total time to perform the in-place radix sort. Each level of a multiple level in-place radix sort is performed with the smaller radix sizes. Each level of the sort includes dividing the data set into N buckets; dividing the buffer into N buckets; and iteratively loading a respective segment in each bucket of the data set into a respective bucket of the buffer, performing an in-place radix sort on the data in the buffer, and returning sorted buffer data to the data set on the external storage device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Brian R. Konigsburg, Vincent Kulandaisamy, Ruchir Puri
  • Patent number: 9946591
    Abstract: An apparatus-implemented method according to one embodiment includes detecting an error while writing data to a tape volume, and repositioning the tape in response to detecting the error. Further, the method includes determining, after the repositioning, a current position of the tape, and determining, based on the current position, whether a rewrite of data associated with the error to the tape volume is allowed. A system according to one embodiment includes a processor and logic integrated with and/or executable by the processor. The logic is configured to cause the foregoing method to occur. A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to perform the foregoing method.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Erika M. Dawson, David C. Reed, Max D. Smith, Joseph M. Swingler
  • Patent number: 9934816
    Abstract: For avoiding debris accumulation on a tape drive, a processor records a position error signal (PES) value and cumulative head turnaround count for each region of a plurality of regions of a magnetic tape. The processor further selects a first region in which to reverse travel of the magnetic tape relative to a tape head. In response to determining one of the PES value for the first region does not exceed a PES threshold and the cumulative head turnaround count for the first region does not exceed a count threshold, the processor reverses travel of the magnetic tape at the first region. In response to determining the PES value for the first region exceeds the PES threshold and the cumulative head turnaround count for the first region exceeds the count threshold, the processor selects a second region at which to reverse travel of the magnetic tape.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Miyamura, Eiji Ogura, Tomoko Taketomi, Kazuhiro Tsuruta
  • Patent number: 9916310
    Abstract: A data storage system is provided that is configured to achieve end-to-end data protection. The system includes a server running a storage archive manager with a first fixity support module, and the system includes a tape drive running a second fixity support module. During operations, the storage archive manager reads a data file with associated fixity information from a disk storage device, and the storage archive manager builds a set of blocks from the data file for writing to the tape drive. The first fixity support module checks fixity of the set of blocks by processing the fixity information associated with the data file. The processing of the fixity information includes determining whether data in the set of blocks is out of order relative to data in the data file or whether data in the set of blocks is corrupt relative to the data in the data file.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 13, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: David G. Hostetter, David Allen Major
  • Patent number: 9904591
    Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: John B. Halbert, Kuljit S. Bains, Debaleena Das, Bill Nale
  • Patent number: 9886977
    Abstract: A recording medium having improved signal-to-noise ratio (SNR) capabilities includes dual cap layers over the recording layer, where the Curie temperature of the first cap layer over the recording layer is greater than the Curie temperature of the recording layer, and the Curie temperature of the second cap layer over the first cap layer is greater than the Curie temperature of the first cap layer. The first cap layer may be composed of a magnetically hard material, such as L10 CoPt, where the second cap layer may be composed of a magnetically soft material, such as Co. Such a medium is particularly useful in the context of heat-assisted magnetic recording (HAMR).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 6, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Oleg Mryasov, Alan Kalitsov, Hoan Ho, Paul Dorsey, Gerardo Bertero
  • Patent number: 9881643
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of tracks. A first codeword is generated comprising first redundancy, and first position information of the head relative to a first track is saved while writing the first codeword to the first track. A second codeword is generated comprising second redundancy, and second position information of the head relative to a second track is saved while writing the second codeword to the second track. Extended redundancy is generated for the first codeword based on the first and second position information, and the first codeword is recovered from the first track based on the extended redundancy generated for the first codeword.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Derrick E. Burton
  • Patent number: 9875037
    Abstract: Embodiments of the present invention provide systems, methods, and computer program products for implementing multiple raid level configurations in a computer storage device. In one embodiment, performance or resiliency of application data being executed to a single computer storage device can be prioritized. Embodiment of the present invention provide systems, methods, and computer program products for a recovery operation, responsive to determining to prioritize performance of application data being executed to the single computer storage device.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mudi M. Fluman, Yaacov Frank, Yehuda Shiran, Ronny Vatelmacher