Abstract: A magnetic disk device includes a magnetic disk on which servo information is recorded, a head to read the servo information of the magnetic disk, and a position control module. When carrying out positioning control of the head, the position control module estimates frequency components of noise in a head positioning control process, using a high-order digital filter that includes first and second variable coefficients that are each based on position error information generated from the servo information read by the head.

Abstract: A disk drive is disclosed comprising a head actuated over a disk. A test pattern is written to the disk and read from the disk to generate a read signal. The read signal is sampled to generate signal samples, the signal samples are filtered with an equalizer filter to generate a first output, and the test pattern is filtered with a target filter to generate a second output. An error signal is generated based on a difference between the first output and the second output. Coefficients of the target filter are adapted in response to the error signal, and after adapting the coefficients of the target filter, a sequence detector is configured based on the coefficients of the target filter.

Abstract: According to an aspect of the present disclosure, a system for correcting for DC characteristics of a magnetic recording system includes: circuitry implementing at least a portion of a write channel of the magnetic recording system; and circuitry configured to process output data of the write channel circuitry in accordance with a read channel of the magnetic recording system and repeatedly trigger re-writing through the write channel circuitry using different ones of a plurality of available data scramblings until a measured baseline wander exceeds a target threshold.

Abstract: A system including an analog front end module to receive a first signal generated by reading data from a storage medium storing the data in concentric tracks, sample the first signal, and output a second signal based on the sampling of the first signal. An equalizer module generates a first vector based on the second signal. The first vector represents the data in the first signal. A detector module generates a second vector based on the first vector. The second vector represents a noise-free vector corresponding to the first vector. A re-timing module re-samples a plurality of samples in the first vector based on the second vector and generates a third vector based on the re-sampling of the plurality of samples in the first vector. An inter-track interference cancellation module removes inter-track interference from the third vector.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output.

Abstract: In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

Abstract: The present application discloses a method to reduce hard-disk vibrations. The method to reduce hard-disk vibrations is for an electrical device having a hard-disk and a speaker, and the method to reduce hard-disk vibrations includes: determining a vibration value of the hard-disk when the speaker outputs an audio signal; determining whether the vibration value exceeds a predetermined vibration value; when the vibration value exceeds the predetermined vibration value, adjusting the audio signal into an adjusted audio signal via a reducing vibration equalizer; and outputting the adjusted audio signal by the speaker, wherein an amplitude of a predetermined frequency of the adjusted audio signal is smaller than an amplitude of the predetermined frequency of the audio signal.

Abstract: In one embodiment, a system includes a tape channel for reading data from a magnetic tape medium to produce a signal, a bank of noise whitening filters positioned subsequent to the tape channel adapted for receiving the signal, the bank of noise whitening filters being adapted for minimizing variance of noise affecting the signal at an output of the bank of noise whitening filters, wherein each noise whitening filter in the bank of noise whitening filters is dependent on a different possible data pattern, a soft DMAX detector adapted for calculating first soft information, dependent on the different possible data patterns, about each bit of the signal from the bank of noise whitening filters, and sending the first soft information to a soft decoder adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft DMAX detector.

Abstract: In one embodiment, a data storage system includes a tape channel for reading data from a tape to produce a signal, an adaptive noise whitening filter adapted for receiving the signal, the noise whitening filter being adapted for minimizing variance of noise affecting the signal output from the noise whitening filter, a soft DMAX detector adapted for receiving the signal from the noise whitening filter, the soft detector adapted for calculating first soft information about each bit of the signal and sending the first soft information to a soft decoder, and the soft decoder positioned subsequent to the soft detector, the soft decoder being adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft DMAX detector, wherein one or more noise whitening coefficients used in the noise whitening filter are updated using a noise whitening filter coefficient updater.

Abstract: In one embodiment, a data storage system includes a tape channel for reading data from a magnetic tape medium to produce a signal, a noise whitening filter positioned subsequent to the tape channel adapted for receiving the signal, wherein the noise whitening filter is adapted for minimizing variance of its output signal, a soft detector adapted for receiving output from the noise whitening filter, the soft detector adapted for calculating first soft information about each bit of the signal and sending the first soft information to a soft decoder, and the soft decoder positioned subsequent to the soft detector, the soft decoder being adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft detector. Other systems, methods, and computer program products are described according to more embodiments.

Abstract: The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: Described embodiments provide an interleaved sampler having N sample and hold circuits for sampling an input signal, and M multiplexers. Each multiplexer is adapted to couple all N of the plurality of sample and hold circuits to a respective output of the interleaved sampler. The interleaved sampler samples at a sample rate of fs, has an interleaved sampling period of M/fs, where M is greater than one and less than N. Because there are more sample and hold circuits than there are samples taken during an interleaved sampling period, different combinations of the sample and hold circuits are used from interleaved sample period to interleaved sample period. This reduces spurious tones generated from offset voltages when using interleaved sample and hold circuits. The order of the sample and hold circuits are clocked might be random, pseudorandom, or a fixed pattern longer than the interleaved sampling period.

Abstract: A system including a first filter module and a second filter module. The first filter module is configured to (i) pass a first DC shift in an input signal and (ii) convert a second DC shift in the input signal to a first component and a second component. The first DC shift is shorter in duration than the second DC shift. The second filter module is configured to detect one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift. In response to detecting one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift, the second filter module is configured to filter one or more of (i) the first DC shift and (ii) the first component and the second component of the second DC shift.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: According to one embodiment, there is provided a controller including an interference cancelling module, a boosting module, and a decoding module. The interference cancelling module generates a first correction signal by cancelling an interference component from an adjacent track in a signal read from a target track of a disk medium. The boosting module generates a second correction signal by boosting a low frequency component of a signal corresponding to the first correction signal. The decoding module decodes a signal based on the second correction signal.

Abstract: To encourage viewer participation, games, contests and social interactions are able to be synchronized with programming such as television shows or commercials utilizing a second screen such as a cell phone, iPad® or laptop computer. The programming is able to be television programming, Internet programming (e.g. a video displayed on a webpage or mobile device) or any other programming. The gaming is able to be any game such as a game of skill or chance, for example, a scavenger hunt or a treasure hunt.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: A storage controller includes a device controller and a read data channel. The read data channel includes a decoder for decoding output of a detector, where the detector is for reading data requested from a storage medium by the device controller, and the storage medium has a plurality of tracks of data thereon. When the device controller requests data from a current track of data on the storage device, the detector reads an adjacent track of data, the decoder decodes data from the adjacent track of data, the detector reads data from the current track, and the decoder decodes the data read from the current track, based on the decoded and stored data from the adjacent track of data. A storage system includes a storage medium having a plurality of tracks of data thereon and a storage controller as described above.

Abstract: According to an aspect of the present disclosure, a method includes: receiving a plurality of groups of one or more phase signals, each group of phase signals having a different phase relative to other groups of one or more phase signals; generating a plurality of interpolated phase shifted signals based on the plurality of groups of one or more phase signals, wherein the plurality of interpolated phase shifted signals do not have an associated common mode component; receiving data bits and precompensating each data bit in accordance with a given interpolated phase shifted signal; and selecting a precompensated data bit for output.

Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize a digital data signal; align the equalized digital data signal; determine a detector reliability metric based at least in part on the aligned equalized digital data signal; perform an iterative decoding process to determine a decoded digital data signal using the detector reliability metric; adjust the aligned equalized digital data signal using the decoded digital data signal; and repeat at least determining the detector reliability metric and performing the iterative decoding process using the adjusted equalized digital data signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: A method for detecting a data sequence includes generating a first sample stream, which is a time-sequenced digital signal associated with samples of an analog signal. The first sample stream is interpolated to generate a second sample stream with a different phase. The first sample stream is equalized to generate a first equalized sample stream. The second sample stream is equalized to generate a second equalized sample stream. The first and second equalized sample streams are processed to estimate the second equalized sample stream. The first equalized sample stream is filtered to generate a first set of noise sample streams. The estimated second equalized sample stream is filtered to generate a second set of noise sample streams. The first set and the second set of noise sample streams are diversity combined to generate a set of combined noise sample streams. A data sequence is detected using the combined noise sample streams.

Abstract: The present inventions are related to systems and methods for information data processing included selective decoder message determination.

Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients.

Abstract: A receiver for a hard disk drive system includes an analog front end module configured to receive a read-back signal and to output a digital read-back signal. An equalizer module is configured to generate a data vector based on the digital read-back signal. A detector module is configured to generate a decision vector based on the data vector. A gain module is configured to generate a scalar gain vector and to generate a revised data vector based on the data vector, the decision vector and the scalar gain vector. A back end module is configured to receive the revised data vector.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: Various approaches, methods, systems, circuits and devices for channel bit density estimation.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly, and more particularly to data processing relying on efficiency improved data detection.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

Abstract: A method for selecting which tap coefficients of a programmable finite-impulse-response (FIR) equalizer to fix is disclosed. In one embodiment, such a method includes performing an initial calibration to determine an initial value for each tap coefficient of a FIR equalizer. These initial values may be used to produce a first waveform. The method then performs an operation on the first waveform to produce a second waveform comprising multiple lobes. The second waveform is then analyzed to determine one or more lobes of the second waveform that have the largest area. The method then fixes coefficients of one or more taps that are closest to the lobe or lobes having the largest area. A corresponding apparatus and computer program product are also disclosed.

Abstract: A disk drive is disclosed comprising a head actuated over a disk, the head comprising a magnetoresistive (MR) read element. An analog read signal emanating from the MR read element is amplified to generate an amplified analog read signal. The amplified analog read signal is filtered in continuous-time to extract a dc component. An amplitude of the amplified analog read signal is measured in continuous-time, and an asymmetry in the amplified analog read signal is estimated in response to the dc component and the amplitude. The amplified analog read signal is modified in response to the estimated asymmetry to generate a compensated analog read signal.

Abstract: A method for selecting which tap coefficients of a programmable finite-impulse-response (FIR) equalizer to fix includes performing an initial calibration to determine an initial value for each tap coefficient of a FIR equalizer. Using these initial values, a “total” FIR equalizer is determined which sets the tap coefficients to their initial values. The method further determines multiple sets of tap coefficients that may potentially be fixed in the FIR equalizer. For each set of tap coefficients that may potentially be fixed, the method determines a “fixed” FIR equalizer that sets the tap coefficients in the set to their initial values and other tap coefficients to zero. The method then determines a phase-difference energy between the “total” FIR equalizer and the “fixed” FIR equalizer for each set of tap coefficients that may potentially be fixed. The set of tap coefficients associated with the lowest phase-difference energy are then fixed.

Abstract: A hard disk drive with a read channel that averages data before the data is provided to a viterbi detector of the channel. Averaging the data reduces the zero mean noise in the data.

Abstract: A receiver for a hard disk drive system includes an analog front end module configured to sample a read-back signal and to output a digital read-back signal. An equalizer module is configured to generate a data vector based on the digital read-back signal. A detector module is configured to generate a decision vector based on the data vector. A re-timing module is configured to generate a first revised data vector based on the data vector and the decision vector. The re-timing module re-samples a plurality of samples in the data vector in a non-sequential time order to generate the first revised data vector. An inter-track interference (ITI) cancellation module is configured to remove ITI from the first revised data vector and to generate a second revised data vector.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptively modifying a scaling factor in a data processing system.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response are described. A described system includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit operable to provide a coefficient adjustment to the asymmetry correction circuit to affect asymmetry compensation based on an estimate of nonlinearity derived from the equalized signal and multiple reconstructed ideal channel output values. The reconstructed ideal channel output values can be derived from an output of the discrete time sequence detector and correspond to at least two different discrete times.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an equalizer circuit, a signal to noise ratio calculation circuit, and a parameter adjustment circuit. The equalizer circuit is operable to equalize a data input to yield an equalized output. The signal to noise ratio calculation circuit is operable to calculate a signal to noise ratio of the equalized output based at least in part on a noise power derived from the equalized output. The parameter adjustment circuit is operable to adjust a parameter based at least in part on the signal to noise ratio.

Abstract: A system including a first circuit and a second circuit. The first circuit is configured to (i) select a first portion of a signal based on a first offset, (ii) amplify the first portion of the signal according to a first function, and (iii) scale the amplified first portion based on a first factor to generate a first compensation for asymmetry in the first portion of the signal. The second circuit is configured to (i) select a second portion of the signal based on a second offset, (ii) amplify the second portion according to a second function, and (iii) scale the amplified second portion based on a second factor to generate a second compensation for asymmetry in the second portion of the signal.

Abstract: Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit.

Abstract: Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value.

Abstract: A storage controller includes a device controller and a read data channel. The read data channel includes a decoder for decoding output of a detector, where the detector is for reading data requested from a storage medium by the device controller, and the storage medium has a plurality of tracks of data thereon. When the device controller requests data from a current track of data on the storage device, the detector reads an adjacent track of data, the decoder decodes data from the adjacent track of data, the detector reads data from the current track, and the decoder decodes the data read from the current track, based on the decoded and stored data from the adjacent track of data. A storage system includes a storage medium having a plurality of tracks of data thereon and a storage controller as described above.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output.

Abstract: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.