Abstract: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device.

Abstract: Devices, systems, and techniques for equalization and detection include, in at least some implementations, first circuitry configured to produce first equalized data responsive to input data by reducing a first characteristic of the input data wherein the first characteristic is noise, inter symbol interference (ISI) or both, a first detector that produces first output data responsive to the first equalized data, second circuitry configured to reduce a second characteristic different from the first characteristic to produce second equalized data, the second equalized data being generated based on the first equalized data, and a second detector that produces second output data responsive to the second equalized data.

Abstract: Described embodiments cancel inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A read channel reads one or more sectors in the desired track and generates one or more groups of sample values corresponding to each of the sectors. An ITI canceller estimates an ITI response and an ITI signal for each sample value corresponding to (i) a next adjacent track and (ii) a previous adjacent track. If the estimated ITI response of the previous adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the previous adjacent track from each associated sample value of the desired track. If the estimated ITI response of the next adjacent track reaches a predetermined threshold, the ITI canceller subtracts the estimated ITI signal corresponding to the next adjacent track from each associated sample value of the desired track.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data.

Abstract: Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: A device is provided that, in one implementation, includes interpolators to generate interpolated phase shifted signals, and a precompensation circuit to provide precompensated versions of data bits in accordance with the interpolated phase shifted signals. Each of the interpolators is assigned a bit pattern different from that assigned to remaining ones of the interpolators.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response include an integrated circuit device including: an input to receive digital data corresponding to an asymmetry corrected analog signal of a read channel; an input to receive sequence data detected in the digital data; circuitry to generate a coefficient adjustment based on an estimate of non-linearity for the read channel, the estimate derived from the digital data and the sequence data; and an output to provide the coefficient adjustment to affect asymmetry correction of the analog signal.

Abstract: Embodiments include a decision feedback equalizer (DFE) that includes a first comparator configured to receive as inputs a soft value and a first threshold, a second comparator configured to receive as inputs the soft value and a second threshold, a selector configured to select an output of either the first comparator or the second comparator as a DFE output based on one or more previous bits output by the selector; an error calculator configured to determine an error for the first comparator and the second comparator, and a threshold adjuster configured to adjust the first threshold and the second threshold, the first threshold and the second threshold each being a non-linear combination of one or more previous outputs of the selector.

Abstract: A storage controller includes a device controller and a read data channel. The read data channel includes a decoder for decoding output of a detector, where the detector is for reading data requested from a storage medium by the device controller, and the storage medium has a plurality of tracks of data thereon. When the device controller requests data from a current track of data on the storage device, the detector reads an adjacent track of data, the decoder decodes data from the adjacent track of data, the detector reads data from the current track, and the decoder decodes the data read from the current track, based on the decoded and stored data from the adjacent track of data. A storage system includes a storage medium having a plurality of tracks of data thereon and a storage controller as described above.

Abstract: Systems and methods for detecting and designing enhanced disk sync marks using correlation detection are disclosed. The enhanced sync marks provide better noise immunity and higher detection rates over traditional Viterbi-based detection schemes even with a shorter sync mark length. The disk sync mark may provide optimal noise immunity for a particular target polynomial or a plurality of common target polynomials. The minimum Euclidean distance between a candidate sync mark and a plurality of right-shifted versions of the candidate sync mark is computed and compared with other candidate sync marks. The sync mark with the largest minimum Euclidean distance is then selected as the optimal mark. Systems and methods are also disclosed for detecting and designing a disk sync mark using correlation detection when the polarity of the disk is unknown or time-varying.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

Abstract: Systems and techniques relating to interpreting signals on a noisy channel. A direct current (DC) correction can be applied to an input of a post processor outside of a main read path that supplies data detector output to the post processor. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, has a main read path including a signal equalizer and a data detector. A post processor is responsive to the output of the data detector, and a DC control unit applies a DC correction to an input of the post processor outside of the main read path.

Abstract: An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.

Abstract: Devices, systems, and techniques for equalization include, in at least some implementations, a first equalizer that produces first equalized data responsive to input data by reducing a total power of both noise and inter symbol interference components of the input data, a first detector that produces first output data responsive to the first equalized data, a second equalizer that produces second equalized data responsive to the first output data by maximizing bit error rate performance, and a second detector that produces second output data responsive to the second equalized data.

Abstract: A circuit for compensating asymmetry in a waveform of an input signal using a piecewise approximation of a saturation curve, the circuit including a first circuit configured to output a first compensation for a first section of the saturation curve using a first function and a second circuit configured to output a second compensation for a second section of the saturation curve using a second function. The second function is different than the first function. The first compensation and the second compensation provide the piecewise approximation of a region of the saturation curve. The region includes at least the first second and the second section.

Abstract: Various embodiments of the present invention provide systems and methods for data equalization. For example, various embodiments of the present invention provide methods for generating equalization data. The method includes inputting N bits of an equalization data pattern into respective stages of a shift register, wherein inputting the N bits occurs synchronous to a system data clock having a system data rate, and shifting the N bits of equalization data to next adjacent next stages of the shift register synchronous to an equalization data clock having an equalization data rate N times the system data rate.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: To effectively suppress a signal in a low frequency region in which the medium noise and the signal distortion are concentrated, and in order to effectively utilize a detected component of the reproduced signal in the low frequency region, a target of partial response equalization to the perpendicularly recorded/reproduced signal is set so that the low-frequency component around the direct current is suppressed to a regulated quantity for both the effective suppression and the effective utilization. Accordingly, a maximum-likelihood decoding process is carried out through the target of partial response equalization. Reliability of data detection is made higher and a signal-to-noise ratio is improved, so that the noise from the recording medium can be reduced more and it is possible to provide a high-density magnetic recording/reproducing apparatus.

Abstract: Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: Systems and techniques associated with signal processing are described. A described technique includes generating asymmetry vectors that model asymmetry in a received analog signal, including an effect of asymmetry spreading in a read channel and selecting at least two different indicators of asymmetry based on the asymmetry vectors. The technique can include using the selected indicators of asymmetry to compensate for one or more asymmetries associated with the analog signal.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: A magnetic media tester comprising a Laser Doppler Vibrometer (LDV) head; and a magnetic read head; the LDV head and the magnetic read head being configured for obtaining correlatable data of a region on a magnetic disk.

Abstract: In a perpendicular magnetic recording system, the data that is being written by the write channel is fed back into the read channel. The read channel processes the data and decides if the written sequence is likely to have very poor DC characteristics. If that is the case, the write channel changes a scrambler seed and rewrites the data using the new scrambler seed. The data may also be inspected for patterns that might cause large baseline wander before being written to disk, i.e., in the write channel. A data sequence may be repeatedly scrambled and encoded until an acceptable level of estimated DC-wander has been achieved. The data sequence may then be written to disk.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response include an integrated circuit device including: an input to receive digital data corresponding to an asymmetry corrected analog signal of a read channel; an input to receive sequence data from a discrete time sequence detector, the sequence data generated by the discrete time sequence detector based on the digital data; an output to provide a coefficient adjustment to affect asymmetry correction of the analog signal; and circuitry to generate the coefficient adjustment based on an estimate of non-linearity for the read channel, the estimate derived from the digital data and the sequence data.

Abstract: Disclosed is a magnetic recording/reproduction device 2 including: a recording/reproduction head 7; and a recording/reproduction head 7 for detecting a leakage magnetic field of each of the plurality of magnetic recording cells 1 so as to reproduce information, the recording/reproduction head 7 carrying out the recording on the magnetic recording medium 4 so that the magnetic recording medium 4 includes continuous recording regions that (i) satisfy Nmin?2 and that (ii) include a continuous recording region that satisfies N?n×Nmin, where N represents a number of magnetic recording cells 1 in a continuous recording region; Nmin represents a minimum value for N; and n represents a positive integer, the continuous recording regions each being a region on a reproduction track in which region magnetic recording cells 1 sharing an identical magnetization direction are sequentially arranged in a circumferential direction of the magnetic recording medium 4.

Abstract: A read-channel module including a VGA module to amplify a signal based on a variable gain, an ADC module to generate a sample based on the amplified signal, and an AGC module to control the variable gain of the VGA module. A gain adjusting module generates (i) a first gain and (ii) a second gain when an amplitude of the sample is (i) less than or equal to a first predetermined threshold and (ii) greater than or equal to a second predetermined threshold, respectively. The AGC module (i) increases and (ii) decreases the variable gain of the VGA module based on (i) the first gain and (ii) the second gain, respectively. The gain adjusting module generates the first gain and the second gain by (i) multiplying a present gain of the AGC module by a predetermined multiplier or (ii) adding a predetermined offset to the present gain.

Abstract: Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

Abstract: Systems and techniques to configure a read channel include, in at least one implementation, an apparatus including: detection circuitry configured to process an input signal from a machine-readable medium to calculate metrics; monitoring circuitry configured to determine a polarity of the input signal based on the metrics and at least one of multiple framings of signal samples of the input signal; and selection circuitry to configure a read channel for the machine-readable medium based on the determined polarity.

Abstract: A disk drive is disclosed comprising a head actuated over a disk having a plurality of tracks. A pattern is read from the disk to generate a read signal, and the read signal is sampled to generate read samples. Predictable disturbing samples are generated as a function of the pattern. The predictable disturbing samples are added to the read samples to generate disturbed samples, and a data sequence is detected from the disturbed samples.

Abstract: A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Abstract: Provided is a method for receiving a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. A coefficient cyclic equalizer vector is generated as a function of the DSS sequence and the DSS readback sequence. An error signal is generated as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.

Abstract: A reproducing apparatus for reproducing channel data from a recording medium using the ITR includes a reading unit reading an information signal recorded on the recording medium; a phase interpolator interpolating a phase of the information signal read on the basis of a phase error signal sent as a feedback; a first waveform equalizer equalizing a waveform of the phase-interpolated information signal while keeping the phase of the information signal fixed; a phase-error-signal generator generating the phase error signal to be sent as a feedback to the phase interpolator on the basis of the information signal whose waveform has been equalized by the first waveform equalizer; a second waveform equalizer equalizing the waveform of the phase-interpolated information signal without limiting a phase change; and a decoder generating the channel data by decoding the information signal whose waveform has been equalized by the second waveform equalizer.

Abstract: A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: Systems, methods and devices for equalization include a first adaptive equalizer to process read data or write data to respectively produce equalized read data or write data; a first detector to detect the equalized read data or the equalized write data to respectively produce detected read data or detected write data; a first comparator to determine an adjustment input based on a comparison of the equalized read data to the detected read data, or the equalized write data to the detected write data; and a second adaptive equalizer to process refined equalized read data or refined equalized write data to respectively produce twice equalized read data or twice equalized write data. The refined equalized read data or the refined equalized write data is respectively produced based on (i) the equalized read data and the adjustment input or (ii) the equalized write data and the adjustment input.

Abstract: Various embodiments of the present invention provide systems and methods for performing data equalization. For example, various embodiments of the present invention provide data equalization circuits that include an equalization circuit and a transition adjustment circuit. The equalization circuit receives a series of at least two original data bits and replaces at least one of the two original data bits with an equalization pattern including two or more equalization bits. The original data bits correspond to an original data clock, and the two or more equalization bits correspond to an equalization data clock. The transition adjustment circuit is operable to modify an occurrence of a transition from one logic state to another logic state within the equalization pattern on a sub-equalization data clock basis.

Abstract: A disk drive is disclosed comprising a disk and a head actuated radially over the disk, wherein the head generates a read signal. A sampling device samples the read signal to generate a sequence of read signal samples, and an equalizer comprising a plurality of coefficients, equalizes the read signal samples to generate a sequence of equalized samples. A sequence detector detects an estimated data sequence from the equalized samples, wherein the sequence detector operates according to a target response comprising a plurality of target values. Control circuitry adapts the equalizer coefficients by computing error values in response to a difference between expected samples and the equalized samples, computing a gradient in response to a correlation of the read signal samples with the error values, and adjusting at least one of the equalizer coefficients in response to the gradient.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: A signal conversion circuit includes: an input circuit that rejects common mode inputs and is configured to receive a differential input signal and shift a first bias of the differential input signal to produce a single ended intermediate signal with a second bias; and an amplifier circuit configured to amplify the single ended intermediate signal to produce an amplified signal. The input circuit can include: first and second transistors with drains configured to couple with a supply voltage, and gates of the first transistor and the second transistor are configured to receive the differential input signal; a first resistor coupled to a source of the first transistor and a drain of a third transistor; and a second resistor coupled to a source of the second transistor and a drain of a fourth transistor; where the third transistor and the fourth transistor are connected in a current mirror configuration.

Abstract: Various embodiments of the present invention provide systems and methods for reducing head distortion. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly, and an adaptive distortion modification circuit. The storage medium includes information that may be sensed by the read/write head assembly that is disposed in relation to the storage medium. The adaptive distortion modification circuit receives the information sensed by the read/write head assembly and adaptively estimates and implements a distortion compensation factor in the analog domain. In some instances of the aforementioned embodiments, the read/write head assembly includes a magneto resistive head. In such instances, the distortion compensation factor is designed to compensate for non-linear distortion introduced by the magneto resistive head.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide methods for modifying magnetic information transfer. The methods include retrieving magnetically represented data from a storage medium, and converting the magnetically represented data to a series of data samples. A preceding pattern and a transition status is identified in the series of data samples, and an equalized channel response is computed based on an estimated NLTS value. An error value is computed that corresponds to a difference between the estimated NLTS value and an actual NLTS value, and a pre-compensation value is computed based at least in part on the error value.

Abstract: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

Abstract: A disk drive is disclosed comprising a disk and a head actuated radially over the disk, wherein the head generates a read signal. A sampling device samples the read signal to generate a sequence of read signal samples when reading a training data sequence recorded on the disk, and an equalizer comprising a plurality of coefficients equalizes the read signal samples to generate a sequence of equalized samples. A sequence detector detects an estimated data sequence from the equalized samples, wherein the sequence detector operates according to a target response comprising a plurality of target values. Control circuitry adapts the target values by computing error values in response to a difference between expected samples and the equalized samples, computing a gradient in response to a correlation of the training data sequence with the error values, and adjusting at least one of the target values in response to the gradient.