Abstract: A magnetic head according to one embodiment includes a reader and a thermal sensor for detecting a thermal effect thereon from a magnetic medium passing by the thermal sensor. A tape drive system according to one embodiment includes a magnetic head for reading data from a magnetic tape, a thermal sensor for detecting a thermal effect thereon from the magnetic tape passing by the thermal sensor, a drive mechanism for passing the tape over the head, and a processor for causing alteration of a readback signal from the magnetic head based on an output of the thermal sensor.

Abstract: A read channel includes a variable gain amplifier, a low-pass filter, an AGC, an analog-to-digital converter, a frequency synthesizer, a filter, a soft-output detector, an LDPC decoding unit, a synchronizing signal detector, a run-length limited decoding unit, a descrambler, and a first baseline wander corrector. The first baseline wander corrector corrects a baseline variation by a feedforward control.

Abstract: A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector. The estimate can be a least mean squared estimate of the non-linearity in the equalized signal.

Abstract: Systems and methods for detecting a disk sync mark are provided. The systems and methods for detecting the disk sync mark rely on a detecting the disk sync mark on at least one timing interval. A window of data read bits from a particular disk sector are examined to determine whether they match the disk sync mark. The disk sync mark may be differentiated from expected versions of the disk sync mark using a calculated set of thresholds.

Abstract: A phase interpolator is provided that, in one implementation, includes an output node, a plurality of phase input circuits, and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit is operable to receive a given phase signal. Each switch is in communication with a given phase input circuit and is operable to couple a given phase signal to the output node.

Abstract: A write driver circuit includes a first write driver that communicates with a first node of a write head. A first feedback path communicates with a control input and an output of the first write driver. The first feedback path includes a first resistance connected between the output of the first write driver and the control input of the first write driver. A second write driver communicates with a second node of the write head. A second feedback path communicates with a control input and an output of the second write driver. The second feedback path includes a second resistance connected between the output of the second write driver and the control input of the second write driver.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: Embodiments in accordance with the present invention provide a magnetic disk drive capable of achieving error recovery stably in a simple configuration in the event of thermal asperity (TA) and minimizing the error recovery time required, and a method for controlling the disk drive. According to one embodiment, if TA occurs, a cutoff frequency of a high-pass filter to which a data read signal is input is first increased and a loop gain of a low-order finite impulse response (FIR) filter connected in series to an FIR filter is also increased as high as possible. Next, a Viterbi decoder to which a signal is input from the low-order FIR filter provides feedback to the low-order FIR filter so that an input signal error becomes a minimum. Tap coefficients of the low-order FIR filter are thus optimized.

Abstract: Removing magneto-resistive asymmetry (MRA) from a signal is disclosed. Removing MRA includes determining an estimated offset error associated with error due to offset in the signal, determining an estimated signal error associated with error due to offset and MRA in the signal, and removing at least a portion of MRA from the signal based at least in part on the estimated offset error and the estimated signal error.

Abstract: A magnetic recording and reproducing device is a hard disk device which writes information onto a magnetic disk (not shown), or reads information therefrom, and includes: a reproducing head; a recording head; and a magnetic head driving circuit. The magnetic head driving circuit is a circuit, by which driving of the reproducing head and the recording head is controlled, and onto which the reproducing head, a recording head driving circuit, a control unit, and a variable impedance element are integrated. This magnetic head driving circuit is switched on a time division base to a read mode during reproducing operation, and to a write mode during recording operation. The control unit reduces the impedance of the variable impedance element during the write mode.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

Abstract: Provided are a read channel, storage drive and method using a measured error to determine coefficients to provide to an equalizer to use to equalize an input signal. A read channel is incorporated in a storage device to process signals read from a storage medium. An equalizer uses coefficients to equalize input read signals to produce equalizer output signals. A detector processes adjusted equalizer output signals to determine output values comprising data represented by the input read signals. An equalizer adaptor is enabled to provide a reference measured error and coefficients used to produce the adjusted equalizer signals that are associated with the reference measured error. The equalizer adaptor computes new equalizer coefficients to use to equalize input read signals that result in a new measured error from the detector and computes a new measured error for the new equalizer coefficients.

Abstract: A storage channel, e.g., for a disk drive system, may asynchronously sample and buffer an entire sector, and then process the buffered sector to recover timing information. The storage channel may operate in an open-loop and utilize an exhaustive search to determine timing parameters. Alternatively, the storage channel may operative in a closed-loop, processing the sector once, and feeding back information obtained during decoding to the timing loop.

Abstract: A read-channel module includes a variable-gain amplifier (VGA) module, an analog-to-digital converter (ADC) module, an amplitude measuring module, a gain adjusting module, and a zero phase start (ZPS) module. The VGA module has a variable gain, amplifies input signals, and generates amplified signals. The ADC module converts the amplified signals from analog to digital format and generates samples. The amplitude measuring module receives N of the samples and measures amplitudes of the N samples, where N is an integer greater than 1. The gain adjusting module communicates with the amplitude measuring module and selectively adjusts the variable gain of the VGA module based on the amplitudes. The zero phase start (ZPS) module communicates with the amplitude measuring module, receives the samples, and selectively generates phase information from the samples based on the amplitudes.

Abstract: To effectively suppress a signal in a low frequency region in which the medium noise and the signal distortion are concentrated, and in order to effectively utilize a detected component of the reproduced signal in the low frequency region, a target of partial response equalization to the perpendicularly recorded/reproduced signal is set so that the low-frequency component around the direct current is suppressed to a regulated quantity for both the effective suppression and the effective utilization. Accordingly, a maximum-likelihood decoding process is carried out through the target of partial response equalization. Reliability of data detection is made higher and a signal-to-noise ratio is improved, so that the noise from the recording medium can be reduced more and it is possible to provide a high-density magnetic recording/reproducing apparatus.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response can include generating multiple asymmetry matrices that model asymmetry in a received analog signal, including an effect of asymmetry spreading in a read channel; comparing the multiple asymmetry matrices; and selecting indicators of asymmetry from the matrices based on the comparing. Systems and techniques can include saving in memory an indication of the selected indicators of asymmetry.

Abstract: A signal processing circuit performs processing for an analog signal output from a head. The signal processing circuit includes: a conversion section that generates a digital signal based on the analog signal; a first filter that equalizes the output of the conversion section; a demodulation section that demodulates data from the output of the first filter; a modulation section that modulates a waveform based on the data demodulated by the demodulation section; a second filter that equalizes the output of the modulation section; and an adaptation section that adapts the response of the second filter such that the output of the second filter becomes equal to the output of the conversion section.

Abstract: An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the writing circuit (334) for sequentially receiving the main data and the parity data, and outputting to the storage apparatus via a write pre-compensation unit (305), a driver (306), and the like.

Abstract: A storage channel, e.g., for a disk drive system, may asynchronously sample and buffer an entire sector, and then process the buffered sector to recover timing information. The storage channel may operate in an open-loop and utilize an exhaustive search to determine timing parameters. Alternatively, the storage channel may operative in a closed-loop, processing the sector once, and feeding back information obtained during decoding to the timing loop.

Abstract: A phase-acquisition (PA) loop for a read channel comprises an accumulator, a comparator, and a filter. The accumulator holds an acquired phase-correction value corresponding to a difference between a phase of a sample clock and a phase of data carried by a read signal, and provides the acquired phase-correction value to a circuit that modifies the read signal to compensate for the phase difference. The comparator receives a reference phase-correction value that also corresponds to the difference between the phases of the sample clock and the data, and generates an error signal that is related to a difference between the reference and acquired phase-correction values. And the filter causes the acquired phase-correction value to have a predetermined relationship to the reference phase-correction value.

Abstract: A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: According to one embodiment, a signal reproducing circuit reproduces a signal read from a recording medium on which the signal has been recorded by perpendicular magnetic recording. The signal reproducing circuit includes a waveform equalizer that equalizes the waveform of the signal based on a waveform equalization target, where D is a one-bit delay operator, previously stored in a storage module. The waveform equalization target is any one of a[1+3D+2D2] [1?D], a[2+5D+2D2] [1?D], and a[1+4D+2D2] [1?D] where a is an integer.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: An apparatus and method are disclosed for decoding servo data recorded on a magnetic disk drive and detecting pinned layer reversals and signal errors, for example, errors due to noise. The servo data is encoded using wide-bi-phase encoding. This encoding is detected by a magneto-resistive sensor that senses the magnetization in domains passing by the sensor. The decoder includes an A/D converter for sampling the signals emitted by the sensor, to provide a sequence of the encoded data. A trellis, such as a Viterbi trellis, is employed to decode the samples generated by the converter. The trellis includes nodes representing states, connected by paths representing transitions, among the nodes. A quality value is generated for the transitions, the quality value representing the distance between each sample in the sequence output by the A/D converter and a corresponding expected sample.

Abstract: A magnetic recording device write channel includes a write equalization encoder for generating a write equalization level signal and a digital to analog converter for converting the write data signal to analog signals for recording. The write equalization level signal from the write equalization encoding device controls an impedance value at an output of said digital-to-analog converter. The output of the digital-to-analog converter is connected to an input of the data transmission line which transmits the write data signal to a write head of the magnetic recording device. Variation in the output impedance of the digital-to-analog converter by comparison to the input impedance of the transmission line controls the level of the equalization transmitted to the write head of the magnetic recording device.

Abstract: A phase error reduction system includes a control module, a phase-locked loop (PLL) module, and a harmonic removal module. The control module generates source timestamps for a plurality of synchronization marks in a source signal using a clock and generates a plurality of target tirnestamps. The PLL module determines phase errors between the source timestamps and the target timestamps and minimizes the phase errors. The harmonic removal module removes harmonics of the phase errors using a weighted moving average filter (MAF). The harmonic removal module comprises a repetitive feed forward (RFF) module that includes an amplifier the scales the phase errors, a delay buffer that generates RFF commands to reduce the phase errors, and a summing module. The MAF filters the RFF commands. The summing module provides sums of the phase errors scaled by the amplifier and the RFF commands filtered by the weighted MAF to the delay buffer.

Abstract: A readback apparatus (a) calculates a variance value of a signal read by a head from a disc medium, (b) estimates a degree of offtracking of the head from a target track to an adjacent track, and interference power from the adjacent track using the variance value of the signal, (c) calculates a soft decision likelihood value for the signal using the degree of offtracking and the interference power, and (d) performs error correcting decoding using the soft decision likelihood value.

Abstract: One embodiment of an equalizer circuit has an FIR filter 116 in the asynchronously oversampled domain with a filter coefficient adaptation module that adapts the filter coefficients to the transfer function of a data read channel. Applications include tape drives, drives for optical and magnetic discs as well as receivers. The filter adaptation is performed on the basis of an error signal delivered by a slicer 128 which operates on synchronous samples after timing recovery and sample reconstruction.

Abstract: A phase locking apparatus is disclosed which, includes a phase error information detecting device to detect phase error information indicating the phase error. The device has a phase position determining device to determine, based on run length limited information, whether or not phase positions of a first and second value from among sampling values constituting synchronous data are under a reverse phase condition in effect when only one of the first and the second values is in excess of a predetermined threshold, and a phase error information calculating device to calculate the phase error information in each of two cases determined, one with the reverse phase condition found to be in effect and the other without effect.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback in magnetic recording systems. A read channel signal is processed in a magnetic recording device by precomputing branch metrics, intersymbol interference estimates or intersymbol interference-free signal estimates for speculative sequences of one or more channel symbols; selecting one of the precomputed values based on at least one decision from at least one corresponding state; and selecting a path having a best path metric for a given state.

Abstract: A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: A novel means for performing dibit extraction is presented. Any one of an unequalized signal dibit, equalized signal dibit, or noise dibit can be extracted. Instead of using the correlation properties of a PN (Pseudo-Noise) sequence to approximate a PN deconvolution sequence, the use of the actual deconvolution sequence (i.e., PN sequence that includes values of +k and 0, where k is oftentimes 1) is employed so that no approximations are needed. The resulting estimate of the channel is therefore very accurate.

Abstract: Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values.

Abstract: Embodiments in accordance with the present invention provide a disk drive and a control method in the disk drive which can obtain good recording performance by amplifying the write current according to the recording method and the recording frequency. A HDD in accordance with an embodiment of the present invention comprises a write current supply section and a write head. The write current supply section generates a write signal for recording to a disk and, based on the write current, generates a write current IW. The write head records data to the disk by the write current IW. The write current supply section comprises a write channel to generate a write signal, a write driver to generate a write current from the write signal, a high frequency pattern extracting circuit to extract high frequency pattern parts from the write signal, and a write driver to generate a write current IB from the extracted high frequency pattern parts.

Abstract: A signal processing circuit performs processing for an analog signal output from a head. The signal processing circuit includes: a conversion section that generates a digital signal based on the analog signal; a first filter that equalizes the output of the conversion section; a demodulation section that demodulates data from the output of the first filter; a modulation section that modulates a waveform based on the data demodulated by the demodulation section; a second filter that equalizes the output of the modulation section; and an adaptation section that adapts the response of the second filter such that the output of the second filter becomes equal to the output of the conversion section.

Abstract: Provided is a read channel incorporated in a storage device to process signals read from a storage medium. The read channel includes an equalizer equalizing input read signals to produce equalizer output signals. A detector senses an adjusted equalizer output signal to determine an output value comprising data represented by the input read signals. An equalizer adaptor receives the output value from the detector to determine a first error signal used to adjust the equalizer operations. A component adjusts the equalizer output signals being transmitted to the detector, wherein the component is adjusted by a second error signal calculated from the output value from the detector, wherein the first and second error signals are different.

Abstract: An adaptive asymmetry control circuit is described. Such a circuit may be used in magnetic recording applications, for example. The adaptive asymmetry control circuit uses a peak detector which supplies at regular intervals positive or negative signal peak values of an equalized sampled data stream. An asymmetry learning function generates a summation of N pairs of positive and negative signal peak values divided by N as an average signal asymmetry value. The average signal asymmetry value is divided by 2 in an optimal threshold function producing an optimal threshold value. Then a threshold detector, that uses the optimal threshold value as a threshold, slices the sampled data stream at regular intervals.

Abstract: A method used in a disk drive system for compensating a frequency component affecting servo control performance. The method includes detecting a frequency component affecting a servo control output in a disk drive/head during a manufacturing process and storing the detected frequency component in a nonvolatile memory device. A frequency component is read from a nonvolatile memory device corresponding to a selected head each time the disk drive is turned on by a user. A parameter value of a filter is determined by using a servo control circuit of the disk drive to suppress the read frequency component.

Abstract: A phase interpolator is provided that, in one implementation, includes an output node, a plurality of phase input circuits, and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit is operable to receive a given phase signal. Each switch is in communication with a given phase input circuit and is operable to couple a given phase signal to the output node.

Abstract: A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.

Abstract: In an apparatus for recording and regenerating data, a pass metric is calculated based on a likelihood converted from a previous calculation result iteratively until all pass metrics of the same data recorded many times on a recording medium are calculated, and then data recorded on the recording medium is decoded.

Abstract: Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.

Abstract: Timing recovery in partial-response-based magnetic recording systems customarily employs the “decision-directed” method wherein phase error is recovered from the differences between the noise-corrupted received signal samples and their estimated ideal (noise and phase error free) values. The filtered phase error drives a numerically-controlled oscillator which determines the instants at which the signal is resampled, attempting to place said instants at the ideal sampling times. The resampled signal contains errors due to mistiming as well as to the original corrupting noise, and these errors directly influence the success of subsequent detection. However, the noise can be reduced using adaptive linear prediction, having the effect of reducing the output error for a given noise input, or maintaining the same error for a larger noise input.

Abstract: A method for optimizing read/write channel parameters of a hard disk drive. The process includes measuring a first bit error rate of a head using an initial set of read/write channel parameters and varying all of the read/write channel parameters with a random jump. The random jump may be created from the generation of a random number. The process then includes measuring a second bit error rate of the head using the varied read channel parameters and accepting the varied read/write channel parameters as the new optimum, if the second bit error rate is lower than the first bit error rate.

Abstract: Embodiments of the present invention provide optimization of read/write channels in a recording system by embedding channel optimization algorithm/procedure into the channels, or a system-on-chip (SOC) where a read/write channel is integrated with a disk drive controller, according to an Embedded Channel Optimization Solution (ECOS).

Abstract: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

Abstract: A read/write channel for a hard disk drive comprising at least one analog read component and a fly height control system. The fly height control system controls fly height based on a current fly height value generated based on a fly height measurement signal that passes through the at least one analog read component. The read/write channel comprises a calibration signal generator and a processor. The calibration signal generator generates a calibration signal that is coupled to the at least analog read component to place the read/write channel in a calibration mode. The processor generates compensation data based on an output of the at least one analog read component when the read/write channel is in the calibration mode. The processor generates the current fly height value based on the fly height measurement signal and the compensation data when the read/write channel is in a fly height measurement mode.