Abstract: A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.

Abstract: In an embodiment, a semiconductor device is disclosed that includes at least one processing device and firmware including a dynamic demodulation engine. The dynamic demodulation engine, when executed by the at least one processing device, is configured to obtain a digital signal waveform, dynamically select a bit detection method based at least in part on a characteristic of the digital signal waveform, perform demodulation of the digital signal waveform using the selected bit detection method and generate decoded packets based at least in part on the demodulation.

Abstract: According to one embodiment, a magnetic recording device includes a magnetic head and a controller. The magnetic head includes first and second magnetic poles, a magnetic element provided between the first magnetic pole and the second magnetic pole, first and second terminals electrically connected to one end and another end of the magnetic element, respectively, and a coil. The controller is electrically connected to the magnetic element and the coil, and performs a recording operation. In the recording operation, the controller supplies a recording current to the coil while applying an element voltage between the first and second terminals. When the applied voltage is changed while the recording current is supplied, a differential resistance of the magnetic element becomes a first differential resistance peak when the applied voltage is a first voltage, and becomes a second differential resistance peak when the applied voltage is a second voltage.

Abstract: In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After tpz, during a compensation time period (tcomp), the current sources enabled during td are disabled and a compensation current source is enabled. After tcomp, the compensation current source is disabled.

Abstract: Systems and methods for implementation of modified decision feedback equalization. In one embodiment, a method, includes sweeping a reference voltage signal across a set of voltages to find a center point of an eye diagram, determining whether an asymmetry is present in the eye diagram relative to the center point of the eye diagram, and when an asymmetry is determined to be present, generating a control signal to select a mode of decision feedback equalization to be applied to an input data bit.

Abstract: Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.

Abstract: According to one embodiment, a magnetic disk device includes a recording medium, a recording head including a main magnetic pole, a write shield magnetic pole, a coil, and a spin torque oscillator provided between the main magnetic pole and the write shield magnetic pole and a controller including a record current supply circuit and a drive current supply circuit. The controller executes a process of monitoring variation of a resistance value of the spin torque oscillator while increasing the record current in a state in which the spin torque oscillator is energized and detecting a record current value when the resistance value is increased most largely, and a process of setting the detected record current value to a lower limit of the record current supplied to the coil.

Abstract: According to one embodiment, a magnetic disk device includes a disk, a head including a read head that reads data from the disk, a write head that writes data into the disk, and an assist element that generates energy for improving write performance of the write head, and a controller that adjusts a degauss condition after a stop of a write process of the write head, based on a resistance value of the assist element, and adjusts a data format of the disk in accordance with the degauss condition, the resistance value being measured after data is written into the disk, and the write process having an influence on the resistance value.

Abstract: Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.

Abstract: A method for writing servo data includes: writing the servo data as the head moves outwardly towards a radial position on the disk one step at a time, wherein the same address data are written as the head moves outwardly in two consecutive steps, writing the servo data as the head moves inwardly towards the radial position one step at a time, so as to overwrite part of servo data that have been written in a previous step, wherein the same address data are written as the head moves inwardly in two consecutive steps, and writing either one of two-phase burst data, or address data and the other of said two-phase burst data, at the radial position.

Abstract: Apparatus for generating supply voltages in a data storage device. In some embodiments, the apparatus includes a data transducer adjacent a rotatable magnetic recording medium, the data transducer having a write coil and an electromagnetic source for thermally assisted recording by the write coil. A preamplifier/driver circuit (preamp) has a write driver adapted to supply write currents to the write coil and a source driver adapted to supply source voltage to the electromagnetic source. A voltage regulation circuit applies a first positive supply voltage to the write driver and a different, second positive supply voltage to the source driver.

Abstract: A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.

Abstract: Provided is a storage apparatus that detects abnormalities of a hard disk caused by the instantaneous power failure of a low voltage power supply. An effective value reduction detecting circuit transmits a detection signal, when the voltage of a low voltage power supply is lower than specific voltage. CPU memorizes time t1 to a flash memory. Also, CPU memorizes time t2, when recovering low voltage power supply 13 on proper voltage. Then, CPU computes period of time T, which is time between time t1 and t2. If the computed period of time T is within a range from first period of time T1 to the second period of time T2, CPU operates a voltage switch and re-supply the power supply to the hard disk. If not within the range, CPU does not re-supply power to the hard disk.

Abstract: The magnetic disk unit includes: a magnetic recording medium; a thermally-assisted magnetic recording head including a magnetic pole applying a recording magnetic field to the magnetic recording medium and a heating element heating the magnetic recording medium; and a controller allowing the heating element to perform a continuous heating operation at a first temperature for a first time period, and halting the heating operation of the heating element or allowing the heating element to perform a heating operation at a second temperature lower than the first temperature for a second time period that follows the first time period, the first time period having a length substantially equal to or less than a length of a time required for the magnetic recording medium to rotate one turn, and the second time period having a length substantially equal to or more than the length of the first time period.

Abstract: An aspect of the present invention includes a circuit having a cascoded H-bridge, an upper voltage supply component, a lower voltage supply component and a pre-driver component. The cascoded H-bridge is arranged to provide a driving signal for driving a load. The upper voltage supply component can provide an upper supply voltage to the cascoded H-bridge. The lower voltage supply component can provide a lower supply voltage to the cascoded H-bridge. The pre-driver component can provide a pre-driving signal to the cascoded H-bridge, wherein pre-driver component has a first voltage source and a second voltage source. The first voltage source can provide an upper swing voltage and the second voltage source can provide a lower swing voltage. The pre-driver component can provide the pre-driving signal based on the upper swing voltage, the lower swing voltage and one of the upper supply voltage and the lower supply voltage.

Abstract: Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and providing an input to AB drivers of the output stage, in which an offset test circuit selectively drives the high pass filter output nodes according to the offset at the filter input to facilitate measurement of the preceding circuit offset at the driver output terminals, and a common mode regulator circuit regulates common mode voltages at the first and second driver output nodes to a predetermined value in read and write modes.

Abstract: According to one embodiment, a magnetic disk apparatus includes a main magnetic pole configured to apply a recording magnetic field to a recording medium, a recording coil configured to magnetize the main magnetic pole, a spin-torque oscillator adjacent to the main magnetic pole, and configured to generate a high frequency magnetic field, a recording current control circuit configured to supply a recording current to the recording coil, a driving current control circuit configured to supply a fixed driving current to the spin-torque oscillator, and an overshoot control circuit configured to control overshoot current of the recording current in proportion to the magnitude of the driving current after the recording current has reversed.

Abstract: Interface circuitry of a storage device or other type of processing device comprises a digital input detector and an adaptive power supply. The digital input detector comprises an input transistor. The adaptive power supply provides a variable supply voltage to the digital input detector that varies with a threshold voltage of the input transistor. In one embodiment, the variable supply voltage provided to the digital input detector by the adaptive power supply varies with the threshold voltage of the input transistor about a set point value determined as a function of an expected logic level of an input signal. For example, the set point value may be determined as a function of a minimum expected logic high input signal level. In such an arrangement, the input transistor is biased at or close to the threshold voltage for an input signal having the minimum expected logic high input signal level.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises degauss circuitry coupled to or otherwise associated with one or more write drivers. The degauss circuitry is configured to generate an asymmetric degauss signal to be applied to the write head. The asymmetric degauss signal has a waveform with upper and lower decay envelopes that are asymmetric about a specified degauss current level, such as a substantially zero current level.

Abstract: Approaches described in this disclosure are generally directed to methods and devices for delaying a write turn-on of a memory device. A write control signal from a memory controller to a preamplifier of a storage device is asserted. A warm-up interval of write drivers of the preamplifier is initiated, the warm-up interval having a duration of predetermined length. Data is transmitted to the write drivers during the warm-up interval.

Abstract: Write enhancement circuitry on the head carrier of a magnetic recording disk drive provides additional write current overshoot beyond that provided by the write driver circuitry. The write enhancement circuitry is formed on the head carrier as ladder network blocks. A first ladder network block is a first capacitor C1 located in parallel with the write coil. The second ladder network block includes a second capacitor C2 having substantially the same inductance L2. The compensation circuitry is referred to as a ladder network because additional ladder blocks, like the second block but with different values of capacitance and inductance, may be located on the head carrier.

Abstract: A write driver circuit for generating a write current pulse for use by a magnetic write head includes an output stage adapted for connection with the magnetic write head and a charge storage circuit connected with the output stage. The charge storage circuit is operative in a first mode to store a prescribed charge and is operative in a second mode to transfer at least a portion of the charge stored therein to the output stage to thereby enable an output voltage level of the output stage to extend beyond a voltage supply rail of the write driver circuit. A control circuit in the write driver circuit is operative to generate at least one control signal for selectively controlling a mode of operation of the charge storage circuit.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising write pulses responsive to write data, and a driver controller configured to adjust overshoot amplitudes of respective ones of the write pulses utilizing a segmented digital-to-analog converter. The overshoot amplitudes are adjusted by detecting patterns in the write data, decoding a first portion of a base overshoot value to identify a corresponding number of base overshoot segments, combining the base overshoot value and a differential overshoot value, decoding a first portion of the combined base overshoot and differential overshoot values to identify a corresponding number of enhanced overshoot segments, and selecting between the number of base overshoot segments and the number of enhanced overshoot segments responsive to detection of a particular pattern.

Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Abstract: In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: Systems and/or methods for measuring latency in an electronic device such as, e.g., a storage device, may include coupling circuitry configured to capacitively couple an outbound or write data path to an inbound or read data path. A latency measurement signal may be driven on the write data path, the coupling circuitry may transmit at least a portion of the latency measurement signal from the write data path to the read data path, and the latency measurement signal may be sensed on the read data path to be used to determine communication path latency in the device.

Abstract: A first parameter associated with a writer preamp is defined. A write current of the writer preamp is adjusted in accordance with the first parameter so that an asymmetric signal is applied at a write head. The asymmetric signal results in symmetric writing of bits to a medium.

Abstract: Method and apparatus for detecting head disk interference (HDI). In accordance with some embodiments, a bias calibration circuit is adapted to respectively bypass or amplify a head disk interference (HDI) signal output from an HDI sensor responsive to a bias voltage adjusted according to a first control signal. A detection circuit is adapted to compare a swing range of a signal output from the bias calibration circuit and a swing range of a reference signal, and to output the first control signal responsive to said comparison.

Abstract: Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and providing an input to AB drivers of the output stage, in which an offset test circuit selectively drives the high pass filter output nodes according to the offset at the filter input to facilitate measurement of the preceding circuit offset at the driver output terminals, and a common mode regulator circuit regulates common mode voltages at the first and second driver output nodes to a predetermined value in read and write modes.

Abstract: A method for calibrating a reflection compensator is provided. A delay is initially set to a predetermined minimum, and an input pulse is transmitted across a transmission line. A compensation current is then applied after the delay. The reflection from the transmission line is digitized to generate a measurement, and a determination is made as to whether the compensation current substantially compensates for the reflection. If the compensation current does not substantially compensate for the reflection, then the delay is adjusted, and the process is repeated until the compensation current substantially compensates for the reflection.

Abstract: A HDD including write components configured to operate within an operating voltage range, charging circuitry comprising a charging capacitor. The charging capacitor includes a higher voltage when charged than the operating voltage range. The HDD also includes pulse circuitry configured to pulse power from the charging circuitry to the write components within the operating voltage range during a controlled shut down of the write components such that remaining data-sector bits are written during the controlled shut down.

Abstract: Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.

Abstract: A disk drive is disclosed comprising a disk, an actuator arm comprising a suspension, and a head coupled to a distal end of the suspension, wherein the head comprises a write coil. The disk drive further comprises a preamp operable to generate a write current applied to the write coil in response to a single polarity supply voltage which may be positive or negative. In one embodiment, the transmission lines that couple the write coil to the suspension comprise respective, parallel plate sections that form a capacitance which enables driving the preamp with the single polarity supply voltage.

Abstract: A circuit for use with a memory storage device including a magnetic storage medium and a write head operative to subject the magnetic storage medium to a magnetic field in response to an application of current to the write head, includes a write circuit operative to generate a write current supplied to the write head. The write current is characterized by a current waveform that reverses polarity in accordance with data to be stored on the magnetic medium. The circuit for use with the memory storage device further includes a degauss circuit operative to generate a degaussing current supplied to the write head. The degaussing current is characterized by a current waveform that oscillates between opposite polarities with an amplitude and a frequency that change over time.

Abstract: A system including a first circuit and a second circuit. The first circuit is configured to (i) select a first portion of a signal based on a first offset, (ii) amplify the first portion of the signal according to a first function, and (iii) scale the amplified first portion based on a first factor to generate a first compensation for asymmetry in the first portion of the signal. The second circuit is configured to (i) select a second portion of the signal based on a second offset, (ii) amplify the second portion according to a second function, and (iii) scale the amplified second portion based on a second factor to generate a second compensation for asymmetry in the second portion of the signal.

Abstract: A method of operating a pre-amplifier of a hard disk drive is provided. The method includes generating a comparison signal corresponding to a result of comparing a reference signal with a difference between differential signals corresponding to write data, and controlling transmission of the differential signals to a write head in response to the comparison signal.

Abstract: An apparatus comprising a control circuit, a driver circuit and a write head. The control circuit may be configured to generate a plurality of control signals in response to a data input signal. The driver circuit may be configured to generate a differential write control signal in response to the plurality of control signals. The driver circuit may receive the plurality of control signals through a flexible bus. The driver circuit may be located remotely from the control circuit. The write head may be configured to write information by physically moving above one of a plurality of tracks on a disk in response to the write control signal. The driver circuit may be configured to move along with the write head.

Abstract: A device for setting a bias for a magneto-resistive (MR) head can include a counter configured to provide a count value that varies incrementally from a first count value to a maximum count value. Logic is configured to determine at least one of whether the bias for the MR head has reached a predetermined threshold and whether the counter has reached the maximum count value. The logic provides a bias output signal corresponding to the count value for setting the bias of the MR head according to the determination by the logic.

Abstract: A disk drive data storage system comprising at least one data storage disk and a sensor assembly proximate the data storage disk. The sensor assembly further comprises circuitry for writing data to the data storage disk and circuitry for reading data from the data storage disk. The system also comprises circuitry for controlling the circuitry for reading data during different time periods so that the circuitry for reading data consumes different levels of power while the circuitry for writing data is writing data to the data storage disk.

Abstract: A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC current signal; a first resistor coupled at one end to a first voltage supply; a first current driver coupled to the input current driver and a first switch control; a second switch coupled a first current driver output, another end of the first resistor, and the output control; a dynamic booster coupled between the first voltage supply and the output control; and wherein the reduced power driver is operative for selectively adding an overshoot current to the output control so that power consumption is reduced, while synchronizing the DC current signal with the overshoot current.

Abstract: An apparatus including one or more reader circuits, one or more writer circuits, and a loopback channel. The one or more reader circuits may be configured to read data from a magnetic medium. The one or more writer circuits may be configured to write data to the magnetic medium. The loopback channel is coupled between the one or more reader circuits and the one or more writer circuits.

Abstract: A circuit for compensating asymmetry in a waveform of an input signal using a piecewise approximation of a saturation curve, the circuit including a first circuit configured to output a first compensation for a first section of the saturation curve using a first function and a second circuit configured to output a second compensation for a second section of the saturation curve using a second function. The second function is different than the first function. The first compensation and the second compensation provide the piecewise approximation of a region of the saturation curve. The region includes at least the first second and the second section.

Abstract: A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal.

Abstract: Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

Abstract: A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned recording media. The preamplifier contains a write pre-driver that conditions write data, a synchronization circuit that accepts a delay offset value and a write clock and produces a delayed clock, and a write output driver that is gated by the delayed clock to produce write pulses for magnetizing the bit islands. Gating the write output driver using the delayed clock results in more accurate synchronization than delaying the write data into the preamplifier due to the reduction of the overall length and variability of interconnects and transistors in the intervening circuitry.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: A magnetic device includes a write element having a write element tip and a conductive coil for carrying a current to induce a first field from the write element. A conductor proximate the write element tip carries the current to generate a second field that augments the first field. A driver provides the current to the conductive coil and the conductor, and a circuit phase shifts the current through the conductor relative to the current through the conductive coil.

Abstract: An object of the present invention is to provide a deterioration detection method of a head and a magnetic disk inspection apparatus in which the number of times of exchanging the head due to deterioration is decreased to improve the throughput of an inspection. In the present invention, a resistance value detecting circuit that is directly coupled to both terminals of an MR head is provided to measure the resistance value of the MR head, and the measured value is compared with the initial value of the exchanged head, so that it is possible to recognize a deterioration state of each head irrespective of a magnetic disk as a measurement target.

Abstract: A circuit for providing a write current having a programmably adjustable duty cycle in a hard disk drive write channel has a differential pair gain circuit for receiving a data input signal and generating a differential output voltage to provide a differential write signal for generating the write current. First and second programmable current sources are connected to the differential pair gain circuit to create a programmable voltage offset of the differential output voltage to programmably adjust the duty cycle of the write current.