Recording Amplifier Patents (Class 360/68)
  • Patent number: 7417817
    Abstract: A write driver circuit for a magnetic storage medium includes a first write driver sub-circuit that has an output that communicates with a first node of a write head. The first write driver circuit includes a first driver circuit and a first feedback path between the input and the output of the first driver circuit. A second write driver sub-circuit has an output that communicates with a second node of the write head. The second write driver sub-circuit includes a second driver circuit and a second feedback path between the input and the output of the second driver circuit. The write driver circuit has a substantially constant output impedance during operation, balanced differential and common mode resistances, and a substantially constant common mode voltage across the write head during operation.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: August 26, 2008
    Assignee: Marvell International Ltd.
    Inventors: Farbod Aram, Sehat Sutardja
  • Patent number: 7417713
    Abstract: An optical disc used for storing content includes a theft control area selected to render the disc unreadable. The disc must be exposed to radiation of a specific wavelength before it can be read by a regular device. The theft control area may include an area that contains data that instructs the device not to read the disc. This area includes a coating that changes its optical characteristics when exposed to the radiation. The material could be radiochromic or thermochromic. Alternatively, the theft control area includes an RFID device that includes an element that is radiation sensitive. In this embodiment, when the disc is irradiated, the element changes its electrical characteristics.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: August 26, 2008
    Assignee: Warner Bros. Entertainment Inc.
    Inventors: Wayne M Smith, Christopher J Cookson, Lewis S Ostrover, Alan E Bell
  • Patent number: 7411755
    Abstract: A write driver system comprises first switching devices that generate gate drive signals. A write driver circuit includes second switching devices that are controlled by the gate drive signals. The second switching devices have higher voltage stress thresholds than the first switching devices and wherein the second switching devices have slower switching times than the first switching devices.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 12, 2008
    Assignee: Marvell International Ltd.
    Inventors: Farbod Aram, Pantas Sutardja
  • Patent number: 7408313
    Abstract: A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: August 5, 2008
    Assignee: Marvell International Ltd.
    Inventors: Chan Sang Kong, Kien Beng Tan, Xiao Yu Miao
  • Patent number: 7405894
    Abstract: One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: July 29, 2008
    Assignee: Broadcom Corporation
    Inventors: Chengzhi Pan, Andrei Vityaev
  • Patent number: 7375909
    Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 20, 2008
    Assignee: STMicroelectronics, Inc.
    Inventors: Alessandro Venca, Roberto Alini, Baris Posat
  • Patent number: 7372649
    Abstract: An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Cougar VanEaton, Bryan E. Bloodworth, Glenn Mayfield, Tuan Van Ngo
  • Patent number: 7372653
    Abstract: Embodiments of the invention provide a hard disk drive that is capable of performing degaussing promptly and properly and a recording method for use with such a hard disk drive. A hard disk drive according to one embodiment of the present invention comprises a current source for supplying a first current, which flows to a write head for writing data onto a magnetic disk; a current source for supplying a second current, which flows to the write head when the polarity of the first current changes; transistors for reversing the polarity of a current flowing to the write head; and a control circuit for exercising control so that the second current I2, which flows from the current source to the write head when the polarity of the first current I1 is reversed, becomes approximately zero before the first current I1 converges to approximately zero during a degauss period.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 13, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hiroaki Suzuki, Kenji Okada
  • Publication number: 20080100948
    Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Inventor: Larry LeeRoy Tretter
  • Patent number: 7365928
    Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: April 29, 2008
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.R.L.
    Inventors: Alessandro Venca, Roberto Alini, Baris Posat
  • Patent number: 7362530
    Abstract: An amplifier apparatus for use with a sensor includes: (a) a first and a second amplifying circuit segment coupled with the sensor and cooperating to effect substantially balanced handling of signals received from the sensor; the first amplifying circuit segment includes a first transistor device; the second amplifying circuit segment includes a second transistor device; (b) a countercurrent unit coupled with the first and second amplifying circuit segments for receiving a first indicator signal from the first transistor device and a second indicator signal from the second transistor device; the first indicator signal represents a first parameter in the first transistor device; the second indicator signal represents a second parameter in the second transistor device; the countercurrent unit provides feedback signals to at least one of the first transistor and second transistor devices to reduce input impedance of the apparatus.
    Type: Grant
    Filed: November 6, 2004
    Date of Patent: April 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Motomu Hashizume
  • Patent number: 7355804
    Abstract: A disk drive includes a rotatable data storage disk, and head, a controller, and a preamplifier. The head is configured to write data to and read data from the disk. The controller is configured to generate a write current command. The preamplifier includes a plurality of write current parameters, and is configured to select among the plurality of write current parameters based on the write current command from the controller, and to generate a write current having a shape that varies based on which of the write current parameters are selected. The write current is provided to the head to write a plurality of data bits on the disk.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: April 8, 2008
    Assignee: Maxtor Corporation
    Inventors: Roger Kassab, Richard E. Olsen
  • Publication number: 20080055760
    Abstract: An H-bridge driver for a disk drive system includes first and second high side switched legs and first and second low side switched legs. An inductor head for writing data to and reading data from a magnetic media is connected to form a center of the H-bridge. The system includes a voltage regulator circuit that generates a common mode regulated voltage. First and second high side logic circuits, which selectively control operation of the first and second high side switched legs, are coupled between a high reference voltage and the common mode regulated voltage. First and second low side logic circuits, which control the first and second low side switched legs, are coupled between the common mode regulated voltage and ground.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Inventors: Vineet Tiwari, Baris Posat
  • Patent number: 7339760
    Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Agere Systems Inc.
    Inventors: Jeffrey A. Gleason, John D. Leighton, Scott M. O'Brien
  • Patent number: 7315428
    Abstract: In one embodiment, a magnetic media write signal filter includes a plurality of resistors connected in series across output signal lines of a write driver and a capacitor connected between a junction of resistors and a ground.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: January 1, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lawrence A. Hansen, Gary Bartles
  • Patent number: 7292074
    Abstract: The present invention describes a voltage-mode boosting write driver circuit (160), comprising a plurality of inputs (WDP, WDN), a plurality of outputs (HWX, HWY), a transducer (L2), a flex interconnection (T1) coupled to the outputs (HWX, HWY) and to the transducer (L2), a first resistor (R15) and a second resistor (R43) coupled to the outputs (HWX, HWY) and to the transducer (L2), an H-switch (Q15, Q60, Q11, Q22) coupled to the resistors (R15, R43), and a plurality of top boosting circuits (Q42, Q47, R36, and Q43, Q48, R37) coupled to the outputs (HWX, HWY).
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Raymond Elijah Barnett, Tuan Van Ngo
  • Patent number: 7280300
    Abstract: A write driver circuit for a magnetic storage medium that communicates with a write head having first and second nodes comprises a first driver circuit having a first input, a first output that communicates with the first node, and a first feedback path between the first input and the first output. A second driver circuit has a second input, a second output that communicates with the second node, and a second feedback path between the second input and the second output. A first write current circuit selectively drives current through the write head in a first direction. A second write current circuit selectively drives current through the write head in a second direction. A first boost circuit decreases a first transition period between current flowing in the first direction and current flowing in the second direction.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: October 9, 2007
    Assignee: Marvell International Ltd.
    Inventors: Farbod Aram, Sehat Sutardja
  • Patent number: 7277245
    Abstract: A write driver circuit for a magnetic storage medium that communicates with a write head having first and second nodes comprises a first driver circuit with an input and an output that communicates with the first node of the write head. A first charge pump communicates with said input and said output of said first driver circuit and provides additional current to said input of said first driver circuit during a first transition period between current flowing through the write head in a first direction and current flowing through the write head in a second direction. A second driver circuit with an input and an output communicates with the second node of the write head. A second charge pump communicates with said input and said output of said second driver circuit and provides additional current to said input of said second driver circuit during a second transition period between current flowing through the write head in said second direction and current flowing through the write head in said first direction.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: October 2, 2007
    Assignee: Marvell International Ltd.
    Inventors: Farbod Aram, Sehat Sutardja
  • Patent number: 7271971
    Abstract: A read channel equalizer of a magnetic tape drive which equalizes digitally sampled magnetic signals detected by a read head is dynamically adapted. A detector of equalizer dynamic adaptation logic compares equalizer output signals to desired values that are based on the decoding scheme (such as +2, 0 and ?2 for PR4) to sense equalizer output signals that are offset from at least one desired value, and signals the fact of each offset and its polarity as amplitude independent error signals. The signaled sensed amplitude independent error signals are fed back to adjustable taps of the equalizer. The simplified error signals thus avoid complex calculations of waveform errors, such as least mean square calculations. The error signals may be weighted and may be adjusted to align synchronously provided error signals with asynchronous taps of the equalizer.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert Allen Hutchins, Glen Alan Jaquette, Evangelos S. Eleftheriou, Sedat Oelcer
  • Publication number: 20070211365
    Abstract: There is provided a magnetic disk device or the like which is capable of improving signal quality by suppressing occurrence of erasure of adjacent tracks due to spreading of a writing spot. The magnetic disk device is capable of controlling a steady state value of a write current for writing into a magnetic disk, an overshoot value, or a width thereof. The magnetic disk device comprises a VMM measurement section that measures a VMM, and a write current setting section that sets the write current, based on a value of the VMM measured by the VMM measurement section, such that a data writing spot is prevented from spreading during writing into the medium and occurrence of side erasure is prevented.
    Type: Application
    Filed: June 14, 2006
    Publication date: September 13, 2007
    Inventor: Yuichiro Yamazaki
  • Patent number: 7265926
    Abstract: A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The first and second voltage circuitry comprises a first transistor (421P2) of a first type and coupled to the first node, a first transistor (422N2) of a second type and coupled to the second node, a second transistor (441P2) of the first type and coupled to the second node, and a second transistor (442N2) of the second type and coupled to the node. The system also comprises circuitry for providing, during a first time period, a first biasing signal (VNDY) and a second biasing signal (VPDY) and circuitry for providing, during a second time period, a third biasing signal (VNDX) and a fourth biasing signal (VPDX).
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: September 4, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Reza Sharifi
  • Publication number: 20070195446
    Abstract: Provided is a method and an apparatus for controlling a write parameter according to a voltage variation. The method for controlling the write parameter includes monitoring a voltage supplied to a pre-amplifier before performing a write operation and adjusting the write parameter supplied to the pre-amplifier based on the monitoring result. Controlling the write parameter includes reading a predetermined write parameter from a write parameter table based on the monitoring result, and adjusting the read write parameter to the write parameter which will be supplied to the pre-amplifier.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 23, 2007
    Inventor: Jong-Yun Yun
  • Patent number: 7256954
    Abstract: An adaptive equalizer comprising a variable filter which equalizes a digital input signal which is input in a time sequential order, an adaptive controller unit which updates a filter coefficient of the variable filter based on an output signal of the variable filter and the input signal and according to an equalization algorithm, and a coefficient resetting unit which resets a filter coefficient of the variable filter at a predetermined timing.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: August 14, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Orimitsu Serizawa
  • Patent number: 7256955
    Abstract: Data is written to a magnetic media, by applying a magnetic write field to the magnetic media with a write pole, in conjunction with a high frequency magnetic field, to the magnetic media to assist writing to the magnetic media. The high frequency magnetic field is generated by applying a specific write current waveform to the magnetic writer, resulting in the generation of a high frequency magnetic write field.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: August 14, 2007
    Assignee: Seagate Technology LLC
    Inventors: Taras G. Pokhil, Victor B. Sapozhnikov, Andrzej A. Stankiewicz, Janusz J. Nowak
  • Publication number: 20070183072
    Abstract: A magnetic recording method is provided where ternary data is recorded on a magnetic recording medium by forming a first area that corresponds to a first value of the data and in which a first magnetization state is continued at least during the minimum write width. A second area that corresponds to a second value of the data in which a second magnetization state is oppositely magnetized as compared with the first magnetization state is continued at least during the minimum write width. A third area that corresponds to a third value of the data in which the magnetic intensity detected by the read head corresponds to a “0.” Accordingly, the ternary data can be recorded using the characteristic that a signal having a width narrower than the detection width of the read head is not detected by the read head.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 9, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chul-woo Lee
  • Patent number: 7253978
    Abstract: The invention includes a testing method which may be applied to at least one writer in a disk drive during the self-test phase to generate write parameters, focused on the Over Shoot Control (OSC) of the write current parameter to improve the reliability of write operations by that writer. The Minimum OSC is used for write operations in normal temperatures. The Optimum OSC is used for a first lower temperature range, preferably between essentially 15 degrees Centigrade and essentially 5 degrees Centigrade. The Maximum OSC is preferred below essentially 5 degrees Centigrade. The Minimum OSC should preferably guarantee both an Adjacent Track Write (ATW) criteria, as well as guarantee a Write Induced Instability (WII) criteria. The invention includes the write parameter collection, as well as the disk drive containing the generated write parameter collection.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae Jung Lee, Sang Lee, Keung Youn Cho
  • Patent number: 7242545
    Abstract: An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 10, 2007
    Assignee: Marvell International Ltd.
    Inventor: Chi Fung Cheng
  • Patent number: 7242544
    Abstract: An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current directing circuit receiving the write signals and directing a write current to establish a write voltage between first and second write loci in a first or second excursion toward a first or second polarity in response to the first or second write signal. The first and second write loci are coupled with supply locus via an adjacent first or second impedance unit and a first or second switching unit. The first and second switching units are controlled at first and second control loci by the first and second write signals. First and second boost systems are coupled with the first and second control loci for boosting the write voltage toward the first and second polarities during first and second excursions.
    Type: Grant
    Filed: January 10, 2004
    Date of Patent: July 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Joseph Price, Jr., Tuan Van Ngo
  • Patent number: 7224135
    Abstract: A method for driving a motor by imposing the current in the motor by means of power current mirrors is presented. This allows driving the motor in current with higher accuracy and lower electrical noise. The Hard Disk Drive application is an example where higher resolution is required for the VCM motor. Furthermore this method reduces the complexity of the system eliminating components and high performance circuits. Moreover this approach reduces the development and manufacturing cost by simplifying the testability and the analysis of the system. The intrinsic elimination of DC offset also takes out the need for the system offset calibration phase and significantly improves on the harmonic distortion of the transfer function. Furthermore this method offers the advantage of faster overall response of the system and higher efficiency.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: May 29, 2007
    Assignee: Acutechnology Semiconductor Inc.
    Inventor: Paolo Menegoli
  • Patent number: 7221529
    Abstract: The invention is directed to a magnetic head driving circuit and a magnetic disk device which achieve a low flying-height with thermal protrusion and thus a reliable write operation on the magnetic disk. The write circuit 3 receives the write data signal Sw inputted therein, and generates and outputs the write voltages Wx, Wy based upon the inputted signal. The write voltages Wx, Wy are composed of a preamble portion T1, a sink mark T2 and a user data portion T3 in each sector for magnetic recording. In the write voltage, the frequency f2 of the signal in the preamble portion T1 is higher than half the frequency f1 of the signal in the user data portion T3.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: May 22, 2007
    Assignee: TDK Corporation
    Inventors: Mitsuo Otsuki, Hiroshi Kiyono, Nobutaka Nishio, Hiroki Matsukuma
  • Patent number: 7209304
    Abstract: The thermal decay of data written to a magnetic mass storage medium is determined by measuring and analyzing the time-domain equalized-signal-to-noise ratio (ESNR) and equalized signal-to-total-distortion noise ratio (ESTDR) of written data. In some embodiments, a test track and a reference track are initialized from data. Subsequently, the reference track is re-initialized from the test data, and the time-domain ESNR and/or ESTDR measurements are made of the test track and the reference track, at predetermined time intervals. Later, the time-domain ESNR and ESTDR measurements are analyzed to determine the thermal decay of the data written. In another embodiment of the present invention, the ESNR and/or ESTDR measurements includes reading the data through a non-return-to-zero bus in phases, in which the phases are selected in sequence.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: April 24, 2007
    Assignee: Seagate Technology LLC
    Inventors: Edmun Chian Song Seng, UttHeng Kan
  • Patent number: 7206155
    Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jeremy Kuehlwein, Raymond E. Barnett
  • Patent number: 7184232
    Abstract: An apparatus for driving a write head in response to a data signal includes: (a) a first drive unit coupled with the write head; (b) a second drive unit coupled with the write head; and (c) a control unit coupled with the first and second drive units. The control unit receives the data signal and generates control signals to the first drive and second drive units in response to the data signal. The control signals control the first drive unit to apply a first drive signal to a first write head side in a first signal polarity and control the second drive unit to apply a second drive signal to the a second write head side in a second signal polarity opposite to the first signal polarity when the data signal effects a signal excursion. The first drive signal and the second drive signal are equal in magnitude time coincident.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Motomu Hashizume, Jinguji Naoko, Indumini Ranmuthu, Neel Seshan
  • Patent number: 7161752
    Abstract: An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: January 9, 2007
    Assignee: Marvell International Ltd.
    Inventor: Chi Fung Cheng
  • Patent number: 7154693
    Abstract: A HDD write driver circuit (10) having a boost current overshoot programmed by a plurality of pull-up devices (MP35, MP36, MP39, MP45). The pull-up strength of an inverter (20) is adjustably selected by programming pull-up PMOS devices, and less power is dropped across a resistor (R41) such that there is less boost current overshoot when an overshoot MSB is low.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: John J. Price, Jr.
  • Patent number: 7133234
    Abstract: The present invention discloses an apparatus (160) comprising a common mode generator circuit (162) coupled to a current directing circuit adapted to provide current to a first write head connection node (170) and to a second write head connection node (172).
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Bryan E. Bloodworth, Thomas Cougar Van Eaton
  • Patent number: 7130143
    Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventor: Larry LeeRoy Tretter
  • Patent number: 7126773
    Abstract: A method is presented for precompensation of Non-Linear Transition Shift (NLTS) in magnetic recording media using a perpendicular recording write head. The method includes maintaining a count of non-transition data bits (“zeroes”) preceding a data transition (“one”) to be written. A precompensation value is assigned which correlates to the count of non-transition data bits preceding the data transition to be written. The assigned precompensation value is then applied to delay timing of a write signal sent to the perpendicular recording write head so that the location of the actual written data transition more closely aligns with an ideal location of the data transition to be written.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: October 24, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventor: Alexander Taratorin
  • Patent number: 7123429
    Abstract: A method and apparatus for providing write pre-compensation using a read timing path is disclosed. The present invention generates a first phase clock signal having a first phase and being synchronized with a read signal of a read path, generates a second phase clock signal having a second phase at a predetermined phase difference with the first clock signal and uses the first and second clock signals to shift write data to achieve write data comprising a first desired pre-compensation.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 17, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Firmin M. Musungu, Joey M. Poss, Raymond A. Richetta
  • Patent number: 7123430
    Abstract: A method and apparatus for providing write pre-compensation using a read timing path is disclosed. The present invention generates a first phase clock signal having a first phase and being synchronized with a read signal of a read path, generates a second phase clock signal having a second phase at a predetermined phase difference with the first clock signal and uses the first and second clock signals to shift write data to achieve write data comprising a first desired pre-compensation.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: October 17, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Firmin M. Musungu, Joey M. Poss, Raymond A. Richetta
  • Patent number: 7113359
    Abstract: Disclosed are methods and circuits for impedance-controlled write drivers using matched impedance control circuits coupled in parallel with a magnetic write head.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Motomu Hashizume, Naoko Jinguji
  • Patent number: 7110204
    Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Davy H. Choi
  • Patent number: 7110198
    Abstract: A write driver system comprises a control circuit that includes first switching devices and that generates gate drive signals. A write driver circuit includes second switching devices that are controlled by the gate drive signals from the control circuit. The second switching devices have higher voltage thresholds than the first switching devices. The second switching devices have slower switching times than the first switching devices.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: September 19, 2006
    Assignee: Marvell International Ltd.
    Inventors: Farbod Aram, Pantas Sutardja
  • Patent number: 7095577
    Abstract: A disk drive is disclosed for optimizing write current settings relative to drive operating characteristics and an ambient temperature reading. Test data is written to and read from the disk using different write current settings to generate a plurality of corresponding quality metrics. The quality metrics are evaluated to generate an optimized write current setting for the ambient temperature reading. In one embodiment, the first write current setting is selected relative to a previously optimized write current setting that corresponds to the ambient temperature reading. This embodiment expedites the optimization process by testing write current settings surrounding a previous write current setting rather than testing the entire range of write current settings.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 22, 2006
    Assignee: Western Digital Technologies, Inc.
    Inventors: Raffi Codilian, Iftikhar K. Baqai
  • Patent number: 7095576
    Abstract: A method and apparatus for controlling a write current capable of improving an adjacent track erasure (ATE) property of a hard disk drive. The method for controlling the write current in a hard disk drive includes applying overshoot current and write current to a head to write data on a disk, waiting for a predetermined time to pass, with the predetermined time being determined according to a thermal pole tip protrusion (TPTP) property of the head, and reducing the overshoot current and the write current upon passing of the predetermined time. Accordingly, since the overshoot current and the write current are decreased at the time of the TPTP being saturated, it is possible to effectively improve an ATE property of the hard disk drive.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: August 22, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-yoon Kim, Jae-deog Cho, Seong-hwan Yu, Jin-wan Jun
  • Patent number: 7092186
    Abstract: A disk drive is disclosed which demagnetizes the head after a write operation. Write circuitry applies a write signal to the head in order to write data to a selected data sector during a write operation, wherein the write signal comprises a predetermined write current amplitude. Control circuitry demagnetizes the head at the end of the write operation by maintaining the write current amplitude while increasing a frequency of an AC write signal applied to the head over a predetermined demagnetization interval, wherein increasing the frequency of the AC write signal decreases an amplitude of the AC write signal when observed at the head.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: August 15, 2006
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dennis W. Hogg
  • Patent number: 7092189
    Abstract: A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an impedance matching section of the write driver circuit and can be selectively enabled to correspondingly set the output impedance of the write driver circuit. The amplifiers may be Class AB amplifiers, each of which have a smaller size than an conventional AB used in a single amplifier write driver circuit. Each of the Class AB amplifiers has a corresponding matching resistor, and a current source, each being selectively enabled and disabled by enabling and disabling, respectively, the corresponding current sources, such as through the use of serial interface bits.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: August 15, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Jeremy Robert Kuehlwein
  • Patent number: 7072130
    Abstract: A recording system, such as a magnetic or optical recording system, sets input attenuation level setting and variable gain amplifier (VGA) operating region during zero gain start (ZGS) by sharing the ZGS adjustment between attenuator settings and VGS gain setting. Further adjustment is made to attenuator settings and VGS gain setting for each subsequent servo or read sector event. The input attenuation level setting and variable gain amplifier (VGA) operating region are set so as to minimize effects of gain error due to incorrect attenuator setting, and subsequently operate the VGA near the center of its range where the non-linear effects are minimal.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: July 4, 2006
    Assignee: Agere Systems Inc.
    Inventor: Viswanath Annampedu
  • Patent number: 7068450
    Abstract: A preamplifier device (26) for a thin film transducer disk drive system having operation speeds up to and greater than 2 Gb/s. The device (26) includes a low power/high speed driver (203) having a cascaded Class AB buffer. In at least one embodiment the device (26) includes separated drive devices in the driver (203) and H-bridge circuit (205) realized in multiple smaller devices biased separately to reduce transistor self-heating effects and a further embodiment includes a reference (201) having a base cancellation scheme and a Class AB current source for improving accuracy and stability is such high speed devices.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tuan Van Ngo, Raymond Elijah Barnett
  • Patent number: 7061321
    Abstract: A read amplifier system for connection through interconnects to a magnetoresistive (MR) head includes two input transistors, two bias transistors connected to the two input transistors by common source connections, a bias voltage control circuit connected to base terminals of the two bias transistors, a common mode voltage control circuit connected between first and base terminals of the input transistors to provide feedback from the first terminals to the base terminals, and a compensating circuit connected between the outputs of the amplifier system and the base terminals of the input transistors for providing a feedback from the outputs to the base terminals. The two base terminals of the input transistors are respectively connected to the interconnects of the MR head. The bias voltage control circuit applies a bias voltage to base terminals of the two bias transistors, and through the common sources to the base terminals of the input transistors, and thereby across the MR head.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: June 13, 2006
    Assignee: Guzik Technical Enterprises
    Inventors: Anatoli B. Stein, Serguei Pantchenko