Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.

Abstract: A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

Abstract: A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

Abstract: Systems and techniques relate to current slew control circuits. According to an aspect, a system implementing the quadratic slew control aspects comprises a disk; a read/write head; and a slew control circuit coupled to the read/write head, the slew control circuit configured to: receive an input current signal, apply a slew current to the input current signal in response to a change in a power setting for the read/write head, and provide an output current signal that is adjusted to a quadratic current slew based on the applied slew current, the output current signal generating an output voltage characterized by a linear slew and controlling a movement of the read/write head over the disk.

Abstract: An apparatus, according to one embodiment, includes: a controller having: a first circuit having a reference resistance, a second circuit having an adjustable resistance, and logic integrated with the controller, executable by the controller, or integrated with and executable by the controller to perform the following process: compare output voltages of the first and second circuits, alter the resistance of the second circuit until the output voltage of the first circuit is less than or equal to the output voltage of the second circuit, and extract setting information in response to determining that the output voltage of the first circuit is less than or equal to the output voltage of the second circuit.

Abstract: A multiphase DC voltage converter and a method for controlling a multiphase DC voltage converter, having at least two parallel coils which are controlled in a time-shifted manner, at least one control unit for activating the coils, and at least one magnetically sensitive sensor element for detecting a magnetic field generated by the current flow through the coils. The control unit controls the current flow through the coils as a function of an output signal of the at least one sensor element.

Abstract: A storage controller interface includes, on a disk controller side of the storage controller interface, a first transceiver circuit configured to transfer a first block of user data to a read channel during a write operation, and a gate transmit circuit configured to, subsequent to the first block of user data being transferred, assert a gate signal to flush the first block of user data from the read channel. The storage controller interface further includes, on a read channel side of the storage controller interface, a second transceiver circuit configured to receive the first block of user data, a gate receive circuit configured to receive the gate signal, and a write fault transceiver circuit configured to selectively assert a write fault signal if the gate transmit circuit does not assert the gate signal subsequent to the first block of user data being transferred to the read channel.

Abstract: A disk drive preamplifier integrated circuit. The integrated circuit comprises a differential output driver configured to drive readback data to an output load, wherein the output driver comprises a differential mode filter configured to filter alternating current of an on-chip power supply.

Abstract: An apparatus, according to one embodiment, includes: a controller having: a first circuit having a reference resistance, a second circuit having an adjustable resistance, and logic integrated with and/or executable by the controller, the logic being configured to cause the controller to perform the following process: apply a voltage to the first and second circuits, compare output voltages of the first and second circuits, alter the resistance of the second circuit until the output voltage of the first circuit is less than or equal to the output voltage of the second circuit, extract setting information in response to determining that the first voltage of the first circuit is less than or equal to the second voltage of the second circuit, and apply the extracted setting information to a component of a write driver circuit for setting a resistance value of the component.

Abstract: A method of designing, for a magneto-resistive (MR) sensor, a protection circuit having a first and a second N-channel field-effect transistor (NFET) and at least one positive-negative (PN) diode is disclosed. The method may include determining a safe operating voltage range for the MR sensor and determining, within the safe operating voltage range, a normal operating voltage range for the MR sensor. The method may also include determining a protection threshold voltage range outside of the normal operating voltage range and within the safe operating voltage range of the MR sensor. The method may also include selecting device parameters to configure the first and second NFETs and the at least one PN diode to, in response to a voltage applied to the MR sensor being within a protection threshold voltage range, limit, by shunting current, the voltage applied to the MR sensor.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit.

Abstract: A disk drive read circuit is disclosed comprising a read element for generating a read signal, and a sense amplifier comprising an input terminal coupled through a first capacitor to the read element and an output terminal coupled through a second capacitor to a transmission line, wherein the sense amplifier is for amplifying the read signal.

Abstract: An operational amplifier has an input stage which generates a first input current and a second input current in accordance with a first input signal and a second input signal, an offset adjuster which gives offsets to the first input current and the second input current respectively to generate a first output current and a second output current, an output stage which generates an output signal in accordance with the first output current and the second output current, and an offset current generator which generates a first offset current and a second offset current in accordance with an offset adjustment signal. The offset adjuster gives the offsets to the first input current and the second input current respectively by using the first offset current and the second offset current.

Abstract: A disk drive preamplifier (preamp) includes a write driver that has two pairs of programmable bypass current sources not connected to the write current source to compensate for the inherent magnetic asymmetry of the write head. One pair of the programmable bypass current sources provides a fixed bypass current in one direction. The other pair provides a fixed bypass current in the opposite direction. Prior to writing, only one of the pairs of bypass current sources is selected and programmed with the correct value of bypass current. When the write driver generates the positive and negative write current pulses during writing the selected bypass current sources provide a fixed offset to the amplitude of the write current pulses.

Abstract: A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.

Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Abstract: An integrated circuit (IC) includes a programmable gain amplifier. The programmable gain amplifier comprises a first-stage amplifier configured to operate with at least one relatively high power supply voltage in order to accommodate at the input of the first-stage amplifier a relatively large range of input signals, the first-stage amplifier having a gain setting that is adjustable from a set of predetermined gain settings separated in relatively coarse increments so as to minimize the number of analog switches that must be implemented with high-voltage active devices in order to set each gain setting.

Abstract: Individual magneto-resistive read elements are connected to the pre-amplifier through a multi-conductor transmission line; one side of each magneto-resistive read element is taken to a single common lead which is also received in the read pre-amplifier. Amplification and bias control are performed by the read pre-amplifier. A low-noise input stage amplifier configuration accommodates a shared common lead in a multi-head environment. Means for independently biasing the magneto-resistive read elements are also provided. Feedback loops are employed to regulate the operating points of the input stages, and to set the potential of the common head terminal. Two-dimensional magnetic recording system testability is enhanced by ability to multiplex any head to a single system output.

Abstract: Disk drive embodiments with common lead connections in the slider, suspension, and preamplifier are described. The arm electronics IC includes a preamplifier with single-ended input from the set of signal traces that include a common signal return lead for the plurality of read transducers (readers) in the slider. Two embodiments of the preamps are described that include a single-ended design and a pseudo-single-ended design. Each embodiment supplies the required bias to each read transducer using an operational transconductance amplifier (OTA) that drives a variable current source connected to the transducer. The positive input to the OTA is a DC voltage with the AC signal from the transducer imposed on it. The negative input is a DC reference voltage. Various embodiments of the signal trace configuration on the suspension are described including a single and double layer embodiments.

Abstract: A class-AB amplifier has upper side and lower side transistors, a linear driver, upper side and lower side idlers, upper side and lower side detection current generators, and an off driver. The upper side and lower side idlers bias upper side and lower side gate voltages by generating upper side and lower side bias currents so as to turn on the upper side and the lower side transistors at the same time in the crossover region between an input voltage and a reference voltage respectively. The upper side detection current generator and the lower side detection current generator generates upper side and lower side detection currents in accordance with upper side and lower side bias currents respectively.

Abstract: A switching regulator has an output stage which, with an output switch element, an inductor, a rectifying element, and a smoothing element, generates an output voltage from an input voltage, a divided voltage generator which generates a divided voltage from a switch voltage generated at one terminal of the rectifying element, a selector which outputs one of the divided voltage and a fixed voltage in accordance with a switching signal as a select voltage, a zero-cross comparator which monitors the select voltage to generate a zero-cross detection signal, and a controller which generates the switching signal in accordance with the necessity of monitoring the zero-cross of an inductor current and which performs on/off control of the output switch element reflecting the zero-cross detection signal.

Abstract: A system including a first transmission line, a second transmission line, a first element, a second element and a differential amplifier. The first element is configured to read a storage media to generate a read signal, where the first element is connected to the first transmission line. The second element is configured to detect interference and generate an interference signal, where the second element is connected to the second transmission line. The differential amplifier includes a first input and a second input, where the first input of the differential amplifier is connected to a the first transmission line and receives the read signal, and where the second input of the differential amplifier is connected to the second transmission line and receives the interference signal.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission. In one case, a data processing system is disclosed that includes: a two stage tone reduction circuit including a first stage circuit and a second stage circuit; and a polarity change circuit operable to change a polarity of the second stage output to yield a tone reduction output.

Abstract: Interface circuitry of a storage device or other type of processing device comprises a digital input detector and an adaptive power supply. The digital input detector comprises an input transistor. The adaptive power supply provides a variable supply voltage to the digital input detector that varies with a threshold voltage of the input transistor. In one embodiment, the variable supply voltage provided to the digital input detector by the adaptive power supply varies with the threshold voltage of the input transistor about a set point value determined as a function of an expected logic level of an input signal. For example, the set point value may be determined as a function of a minimum expected logic high input signal level. In such an arrangement, the input transistor is biased at or close to the threshold voltage for an input signal having the minimum expected logic high input signal level.

Abstract: A data signal comprising an even component and an odd component with differing amplitudes is received at a main automatic gain controller (AGC). The even component is adjusted by a first interleaved AGC and the odd component is adjusted by a second interleaved AGC such that even and odd component amplitudes are substantially equal. Amplitude adjusted even and odd components are recombined to define a data signal with components having substantially equal amplitudes. The even and odd components can be generated by a read transducer moving relative to a magnetic storage medium comprising tracks defined by discrete and spaced-apart recording bits arranged in an interspersed pattern. A read channel separates the data signal into even and odd samples such that a gain can be independently adjusted for each of the even and odd samples to compensate for asymmetry between the even and odd samples.

Abstract: First and second read sensors are coupled in series to a preamplifier via respective first and second signal lines and a common signal line between the first and second read sensors. Independent first and second currents are supplied to the respective first and second read sensors. The first and second currents are varied to maintain respective first and second fixed bias values (e.g., fixed voltage or fixed current) on the first and second read sensors.

Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.

Abstract: Disk drives with sliders including with an impedance compensation network in the signal path for the read sensor are described. The read signal bandwidth at the preamplifier is improved by the impedance compensation network to allow signals in the multi-GHz range from spin torque oscillators as well as tunnel magnetoresistance (TMR) sensors to be used. An embodiment of the invention achieves a signal layout balance by constructing two inductor-capacitor pair structures on the trailing edge of the slider that are integrated into the differential read signal traces. The differential balanced structure helps to suppress external signal interference pick-up from transferring from common-mode pick-up to differential mode.

Abstract: A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises degauss circuitry coupled to or otherwise associated with one or more write drivers. The degauss circuitry is configured to generate an asymmetric degauss signal to be applied to the write head. The asymmetric degauss signal has a waveform with upper and lower decay envelopes that are asymmetric about a specified degauss current level, such as a substantially zero current level.

Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.

Abstract: Aspects of the disclosure pertain to a system and method for providing zero gain start (ZGS) and gain acquisition based on an adaptive analog-to-digital converter (ADC) target. The adaptive ADC target is used to collect channel characteristics and based on the adaptive ADC target, an adjusted 2T amplitude target value is generated.

Abstract: Systems and methods for improving accuracy of head positioning using existing servo patterns are provided. In one embodiment, a method for improving read head positioning is provided that comprises: writing a series of tracks over a range of read offsets to be calibrated; measuring a set of raw track profiles from the series of tracks; sampling the set of raw track profiles at a series of signal amplitude levels; constructing a reference track profile from the set of sampled track profiles; calculating a set of read offset deltas from each sampled track profile; merging the sets of read offset deltas into a set of average read offset deltas; and converting the set of average read offset deltas into a read offset correction table. A similar method for improving disk write head positioning is also provided which utilizes such a read offset correction table to eventually create write offset correction table.

Abstract: Embedded contact sensor controls for use in arm electronics (AE) in a disk drive are described that provide for removing undesirable offsets between the measured voltage across the ECS resistor in the slider and the balance resistor in ECS amplifier in the arm electronics (AE), which allows increased amplification of the resulting adjusted signal without saturation. Embodiments include a Zero-Offset Circuit, which can be activated periodically or on demand to sample and hold the present DC offset voltage in the ECS amplifier signal and subtract the DC offset voltage from ECS amplifier signal. The adjusted signal can then be further amplified without saturation.

Abstract: A write driver circuit for generating a write current pulse for use by a magnetic write head includes an output stage adapted for connection with the magnetic write head and a charge storage circuit connected with the output stage. The charge storage circuit is operative in a first mode to store a prescribed charge and is operative in a second mode to transfer at least a portion of the charge stored therein to the output stage to thereby enable an output voltage level of the output stage to extend beyond a voltage supply rail of the write driver circuit. A control circuit in the write driver circuit is operative to generate at least one control signal for selectively controlling a mode of operation of the charge storage circuit.

Abstract: A balanced amplifier with a relatively high input impedance with wide bandwidth for use as a fly-height sensor head preamplifier in a magnetic storage read system. The balanced amplifier has two substantially identical halves, each amplifier half having an input transistor, responsive to the input node of the amplifier half disposed in series with a cross-coupling transistor receiving a buffered cross-coupled version of the input signal applied to the other half of the balanced amplifier. Use of cascoded transistors and voltage-followers to limit voltages across various the input and cross-coupling transistors enhance the common mode rejection and power supply rejection ratios of the amplifier while retaining a low high-frequency noise figure similar to low-input impedance balanced amplifier designs.

Abstract: In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Abstract: A magnetic storage system includes a read and write device that (i) magnetically writes data on a platter, and (ii) reads, via a read element, the data written magnetically on the platter. The read element includes a first terminal and a second terminal. A transistor includes a gate. The transistor is closed responsive to the gate not receiving power. Responsive to the gate of the transistor receiving power, the transistor provides an open circuit between the first terminal and the second terminal. Responsive to the gate of the transistor not receiving power, the transistor shorts the first terminal to the second terminal. A first limiting circuit limits a first voltage of (i) the transistor and (ii) the first terminal. A second limiting circuit limits a second voltage of (i) the transistor and (ii) the second terminal.

Abstract: In various embodiments, systems and methods to detect signal irregularity caused by defects in the read/write head element are disclosed. In some embodiments, an exemplary system comprises a memory and a processor. The processor is coupled to the memory and is configured to implement a filter module and a detector module. The filter module is configured to generate a test waveform based on data read from a medium by a storage device head to be tested. The detector module is configured to generate a signal quality value based on a property of at least a portion of the test waveform, compare the signal quality value to an event threshold, and generate an event indicator based on the comparison, the event indicator indicating possible instability of the storage device head.

Abstract: Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a biasing circuit and an amplifier. The biasing circuit is configured to generate a bias voltage and a bias current based on a first resistor having a first resistance determined based on a second resistor. The amplifier is biased based on the bias voltage and bias current to generate an electrical signal that varies in response to a resistance change of the second resistor.

Abstract: A hard disk drive or other storage device comprises a storage medium, a read head configured to read data from the storage medium, and control circuitry coupled to the read head and configured to process data received from the read head. The control circuitry comprises read channel circuitry that includes a low-density parity check decoder or other type of decoder. Power management circuitry associated with the read channel circuitry is configured to detect a power control condition of the read channel circuitry and to control insertion of idle clock cycles in a clock signal supplied to the decoder responsive to the detected power control condition. For example, the read channel circuitry may comprise a clock generator configured to gate the clock signal responsive to a control signal from the power management circuitry.

Abstract: Disk drives with preamp rotational parameter control (RPC) using standard digital serial interface lines to the preamp are described. The standard serial interface lines are used to generate a special signal pattern that does not follow the serial communication protocol. The special signal pattern is used to implement RPC when doing so will not interference with other signals, preferably in the read/write recovery gap between the data and the servo field in a standard track format. A value of a selected preamp parameter can be incremented or decremented by one LSB during the read/write gap time in each servo sector as the disk rotates. Embodiments of the invention allow fly-height and write driver parameters to be varied inside of a single disk revolution. Embodiments are described that include two or four parameters in the set, which allows for multiple updates of each parameter per revolution of the disk.

Abstract: A voltage booster is disclosed comprising an input for receiving an input voltage Vin, a first charging capacitor C1, a second charging capacitor C2, and an output capacitor Cout. The output capacitor Cout is charged to four times Vin by connecting C1 in parallel with Vin to charge C1 to Vin, after charging C1 to Vin, connecting C2 in parallel with Vin plus C1 to charge C2 to twice Vin, after charging C2 to twice Vin, connecting C1 in parallel with Vin to recharge C1 to Vin, and after recharging C1, connecting Cout in parallel with Vin plus C1 plus C2 to charge Cout to four times Vin.

Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: A system and method for monitoring fly height between a magnetic recording medium and a transducing head. In a first exemplary embodiment, magnetic spacing change value is calculated using media noise on the recording medium (instead of prerecorded tones) to provide a broadband frequency distribution that results in improved Wallace equation accuracy. In a second exemplary embodiment, a magnetic spacing change value is acquired by any suitable method but is adjusted as necessary to reflect transducing head wear, thus providing a methodology for calculating changes in fly height by taking into account the signal loss that is attributable to wear. In this way, a basic understanding of the mechanism causing changes in magnetic spacing is achieved.

Abstract: Systems and/or methods for measuring latency in an electronic device such as, e.g., a storage device, may include coupling circuitry configured to capacitively couple an outbound or write data path to an inbound or read data path. A latency measurement signal may be driven on the write data path, the coupling circuitry may transmit at least a portion of the latency measurement signal from the write data path to the read data path, and the latency measurement signal may be sensed on the read data path to be used to determine communication path latency in the device.

Abstract: Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and providing an input to AB drivers of the output stage, in which an offset test circuit selectively drives the high pass filter output nodes according to the offset at the filter input to facilitate measurement of the preceding circuit offset at the driver output terminals, and a common mode regulator circuit regulates common mode voltages at the first and second driver output nodes to a predetermined value in read and write modes.

Abstract: A method for calibrating a reflection compensator is provided. A delay is initially set to a predetermined minimum, and an input pulse is transmitted across a transmission line. A compensation current is then applied after the delay. The reflection from the transmission line is digitized to generate a measurement, and a determination is made as to whether the compensation current substantially compensates for the reflection. If the compensation current does not substantially compensate for the reflection, then the delay is adjusted, and the process is repeated until the compensation current substantially compensates for the reflection.