Abstract: The present disclosure relates to a power distribution unit (PDU) having at least one power receptacle for enabling attachment of an AC power cord of an external device thereto. A branch receptacle controller (BRC) has at least one bistable relay and is associated with the one power receptacle for supplying AC power thereto from an AC power source. The BRC monitors a voltage of an external power source and uses it to detect when AC power is lost, and then toggles the bistable relay, if the relay is in a closed position, to an open position.

Abstract: A power tool has a housing, a motor disposed within the housing, a power supply circuit for providing power to the motor, a controller circuit for controlling the power provided to the motor, and an electric static discharge (ESD) protection circuit connected to the power supply circuit and the housing. The ESD protection circuit includes a first resistor connected to the power supply circuit and the housing. The first resistor may be a high impedance resistor. The ESD protection circuit may also have a first capacitor connected in parallel to the first resistor, a second resistor connected in series to the first resistor, and a second capacitor connected in series to the first capacitor and in parallel to the second resistor.

Abstract: A protective device for a trip circuit for a personal protection device for a vehicle, the trip circuit having an ignition device, a high-side end stage, and a low-side end stage. The protective device has a high-side interface for contacting the protective device to a high-side terminal and a low-side interface for contacting the protective device to a low-side terminal of the ignition device, a suppressor diode that is connected between the high-side interface and a second voltage potential; and at least one first diode that is connected between the low-side interface and the second voltage potential.

Abstract: A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.

Abstract: Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Abstract: An apparatus and method for controlling voltage sharing between a set of switching components can include applying power from a current source with a positive lead and a negative lead, closing the set of switching components to connect power from the current source to an electrical load, detecting a set of voltage values for the set of switching components, and controlling a current limiting function of at least one of the set of switching components.

Abstract: A circuit includes electrostatic discharge (ESD) protection circuitry, triggering circuitry, transient detection circuitry, and deactivation circuitry. The ESD protection circuitry is coupled between a first rail and a second rail. The triggering circuitry is configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold. The ESD protection circuitry is configured to activate based on the ESD activation signal. The transient detection circuitry is configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold. The deactivation circuitry is configured to deactivate the triggering circuitry based on the deactivation signal.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.

Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.

Abstract: A variable level power clamping circuit that may be used for the bypass path of an RF receiver having a low-noise amplifier (LNA). Impedance transform circuitry is used to transform the impedance of a signal path to a higher or lower impedance at a clamping circuit, causing the voltage at the clamping circuit to be, respectively, higher (thus clamping at a lower power level) or lower (thus clamping at a higher power level), and then transform the impedance after the clamping circuit to another value, such as to the impedance of the signal path. In a variant embodiment, the clamping circuit and an impedance matching element coupled to an LNA amplification path are re-purposed by selectively connecting those circuit elements to the LNA bypass path through a suitable impedance transform element when in a bypass mode.

Abstract: A multi-channel transient voltage suppressor with ultra-low capacitance is provided, which comprises a plurality of diode strings coupled between an ESD bus line and ground, having each diode string coupled to an I/O pin; a power clamp circuit coupled to the ESD bus line; and a first diode having an anode coupled to the power clamp circuit and a cathode coupled to ground. A second diode may be alternatively disposed between the first diode and the diode strings, having an anode coupled to the ground and a cathode coupled to a common anode of the diode strings. By employing the proposed present invention, it is advantageous of reaching an ultra-low capacitance and meanwhile still maintaining a lower layout area of the circuit structure.

Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node.

Abstract: An amplification device includes an amplification circuit and a protection circuit. The amplification circuit includes a transistor having a first terminal for outputting an amplified radio frequency signal, a second terminal, and a control terminal coupled to the input terminal of the amplification circuit for receiving a radio frequency signal to be amplified. The protection circuit has a first terminal coupled to the output terminal or the input terminal of the amplification circuit, and a second terminal. The protection circuit includes a switch and a first voltage clamping unit. The switch unit is turned on or turned off according to a control signal. The first voltage clamping unit is coupled to the switch unit for clamping a voltage at the first terminal of the protection circuit within a predetermined region when the switch unit is turned on.

Abstract: One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.

Abstract: A shunt resistor having sufficient bonding strength includes a resistor, a pair of bases which are integrally formed with the resistor so as to sandwich the resistor, recessed holes which are respectively formed in the bases, and measurement terminals which are inserted into the recessed holes and are affixed to the bases. Each measurement terminal has a shaft part and a flange part that protrudes outwardly in the circumferential direction of the shaft part. Each recessed hole is formed to have a diameter smaller than the diameter of the flange part, and the shaft parts are respectively inserted into the recessed holes.

Abstract: A touch panel includes two ground wires. One end portion (an end portion X1) of one of the two ground wires and one end portion (an end portion Y1) of the other of the two ground wires form a gap. When the touch panel is viewed from front, the following condition as an example is satisfied: a line segment Z1 intersects at least one of the two ground wires. The line segment Z1 is a line segment which connects any one point P1 on a first line segment and any one point Q1 on a second line segment, the first line segment connecting a site of the end portion X1 and a site of the end portion Y1 which are located on two sides of an outer gate of the gap, the second line segment connecting a site of the end portion X1 and a site of the end portion Y1.

Abstract: An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

Abstract: An ESD protection circuit includes a detection circuit for detecting an ESD event. The detection circuit includes two current mirrors each for providing two detection signals. The ESD protection circuit includes driver circuitry that produces trigger signals to clamp circuits that make conductive the clamp circuits in response to an ESD event based on the detection signals from the current mirrors.

Abstract: Aspects of this disclosure relate to a cascaded filter circuit that includes a hybrid acoustic LC filter, a non-acoustic LC filter, and a switch configured to selectively couple the hybrid acoustic LC filter and the non-acoustic LC filter. The hybrid acoustic filter can filter a radio frequency signal. The hybrid acoustic LC filter can include an acoustic resonator, an inductor, and a capacitor. The non-acoustic LC filter includes an LC circuit. Related multiplexers, wireless communication devices, and methods are disclosed.

Abstract: The present disclosure discloses an electrostatic protection method, an electrostatic protection apparatus and a liquid crystal display. The electrostatic protection method includes: monitoring an interface signal of a timing control circuit and/or a level conversion circuit to determine whether the monitored signal is subjected to electrostatic interference; and when the electrostatic interference is detected, adjusting a timing control signal output by the timing control circuit to a gate driving circuit of an array substrate, wherein the level conversion circuit connects the timing control circuit to the gate driving circuit of the array substrate, and is configured to perform level conversion on an output signal output by the timing control circuit to the gate driving circuit of the array substrate.

Abstract: Disclosed herein is a hold checking method for checking whether or not a wafer is held by an electrostatic chuck in loading the wafer to the electrostatic chuck by operating a transfer unit holding the wafer. The hold checking method includes a connecting step of bringing the wafer held by a transfer pad into contact with the electrostatic chuck to thereby connect the transfer pad through the wafer to the electrostatic chuck, and a hold determining step of supplying electric power from a DC power source through first wiring to the electrostatic chuck after performing the connecting step, and next determining that the wafer is held by the electrostatic chuck when the voltage across a resistor inserted in the first wiring has reached a predetermined voltage value.

Abstract: Disclosed herein are embodiments of a scalable connection and disconnection differential surge limiter circuit that may be utilized in any AC-coupled transceiver. Charge is recycled between PADP and PADN using two diode paths, hence protecting the PAD connected devices from voltage stress. The circuit can act as a protection circuit to limit the voltage on PADP and PADN during differential voltage spikes.

Abstract: The present disclosure relates to electrostatic protection terminals. One example terminal includes a target interface, a protected circuit, a protection unit, a switch unit, and a switch control unit. The protected circuit is configured to suppress an electrostatic discharge (ESD) current or an electrical overstress (EOS) current. A first end of the protection unit is electrically connected to a first pin of the target interface. A second end of the protection unit is electrically connected to a second pin of the protected circuit. The first pin is any pin of the target interface. The second pin is a pin that is in the protected circuit and that needs to be electrically connected to the first pin. The switch unit is connected to the protection unit in parallel. The switch control unit is configured to control the switch unit to be open or closed.

Abstract: An electrostatic discharge protection device includes a voltage divider, a resistor, a capacitor, a first primary transistor, a second primary transistor, a first control circuit, and a second control circuit. The voltage divider is coupled between a first system terminal and a second system terminal for providing a voltage. The resistor is coupled to the first system terminal, and the capacitor is coupled to the resistor. The first primary transistor and the second primary transistor are coupled in series between the first system terminal and the second system terminal. The first control circuit turns on the first primary transistor when an electrostatic discharge event occurs according to voltages provided by the voltage divider and the resistor. The second control circuit turns on the second primary transistor when the electrostatic discharge event occurs according to voltages provided by the voltage divider and the first control circuit.

Abstract: A filter that includes a series circuit of a first Zener diode and a second Zener diode, a third Zener diode connected between a node and ground, and a third inductor. A first series resonant circuit is formed by a parasitic capacitance of the first Zener diode, a parasitic capacitance of the third Zener diode, and the third inductor, and a second series resonant circuit is formed by a parasitic capacitance of the second Zener diode, the parasitic capacitance of the third Zener diode, and the third inductor. Moreover, the parasitic capacitances of the first Zener diode and the second Zener diode are substantially equal, and the parasitic capacitance of the third Zener diode is larger than the parasitic capacitance of each of the first Zener diode and the second Zener diode.

Abstract: A power supply package is disclosed, including a power management integrated circuit (PMIC) die with a plurality of switching circuits, and a plurality of integrated 3-dimensional (3D) inductors disposed around the PMIC die. Each 3D inductor corresponds to a switching circuit and is electrically coupled to first and second connections for the corresponding switching circuit. An integrated electromagnetic interference (EMI) shield is disposed between the PMIC and the 3D inductors.

Abstract: A circuit including a discharging device, a resistive element and a bypass device is disclosed. The discharging device is disposed between a first voltage bus and a second voltage bus. The resistive element is configured to activate the discharging device in response to a high-to-low electrostatic discharge (ESD) event during which the first voltage bus is high in potential relative to the second voltage bus. The bypass device is configured to bypass the resistive element and activate the discharging device in response to a low-to-high ESD event during which the second voltage bus is high in potential relative to the first voltage bus.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.

Abstract: An electrostatic painting device capable of reducing any AC or electromagnetic emissions when the device is powered on is provided. The emissions affect electronic components present during painting of various objects or even when the device is powered on. The electromagnetic induction into the conductive circuit elements in turn induces voltages and currents, which potentially harm the micro-electronic circuits. One such device includes a choke between a fluid tip and a high voltage source of the device to reduce these emissions. The voltage source may include at least one capacitor which supplies the AC emissions representing electromagnetic emissions risk during the discharge of paint from the device. The choke connected to the voltage source substantially reduces the emissions involved during the paint discharge, while allowing the discharge of electrons, thereby imparting negative DC charge to the paint and the workpiece, and preventing damage to electronic circuits during the process.

Abstract: In one example, an electrostatic discharge (ESD) protection circuit includes a first power supply having a first supply voltage, wherein the first power supply is connected to a first node. The ESD protection circuit also includes a second power supply having a second supply voltage, wherein the second power supply is connected to the first node. The ESD protection circuit also includes an inverter that receives an input voltage from the first node and produces an output voltage. An ESD discharge device receives the output voltage and provides a discharge path for the first power supply and the second power supply if the output voltage indicates occurrence of an ESD event affecting the first power supply or the second power supply.

Abstract: A surge protective circuit is connected between a single-phase AC power source and an apparatus that operates with electric power supplied from the AC power source to suppress an overvoltage applied from the AC power source to the apparatus. The surge protective circuit includes: a first constant-voltage device and a first discharge device connected in series between a first ground terminal and a non-ground-side terminal of the AC power source; and a second constant-voltage device and a second discharge device connected in series between a second ground terminal and a ground-side terminal of the AC power source. A midpoint between the first constant-voltage device and the first discharge device and a midpoint between the second constant-voltage device and the second discharge device are connected.

Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit).

Abstract: This disclosure relates to a storage device having a small form factor. The storage device can include a circuit board configured to store data. The circuit board can be enclosed in a housing. The storage device can include a connector mounted perpendicularly to an inner surface of the circuit board and extending through an aperture of an inner surface of the housing. The connector may be configured to electrically connect to an electronic device to transfer data between the storage device and the electronic device. The connector may be a universal serial bus (USB) Type-C connector. The storage device may have a thickness, measured between the inner surface of the housing and an outer surface of the housing, that does not exceed 6 millimeters (mm), for example.

Abstract: An electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.

Abstract: An isolated switched capacitor converter can include: first switches coupled in series between terminals of an input port, and being configured to selectively connect a first terminal of a first capacitor to a first or second terminal of the input port; second switches coupled in series between terminals of an output port, and being configured to selectively connect a second terminal of the first capacitor to a first or second terminal of the output port; third switches coupled in series between terminals of the input port, and being configured to selectively connect a first terminal of a second capacitor to the first or second terminal of the input port; and fourth switches coupled in series between terminals of the output port, and being configured to selectively connect a second terminal of the second capacitor to the first or second terminal of the output port.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An ESD power clamp circuit includes first, second and third timing networks, first and second NMOS transistors and an enable circuit. The first timing network has a first time constant and detects a voltage transient between first and second voltage supply nodes having a rise time less than the first time constant. The first NMOS transistor has a gate connected with an output of the first timing network and a source connected with a gate of the second NMOS transistor. The second NMOS transistor has a drain connected with the first voltage supply node and a source connected with the second voltage supply node. The second timing network is coupled with the gate of the second NMOS transistor and has a second time constant that is greater than a duration of an ESD event. The third timing network is coupled with the enable circuit and has a third time constant, the third timing network generating a first control signal based on the third time constant.

Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

Abstract: A chip protection circuit applied to a chip. The chip protection circuit comprises a transformer circuit, a first protection circuit and a second protection circuit. The transformer circuit has a first side and a second side. Each of the first side and the second side is disposed with first terminals, second terminals and center tap terminals. Three center tap terminal is coupled to a ground. The first protection circuit comprises a diode having a terminal coupled to the center tap terminal at the first side and another terminal coupled to the ground. The second protection circuit comprises input terminals and output terminals. The input terminals of the second protection circuit are coupled to the first terminal and the second terminals at the second side. The output terminals of the second protection circuit are coupled to the chip.

Abstract: A load switch integrated circuit and an electronic device are provided. In a case that a surge voltage is applied to an input of the load switch integrated circuit, a surge detection circuit controls a first discharging unit to be switched on to discharge surge energy from an input of the load switch integrated circuit to the ground, and controls a first switch transistor and a second discharging unit to be switched on through a control circuit to discharge surge energy to an output of the load switch integrated circuit to the ground. Compared with a case that surge energy is discharged only by a surge protection circuit in the conventional technology, surge energy is discharged via two paths, and a circuit area is smaller than that in the conventional technology in a case that there is large surge energy to be resisted.

Abstract: An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control unit, a first electrostatic storage unit configured to store charges, and a second electrostatic storage unit configured to store charges, wherein the first electrostatic storage unit has a first terminal connected to a driving line and a second terminal connected to the switch control unit, and the second electrostatic storage unit has a first terminal connected to the switch control unit and a second terminal connected to a common electrode trace.

Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: A complex electronic component includes a body including a first external electrode and a second external electrode, disposed on an external surface thereof and a laminate; a plurality of first electrodes and a plurality of second electrodes, disposed in the laminate and electrically connected to the first external electrode and the second external electrode, respectively; a third electrode and a fourth electrode, disposed on the laminate to be spaced apart from each other and electrically connected to the first external electrode and the second external electrode, respectively; and an ESD discharge layer disposed between the third electrode and the fourth electrode. In addition, a distance between the third electrode and the fourth electrode is within a range of 30 ?m to 60 ?m.

Abstract: In an Intrinsically Safe (IS) PoDL/PoE system, a PHY in power sourcing equipment (PSE) has its differential transmit terminals coupled across a primary winding of an isolation transformer. One secondary winding is coupled between a positive terminal of a DC voltage source and a first wire of a twisted wire pair. Another secondary winding is coupled between a negative terminal (e.g., ground) of the DC voltage source and a second wire of the twisted wire pair. The secondary windings provide differential data signals output from the PHY's transceiver to the wire pair, while the DC voltage from the DC voltage source is coupled to the wire pair via the two secondary windings. The DC power is applied to a remote power device having a PHY that communicates with the PSE PHY. Therefore, the secondary windings have the dual purpose of DC-coupling and magnetically coupling the differential data to/from the PHY.

Abstract: The present invention relates to an overvoltage protection circuit (1) for protecting the electronics of a motor, in particular of an EC motor, against overvoltage pulses, with two protective devices (FS1, FS2) arranged in series connection between two connections (10, 20), wherein a resistor (R1) or (R2) is connected in parallel to each of the protective devices (FS1, FS2) and at least one capacitive element (C1) is provided in parallel connection to the first protective device (FS1), wherein the overvoltage protection circuit (1) has, between the connections (10, 20), at least a first (lower) and a second (higher) breakdown voltage point at a voltage UZ1 or UZ2 dependent on the voltage change over time k=(dU/dt) of a voltage UGA at the connections (10, 20).

Abstract: The present application discloses a display panel and a display apparatus.