Abstract: The present disclosure relates to electrostatic protection terminals. One example terminal includes a target interface, a protected circuit, a protection unit, a switch unit, and a switch control unit. The protected circuit is configured to suppress an electrostatic discharge (ESD) current or an electrical overstress (EOS) current. A first end of the protection unit is electrically connected to a first pin of the target interface. A second end of the protection unit is electrically connected to a second pin of the protected circuit. The first pin is any pin of the target interface. The second pin is a pin that is in the protected circuit and that needs to be electrically connected to the first pin. The switch unit is connected to the protection unit in parallel. The switch control unit is configured to control the switch unit to be open or closed.

Abstract: Disclosed herein are embodiments of a scalable connection and disconnection differential surge limiter circuit that may be utilized in any AC-coupled transceiver. Charge is recycled between PADP and PADN using two diode paths, hence protecting the PAD connected devices from voltage stress. The circuit can act as a protection circuit to limit the voltage on PADP and PADN during differential voltage spikes.

Abstract: A filter that includes a series circuit of a first Zener diode and a second Zener diode, a third Zener diode connected between a node and ground, and a third inductor. A first series resonant circuit is formed by a parasitic capacitance of the first Zener diode, a parasitic capacitance of the third Zener diode, and the third inductor, and a second series resonant circuit is formed by a parasitic capacitance of the second Zener diode, the parasitic capacitance of the third Zener diode, and the third inductor. Moreover, the parasitic capacitances of the first Zener diode and the second Zener diode are substantially equal, and the parasitic capacitance of the third Zener diode is larger than the parasitic capacitance of each of the first Zener diode and the second Zener diode.

Abstract: An electrostatic discharge protection device includes a voltage divider, a resistor, a capacitor, a first primary transistor, a second primary transistor, a first control circuit, and a second control circuit. The voltage divider is coupled between a first system terminal and a second system terminal for providing a voltage. The resistor is coupled to the first system terminal, and the capacitor is coupled to the resistor. The first primary transistor and the second primary transistor are coupled in series between the first system terminal and the second system terminal. The first control circuit turns on the first primary transistor when an electrostatic discharge event occurs according to voltages provided by the voltage divider and the resistor. The second control circuit turns on the second primary transistor when the electrostatic discharge event occurs according to voltages provided by the voltage divider and the first control circuit.

Abstract: A circuit including a discharging device, a resistive element and a bypass device is disclosed. The discharging device is disposed between a first voltage bus and a second voltage bus. The resistive element is configured to activate the discharging device in response to a high-to-low electrostatic discharge (ESD) event during which the first voltage bus is high in potential relative to the second voltage bus. The bypass device is configured to bypass the resistive element and activate the discharging device in response to a low-to-high ESD event during which the second voltage bus is high in potential relative to the first voltage bus.

Abstract: A power supply package is disclosed, including a power management integrated circuit (PMIC) die with a plurality of switching circuits, and a plurality of integrated 3-dimensional (3D) inductors disposed around the PMIC die. Each 3D inductor corresponds to a switching circuit and is electrically coupled to first and second connections for the corresponding switching circuit. An integrated electromagnetic interference (EMI) shield is disposed between the PMIC and the 3D inductors.

Abstract: A semiconductor system includes a control device, and a semiconductor apparatus coupled with the control device through a first line and a second line. A loading of the second line is greater than a loading of the first line, wherein the semiconductor apparatus includes a first receiving circuit which is electrically coupled with the first line and a second receiving circuit which is electrically coupled with the second line. Further a loading between the first line and the first receiving circuit is greater than a loading between the second line and the second receiving circuit.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: An electrostatic painting device capable of reducing any AC or electromagnetic emissions when the device is powered on is provided. The emissions affect electronic components present during painting of various objects or even when the device is powered on. The electromagnetic induction into the conductive circuit elements in turn induces voltages and currents, which potentially harm the micro-electronic circuits. One such device includes a choke between a fluid tip and a high voltage source of the device to reduce these emissions. The voltage source may include at least one capacitor which supplies the AC emissions representing electromagnetic emissions risk during the discharge of paint from the device. The choke connected to the voltage source substantially reduces the emissions involved during the paint discharge, while allowing the discharge of electrons, thereby imparting negative DC charge to the paint and the workpiece, and preventing damage to electronic circuits during the process.

Abstract: In one example, an electrostatic discharge (ESD) protection circuit includes a first power supply having a first supply voltage, wherein the first power supply is connected to a first node. The ESD protection circuit also includes a second power supply having a second supply voltage, wherein the second power supply is connected to the first node. The ESD protection circuit also includes an inverter that receives an input voltage from the first node and produces an output voltage. An ESD discharge device receives the output voltage and provides a discharge path for the first power supply and the second power supply if the output voltage indicates occurrence of an ESD event affecting the first power supply or the second power supply.

Abstract: A surge protective circuit is connected between a single-phase AC power source and an apparatus that operates with electric power supplied from the AC power source to suppress an overvoltage applied from the AC power source to the apparatus. The surge protective circuit includes: a first constant-voltage device and a first discharge device connected in series between a first ground terminal and a non-ground-side terminal of the AC power source; and a second constant-voltage device and a second discharge device connected in series between a second ground terminal and a ground-side terminal of the AC power source. A midpoint between the first constant-voltage device and the first discharge device and a midpoint between the second constant-voltage device and the second discharge device are connected.

Abstract: Various approaches of adjusting a gain of received signals in integrated circuitry include implementing an open-loop source-degenerated amplifier having a pair of input devices for amplifying the received signals; boosting an effective transconductance of the input devices (e.g., using a pair of super-gm feedback loops); and setting a bias current of devices in the open-loop source-degenerated amplifier (e.g., using a constant-gm bias circuit).

Abstract: This disclosure relates to a storage device having a small form factor. The storage device can include a circuit board configured to store data. The circuit board can be enclosed in a housing. The storage device can include a connector mounted perpendicularly to an inner surface of the circuit board and extending through an aperture of an inner surface of the housing. The connector may be configured to electrically connect to an electronic device to transfer data between the storage device and the electronic device. The connector may be a universal serial bus (USB) Type-C connector. The storage device may have a thickness, measured between the inner surface of the housing and an outer surface of the housing, that does not exceed 6 millimeters (mm), for example.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: An isolated switched capacitor converter can include: first switches coupled in series between terminals of an input port, and being configured to selectively connect a first terminal of a first capacitor to a first or second terminal of the input port; second switches coupled in series between terminals of an output port, and being configured to selectively connect a second terminal of the first capacitor to a first or second terminal of the output port; third switches coupled in series between terminals of the input port, and being configured to selectively connect a first terminal of a second capacitor to the first or second terminal of the input port; and fourth switches coupled in series between terminals of the output port, and being configured to selectively connect a second terminal of the second capacitor to the first or second terminal of the output port.

Abstract: An electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.

Abstract: An ESD power clamp circuit includes first, second and third timing networks, first and second NMOS transistors and an enable circuit. The first timing network has a first time constant and detects a voltage transient between first and second voltage supply nodes having a rise time less than the first time constant. The first NMOS transistor has a gate connected with an output of the first timing network and a source connected with a gate of the second NMOS transistor. The second NMOS transistor has a drain connected with the first voltage supply node and a source connected with the second voltage supply node. The second timing network is coupled with the gate of the second NMOS transistor and has a second time constant that is greater than a duration of an ESD event. The third timing network is coupled with the enable circuit and has a third time constant, the third timing network generating a first control signal based on the third time constant.

Abstract: A chip protection circuit applied to a chip. The chip protection circuit comprises a transformer circuit, a first protection circuit and a second protection circuit. The transformer circuit has a first side and a second side. Each of the first side and the second side is disposed with first terminals, second terminals and center tap terminals. Three center tap terminal is coupled to a ground. The first protection circuit comprises a diode having a terminal coupled to the center tap terminal at the first side and another terminal coupled to the ground. The second protection circuit comprises input terminals and output terminals. The input terminals of the second protection circuit are coupled to the first terminal and the second terminals at the second side. The output terminals of the second protection circuit are coupled to the chip.

Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

Abstract: A load switch integrated circuit and an electronic device are provided. In a case that a surge voltage is applied to an input of the load switch integrated circuit, a surge detection circuit controls a first discharging unit to be switched on to discharge surge energy from an input of the load switch integrated circuit to the ground, and controls a first switch transistor and a second discharging unit to be switched on through a control circuit to discharge surge energy to an output of the load switch integrated circuit to the ground. Compared with a case that surge energy is discharged only by a surge protection circuit in the conventional technology, surge energy is discharged via two paths, and a circuit area is smaller than that in the conventional technology in a case that there is large surge energy to be resisted.

Abstract: An electrostatic protection circuit, a display panel, and a display apparatus are disclosed. The electrostatic protection circuit comprises a switch control unit, a first electrostatic storage unit configured to store charges, and a second electrostatic storage unit configured to store charges, wherein the first electrostatic storage unit has a first terminal connected to a driving line and a second terminal connected to the switch control unit, and the second electrostatic storage unit has a first terminal connected to the switch control unit and a second terminal connected to a common electrode trace.

Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: A complex electronic component includes a body including a first external electrode and a second external electrode, disposed on an external surface thereof and a laminate; a plurality of first electrodes and a plurality of second electrodes, disposed in the laminate and electrically connected to the first external electrode and the second external electrode, respectively; a third electrode and a fourth electrode, disposed on the laminate to be spaced apart from each other and electrically connected to the first external electrode and the second external electrode, respectively; and an ESD discharge layer disposed between the third electrode and the fourth electrode. In addition, a distance between the third electrode and the fourth electrode is within a range of 30 ?m to 60 ?m.

Abstract: The present invention relates to an overvoltage protection circuit (1) for protecting the electronics of a motor, in particular of an EC motor, against overvoltage pulses, with two protective devices (FS1, FS2) arranged in series connection between two connections (10, 20), wherein a resistor (R1) or (R2) is connected in parallel to each of the protective devices (FS1, FS2) and at least one capacitive element (C1) is provided in parallel connection to the first protective device (FS1), wherein the overvoltage protection circuit (1) has, between the connections (10, 20), at least a first (lower) and a second (higher) breakdown voltage point at a voltage UZ1 or UZ2 dependent on the voltage change over time k=(dU/dt) of a voltage UGA at the connections (10, 20).

Abstract: The present application discloses a display panel and a display apparatus.

Abstract: In an Intrinsically Safe (IS) PoDL/PoE system, a PHY in power sourcing equipment (PSE) has its differential transmit terminals coupled across a primary winding of an isolation transformer. One secondary winding is coupled between a positive terminal of a DC voltage source and a first wire of a twisted wire pair. Another secondary winding is coupled between a negative terminal (e.g., ground) of the DC voltage source and a second wire of the twisted wire pair. The secondary windings provide differential data signals output from the PHY's transceiver to the wire pair, while the DC voltage from the DC voltage source is coupled to the wire pair via the two secondary windings. The DC power is applied to a remote power device having a PHY that communicates with the PSE PHY. Therefore, the secondary windings have the dual purpose of DC-coupling and magnetically coupling the differential data to/from the PHY.

Abstract: One embodiment provides a method, including: creating, for a user, a sound desirability index comprising (i) a plurality of sounds and (ii) desirability of the sound to the user with respect to each of the plurality of sounds, wherein the sound desirability index is created in response to the user hearing a sound and the environment of the user when hearing the sound; receiving an audible input within hearing proximity of the user; identifying the current environment of the user; determining the desirability of the audible input to the user by accessing the sound desirability index, and determining the desirability of the audible input based upon a sound in the audible input and the current environment of the user; and modifying a characteristic of at least a portion of the audible input based upon the desirability of the audible input to the user.

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.

Abstract: A surge protective device (SPD) module includes a module housing, first and second module electrical terminals mounted on the module housing, a gas discharge tube (GDT) mounted in the module housing, and a fail-safe mechanism mounted in the module housing. The GDT includes a first GDT terminal electrically connected to the first module electrical terminal and a second GDT terminal electrically connected to the second module electrical terminal. The fail-safe mechanism includes: an electrically conductive shorting bar positioned in a ready position and repositionable to a shorting position; a biasing member applying a biasing load to the shorting bar to direct the shorting bar from the ready position to the shorting position; and a meltable member. The meltable member maintains the shorting bar in the ready position and melts in response to a prescribed temperature to permit the shorting bar to transition from the ready position to the shorting position under the biasing load of the biasing member.

Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.

Abstract: A vertical channel transistor comprising: a structure made of a given bismuth-based material which passes through a gate block where the structure comprises a channel region which extends through the gate block and source and drain regions on either side of the channel region and of the gate block, where the source and drain regions have a cross-section which is greater than the cross-section of the channel region (FIG. 1K).

Abstract: A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Abstract: An apparatus is described. The apparatus includes an electronic circuit includes multiple supply voltage nodes, an output node and an internal node. The electronic circuit also includes first protection circuitry coupled between the internal node and the output node. The electronic circuit also includes a control circuit coupled to the internal node to bias the internal node. The electronic circuit also includes second protection circuitry coupled to the internal node.

Abstract: The invention relates to an electric circuit arrangement for the input protection circuit of a switching power supply, having a surge protection circuit, which is contacted with a supply voltage on an input side and to which a current-compensated choke is connected as a suppression component, said current-compensated choke being connected to a rectifier circuit comprising an energy storage means on an output side. Via modifications to the circuit technology, such as using two varistors as surge protections, and by using suitable switching elements, such as silicon diodes as rectifier elements and ceramic capacitors as an energy storage means, the input protection circuit is designed such that the requirements, which an expanded input voltage range demands of a surge circuit, are fulfilled. Furthermore, the invention relates to a switching power supply having an electric circuit arrangement according to the invention for the input protection circuit.

Abstract: The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.

Abstract: An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.

Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

Abstract: A power supply, including a primary pre-converter, coupled to supplying mains, configured to receive an AC voltage at low frequency and output a high DC voltage, and further configured to receive the high DC voltage and to output the alternating current; a primary converter, disposed on a primary side of the power supply, coupled to the high DC voltage from the primary pre-converter; an isolating transformer to receive the high frequency AC voltage and output a high frequency secondary AC voltage, and to receive a high frequency secondary AC current and to output primary high frequency AC current; and an output converter, on a secondary side of the power supply, wherein the output converter is configured to receive high frequency AC voltage from the isolating transformer and to output a DC voltage of a first or second polarity to an output, and wherein the output converter is configured to receive DC current of a first or second direction from the output and to output a high frequency AC current to the isolat

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.

Abstract: A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.

Abstract: The disclosure presents a method and a hearing device comprising a first portion adapted for being arranged behind an ear of a user for providing a signal, an output transducer for converting the signal to an acoustic output, a coupling element coupled to the first portion, and wherein the coupling element is adapted for transmitting at least the signal or the acoustic output.

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

Abstract: The present disclosure discloses a drive circuit of a transistor, including: a high-voltage power supply and a low-voltage power supply; a high-voltage power supply domain circuit and a low-voltage power supply domain circuit, where the high-voltage power supply domain circuit is connected to the high-voltage power supply; an electrostatic discharge apparatus; a level shifter circuit, wherein the level shifter circuit includes a level detection circuit, a current limiting module, a discharge module, and a switch transistor, the level detection circuit is connected to a positive electrode of the high-voltage power supply and is separately connected to the current limiting module, the discharge module, and the high-voltage power supply domain circuit, the current limiting module is further connected to a first end of the switch transistor, the discharge module is further connected to a negative electrode of the high-voltage power supply, a control end of the switch transistor is connected to the low-voltage pow

Abstract: A multiway switch, a radio frequency system, and an electronic device are provided. The multiway switch is applicable to an electronic device being operable in a single-frequency dual-transmit mode. The electronic device includes the multiway switch, a radio frequency circuit, and an antenna system. The multiway switch includes four T ports and 2n P ports. The four T ports are configured to be coupled with the radio frequency circuit. The 2n P ports are configured to be coupled with the antenna system. The four T ports include two first T ports coupled with all of the 2n P ports. The multiway switch is configured to be coupled with the radio frequency circuit and the antenna system to implement a preset function of transmitting a sounding reference signal (SRS) through 2n antennas of the antenna system corresponding to the 2n P ports in turn.