Abstract: One embodiment provides a method, including: creating, for a user, a sound desirability index comprising (i) a plurality of sounds and (ii) desirability of the sound to the user with respect to each of the plurality of sounds, wherein the sound desirability index is created in response to the user hearing a sound and the environment of the user when hearing the sound; receiving an audible input within hearing proximity of the user; identifying the current environment of the user; determining the desirability of the audible input to the user by accessing the sound desirability index, and determining the desirability of the audible input based upon a sound in the audible input and the current environment of the user; and modifying a characteristic of at least a portion of the audible input based upon the desirability of the audible input to the user.

Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

Abstract: A surge protective device (SPD) module includes a module housing, first and second module electrical terminals mounted on the module housing, a gas discharge tube (GDT) mounted in the module housing, and a fail-safe mechanism mounted in the module housing. The GDT includes a first GDT terminal electrically connected to the first module electrical terminal and a second GDT terminal electrically connected to the second module electrical terminal. The fail-safe mechanism includes: an electrically conductive shorting bar positioned in a ready position and repositionable to a shorting position; a biasing member applying a biasing load to the shorting bar to direct the shorting bar from the ready position to the shorting position; and a meltable member. The meltable member maintains the shorting bar in the ready position and melts in response to a prescribed temperature to permit the shorting bar to transition from the ready position to the shorting position under the biasing load of the biasing member.

Abstract: A vertical channel transistor comprising: a structure made of a given bismuth-based material which passes through a gate block where the structure comprises a channel region which extends through the gate block and source and drain regions on either side of the channel region and of the gate block, where the source and drain regions have a cross-section which is greater than the cross-section of the channel region (FIG. 1K).

Abstract: An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.

Abstract: A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

Abstract: A semiconductor device includes a substrate, a dielectric layer over the substrate, a first resistor element embedded within the dielectric layer, a second resistor element embedded within the dielectric layer, a first doped well within the substrate, the first doped well being aligned with the first resistor element, and a second doped well within the substrate, the second doped well being aligned with the second resistor element, the second doped well being non-contiguous with the first doped well.

Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Abstract: An apparatus is described. The apparatus includes an electronic circuit includes multiple supply voltage nodes, an output node and an internal node. The electronic circuit also includes first protection circuitry coupled between the internal node and the output node. The electronic circuit also includes a control circuit coupled to the internal node to bias the internal node. The electronic circuit also includes second protection circuitry coupled to the internal node.

Abstract: The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.

Abstract: The invention relates to an electric circuit arrangement for the input protection circuit of a switching power supply, having a surge protection circuit, which is contacted with a supply voltage on an input side and to which a current-compensated choke is connected as a suppression component, said current-compensated choke being connected to a rectifier circuit comprising an energy storage means on an output side. Via modifications to the circuit technology, such as using two varistors as surge protections, and by using suitable switching elements, such as silicon diodes as rectifier elements and ceramic capacitors as an energy storage means, the input protection circuit is designed such that the requirements, which an expanded input voltage range demands of a surge circuit, are fulfilled. Furthermore, the invention relates to a switching power supply having an electric circuit arrangement according to the invention for the input protection circuit.

Abstract: An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.

Abstract: A power supply, including a primary pre-converter, coupled to supplying mains, configured to receive an AC voltage at low frequency and output a high DC voltage, and further configured to receive the high DC voltage and to output the alternating current; a primary converter, disposed on a primary side of the power supply, coupled to the high DC voltage from the primary pre-converter; an isolating transformer to receive the high frequency AC voltage and output a high frequency secondary AC voltage, and to receive a high frequency secondary AC current and to output primary high frequency AC current; and an output converter, on a secondary side of the power supply, wherein the output converter is configured to receive high frequency AC voltage from the isolating transformer and to output a DC voltage of a first or second polarity to an output, and wherein the output converter is configured to receive DC current of a first or second direction from the output and to output a high frequency AC current to the isolat

Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, and a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes. The first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure. Other embodiments are also described.

Abstract: A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

Abstract: The disclosure presents a method and a hearing device comprising a first portion adapted for being arranged behind an ear of a user for providing a signal, an output transducer for converting the signal to an acoustic output, a coupling element coupled to the first portion, and wherein the coupling element is adapted for transmitting at least the signal or the acoustic output.

Abstract: The present disclosure discloses a drive circuit of a transistor, including: a high-voltage power supply and a low-voltage power supply; a high-voltage power supply domain circuit and a low-voltage power supply domain circuit, where the high-voltage power supply domain circuit is connected to the high-voltage power supply; an electrostatic discharge apparatus; a level shifter circuit, wherein the level shifter circuit includes a level detection circuit, a current limiting module, a discharge module, and a switch transistor, the level detection circuit is connected to a positive electrode of the high-voltage power supply and is separately connected to the current limiting module, the discharge module, and the high-voltage power supply domain circuit, the current limiting module is further connected to a first end of the switch transistor, the discharge module is further connected to a negative electrode of the high-voltage power supply, a control end of the switch transistor is connected to the low-voltage pow

Abstract: A multiway switch, a radio frequency system, and an electronic device are provided. The multiway switch is applicable to an electronic device being operable in a single-frequency dual-transmit mode. The electronic device includes the multiway switch, a radio frequency circuit, and an antenna system. The multiway switch includes four T ports and 2n P ports. The four T ports are configured to be coupled with the radio frequency circuit. The 2n P ports are configured to be coupled with the antenna system. The four T ports include two first T ports coupled with all of the 2n P ports. The multiway switch is configured to be coupled with the radio frequency circuit and the antenna system to implement a preset function of transmitting a sounding reference signal (SRS) through 2n antennas of the antenna system corresponding to the 2n P ports in turn.

Abstract: A multiway switch, a radio frequency system, and a wireless communication device are provided. The multiway switch includes five throw (T) ports and four pole (P) ports. The five T ports include one first T port coupled with all of the four P ports. The multiway switch is configured to be coupled with a radio frequency circuit and an antenna system of an electronic device operable in a dual-frequency single-transmit mode, to enable a preset function of the electronic device, the antenna system includes four antennas corresponding to the four P ports, and the preset function is a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.

Abstract: An amplitude limiter circuit includes an inductor and a shunt circuit. The inductor has a first terminal connected to an input node. The shunt circuit is connected to a second terminal of the inductor and also is connected to a low impedance node. If an overvoltage condition forms on the input node, the shunt circuit forms an overvoltage current path from the input node, through the inductor, through the shunt circuit and to low impedance node.

Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.

Abstract: An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A detector is coupled between a first input-output pad and a second input-output pad and detects the voltage levels of the first and second input-output pads to generate a detection signal. A inverter generates a control signal according to the detection signal. A control element is coupled between the first input-output pad and a first node. A current release element is coupled between the first node and the second input-output pad. When the detection signal is at a specific level, the control element and the current release element provide a discharge path to release an ESD current from the first input-output pad to the second input-output pad. When the detection signal is not at the specific level, the control element and the current release element do not provide a discharge path.

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Abstract: A device for detecting a number of electrostatic discharges including a discharge protection unit, in which a detection unit is electrically connected in parallel to the discharge protection unit and the detection unit generates an output signal, which represents the number of electrostatic discharges. A related method is also described.

Abstract: An electrostatic discharge (ESD) protection apparatus includes: an ESD circuit, arranged to perform ESD protection, wherein the ESD circuit includes a first Field Effect Transistor (FET) arranged to release ESD energy; a detection circuit, arranged to perform detection to control the ESD protection apparatus to selectively operate in one of a normal mode and a discharge mode; and a logic circuit, arranged to withstand any oscillation due to resistance-inductance-capacitance (RLC) characteristics of the detection circuit. In the detection circuit, different subsets of a plurality of resistors are respectively combined with a portion of a first serial connection circuit, an entirety of the first serial connection circuit, and a second FET to form different serial connection circuits, to configure the second FET to approach a state of being completely turned off in the normal mode.

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

Abstract: In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

Abstract: A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.

Abstract: The embodiments of the invention provide a method and device for radio frequency (RF) limiting. The device for RF limiting comprises: an analog limiter configured to limit a voltage of a RF input to a predetermined safe range during power-off or power-up until a disable control signal is received from the digital controller, a sensing circuit configured to sense a plurality of shunting currents provided by the analog limiter in sequence to determine a value of each bit of a preset current sensing code and sense the limiting voltage, a digital controller configured to control the digital limiter to perform RF limiting function based on the value of each bit of the preset current sensing code, and control the analog limiter to stop limiting the voltage of the RF input if the limiting voltage is within a predetermined acceptable voltage range.

Abstract: A protecting circuit includes a discharge switch, a trigger circuit, and a shunt circuit. The discharge switch is connected between a first terminal and a second terminal. The trigger circuit is connected to the discharge switch and comprises load devices, connected in series between the first terminal and the second terminal, and a first node between a first one and a second one of the load devices. The shunt circuit is connected to the trigger circuit at the first node, where the shunt circuit comprises a shunt switch and a shunt pathway that is connected between the first node and the shunt switch.

Abstract: An integrated circuit includes a signal transmission block suitable for transmitting signals between a pad and an internal circuit, an electrostatic discharge block suitable for protecting the internal circuit from an electrical shock transmitted through the signal transmission block, and a control block suitable for controlling decoupling/coupling operations of the signal transmission block and the electrostatic discharge block.

Abstract: A metal oxide thin-film transistor and manufacturing for the same are provided. The thin-film transistor includes a substrate; a source electrode, a barrier layer and a drain electrode which are sequentially formed on the substrate; and a semiconductor active layer formed on side surfaces of the source electrode and the drain electrode. The semiconductor active layer is connected with the source electrode and the drain electrode. The metal oxide thin-film transistor has a new structure, in which the source and drain electrodes are parallel to the substrate, and the semiconductor active layer is contacted with the source electrode and the drain electrode by a vertical covering or a step covering way. The channel length does not depend on the photolithography process, but depends on the side length of the source and drain electrodes contacted with the semiconductor active layer.

Abstract: Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage.

Abstract: An interface control circuit comprises an interface signal transceiver circuit coupled with an interface which includes at least one interface pin for transmitting and/or receiving an interface signal through the interface, and a protection circuit for generating a protection control signal according to a capacitance of a first interface pin. During a predetermined detection time period starting from an attaching event, the protection circuit senses the capacitance of the first interface pin, and determines that there is an electrolytic substance existing and coupled with the first interface pin when the capacitance is larger than a predetermined first capacitance threshold. The protection control signal triggers the interface signal transceiver circuit to execute a protection operation. The interface includes the first interface pin and the second interface pin, and the first interface pin and the second interface pin can be one same pin or separate different pins.

Abstract: An electrostatic protection circuit includes a trigger circuit that is connected between a first power line and a second power line. The trigger circuit is configured to output a trigger signal in response to a voltage fluctuation between the first and second power lines. A shunt element has a main current path between the first power line and the second power line and is controllable to be on and off using the trigger signal. A control circuit is configured to supply a control signal to turn off the shunt element when a current value of the main current path of the shunt element exceeds a predetermined threshold value.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: Aspects disclosed herein include trigger circuitry for electrostatic discharge (ESD) protection. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. Trigger circuitry, which includes a voltage divider for example, divides a voltage spike between a supply rail and a ground rail to provide a trigger voltage. An ESD clamping circuitry is activated to discharge the voltage spike when the trigger voltage is determined to exceed an ESD threshold voltage, thus protecting the IC from being damaged by the voltage spike. By activating the ESD clamping circuitry based on the trigger voltage divided from the voltage spike, it is possible to adapt the ESD protection circuit to provide ESD protection based on different ESD threshold voltages, thus making it possible to deploy the ESD protection circuit on ICs having different ESD protection requirements.

Abstract: A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.

Abstract: An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.

Abstract: A circuit protection device is provided. The circuit protection device includes an active energy absorber that is coupled between two power lines in an electrical power distribution system and is configured to selectively conduct fault current responsive to overvoltage conditions. The active energy absorber includes an overvoltage protection module that includes two thyristors that are connected in anti-parallel with one another and a varistor that is connected with the overvoltage protection module as a series circuit. The series circuit including the varistor and the overvoltage protection module is connected between the power lines.

Abstract: A device includes a transistor configured for depletion-mode operation, the transistor having a gate terminal and a drain terminal, and an electrostatic discharge (ESD) protection circuit coupling the gate terminal and the drain terminal. The ESD protection circuit includes a discharge path circuit and a trigger circuit coupled to, and configured to control, the discharge path circuit. The discharge path circuit and the trigger circuit are disposed between the gate terminal and the drain terminal.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: There are provided circuits and methods for surge protection. For example, there is provided a clamp circuit for protecting a load against a surge. The clamp circuit can include a power dissipation circuit including at least one transistor and a resistor. The clamp circuit can further include a voltage sensitive device configured to cause a voltage limit across the load when the surge occurs. The power dissipation circuit can be configured to turn on the at least one transistor to dissipate power across one of the resistor and the at least one transistor.

Abstract: A biometric sensing device includes a first electricity storage component, a first sensing component, a first driving component and a control unit. The first sensing component is coupled with the first electricity storage component, wherein when the first sensing component is turned on, a charging path is formed between the first sensing component and the first electricity storage component, and the first sensing component makes the first electricity storage component be charged according to a sensed biometric. The first driving component is coupled with the first electricity storage component and the first sensing component, wherein when the first driving component is turned on, the first electricity storage component discharges. The control unit is coupled with the first sensing component and/or the first driving component for turning on the first sensing component and the first driving component.