Abstract: A transient voltage suppressor (TVS) circuit includes a P-N junction diode and a silicon controlled rectifier (SCR) formed integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes multiple fingers of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer, defining current conducting regions between the fingers. The current paths for the SCR and the P-N junction diode are formed in each current conducting region but the current path for the SCR is predominantly separated from the current path for the P-N junction diode in each current conducting region in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The TVS device of the present invention realizes low capacitance at the protected node. The TVS device is suitable for protecting data pins of an integrated circuit, especially when the data pins are used in high speed applications.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.

Abstract: Golf ball incorporating mixtures of thermoplastic polymers and polymethyl methacrylate (MMA) copolymers. The thermoplastic polymer and MMA copolymers may be included in weight ratios of from 98:2 to 50:50. The mixture may have different hardness than that of the thermoplastic polymer, a glass transition temperature Tg-m greater than a glass transition temperature Tg-tp of the thermoplastic polymer, and a modulus, tensile strength and ultimate elongation greater than that of the thermoplastic polymer.

Abstract: A converter valve includes a top shielding cover, a bottom shielding cover, at least two vertically stacked valve layers, and a maintenance platform. The top shielding cover is disposed at an upper portion of an uppermost valve layer. The bottom shielding cover is disposed at a lower portion of a lowermost valve layer. Each of the valve layers comprises two valve modules disposed side-by-side in a horizontal direction. The two valve modules are electrically connected via a busbar and mechanically connected via securing connectors. A lower valve layer is connected to an upper valve layer in a suspended manner. A body of the maintenance platform is located between horizontal planes on which two vertically adjacent valve layers are located, or between horizontal planes on which the lowermost valve layer and the bottom shielding cover are located.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: An electrostatic discharge (ESD) device includes an active region. The active region includes a first active line having a first plurality of gate features; and a second active line having a second plurality of gate features. The ESD device further includes a first pick-up line having a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line. The ESD device further includes a second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line.

Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

Abstract: A vehicle system in a hybrid vehicle comprises a controller configured to generate for output a modulated voltage to a direct current capacitor to prevent voltage spikes on the capacitor in response to receiving a reference current via a direct current voltage clamping control block that outputs a reference current in response to a difference between a feedback voltage and a reference voltage exceeding a threshold.

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.

Abstract: An electrostatic protection circuit includes a first power line and a second power line. The electrostatic protection circuit includes a trigger circuit connected between the first and second power lines and outputs a trigger signal in response to a fluctuation of a voltage difference between the first and second power lines. The electrostatic protection circuit further includes a shunt element that is controlled by the trigger signal, and includes a main current pathway connected between the first and second power lines. The electrostatic protection circuit further includes a control circuit that is connected between the first and second power lines and supplies a control signal for increasing the conductivity of the shunt element when the voltage difference between the first power line and the second power line exceeds a predetermined voltage.

Abstract: An ESD protection device includes a multilayer body including base material layers, a hollow portion inside the multilayer body, a ground electrode exposed at the hollow portion, first and second discharge electrodes exposed at the shared hollow portion and opposing the common ground electrode, and an auxiliary discharge electrode including conductive particles dispersed in the base material layer and extending along an inner surface of the hollow portion. At least the auxiliary discharge electrode in an adjacent region between the first discharge electrode and the second discharge electrode is divided into a portion on the first discharge electrode side and a portion on the second discharge electrode side by a non-formation section where the auxiliary discharge electrode is not provided in the hollow portion.

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract: A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off.

Abstract: An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.

Abstract: This electrostatic protection circuit makes it possible for a discharge operation to be started only in the case where a rise in an applied voltage is steep, and for static electricity to be sufficiently released. This electrostatic protection circuit includes a discharge circuit that is connected between a first node and a second node and discharges charge produced by static electricity, a latch circuit that is connected between the first node and the second node and outputs a signal that controls operation of the discharge circuit to the discharge circuit, a switch circuit that is connected to the latch circuit and changes the signal that controls operation of the discharge circuit, and a control circuit that is connected between the first node and the second node and outputs a signal that controls operation of the switch circuit to the switch circuit.

Abstract: Systems and methods are provided for protecting a power conversion system. A system controller includes a first controller terminal and a second controller terminal. The first controller terminal is configured to provide a drive signal to close and open a switch to affect a first current flowing through a primary winding of a power conversion system. The second controller terminal is configured to receive first input signals during one or more first switching periods and receive second input signals during one or more second switching periods. The system controller is configured to determine whether a temperature associated with the power conversion system is larger than a predetermined temperature threshold, and in response to the temperature associated with the power conversion system being larger than the predetermined temperature threshold, generate the drive signal to cause the switch open and remain open to protect the power conversion system.

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Abstract: This disclosure describes techniques for generating relatively low regulated power supply voltages over a relatively wide range of input voltages. The techniques for generating the regulated voltages may include using at least two different pass transistors to regulate an output voltage of a voltage regulator. Both the turn-on threshold voltage and the maximum drain-to-source voltage rating of the first pass transistor may be greater than the corresponding characteristics of the second pass transistor. Using two different pass transistors with two different turn-on threshold voltages and two different maximum drain-to-source voltage ratings may increase the range of voltages over which a voltage regulator can generate a relatively low output voltage relative to the range of voltages that would be allowable if a single type of pass transistor were used.

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

Abstract: An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than ?10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than ?10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.

Abstract: A fingerprint sensing device includes a substrate; a plurality of pixels arranged in a grid of rows and columns, each pixel having an active thermal sensing element therein; a first metal layer forming first addressing lines for addressing the active thermal sensing elements; a second metal layer above the first metal layer and forming second addressing lines for addressing the active thermal sensing elements; an electrically conductive ESD protection layer; and an insulating layer disposed between the ESD protection layer and the active thermal sensing elements. The ESD protection layer is electrically connected to a bias potential. The ESD protection layer is disposed in a pattern such that it partially overlaps each pixel, the ESD protection layer at least partially overlapping the active thermal sensing element of each pixel.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

Abstract: A scalable fuse design for individual pixels of a focal plane array of photodiodes comprises a fuse disposed on the upper surface of each photodiode in the array, wherein the fuse is situated proximal to a side of each photodiode. The fuse of each photodiode is electrically coupled to the active region thereof via a first bus and is electrically coupled to an ROIC via a second bus.

Abstract: In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

Abstract: A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.

Abstract: A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other. Each current supply line is connected to a plurality of driving transistors in a line. One end of each current supply line is connected to the first current input terminal via a first wiring intersecting with the current supply lines, and the other end thereof is connected to the second current input terminal via a second wiring intersecting with the current supply lines. Accordingly, a current is supplied to each current supply line from both the first and the second current input terminals. The first and the second current input terminals are provided separately from each other.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: An inverter for an electric machine includes multiple phase systems, each including a high-side switching device and a low-side switching device, the high-side switching device being connected on one side to a first pole of an intermediate circuit and on another side to the low-side switching device, the low-side switching device being connected on one side to the high-side switching device and on the other side to a second pole of the intermediate circuit, the high-side switching device and the low-side switching device each having a circuit breaker which has a switching input, a power input and a power output, the power input and the power output being electrically connected with each other when the circuit breaker is closed and are electrically disconnected from each other when the circuit breaker is open. The inverter further has a control circuit and an intermediate circuit voltage limiting circuit.

Abstract: An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.

Abstract: An image forming apparatus includes a scanner configured to acquire scan data by scanning a scan target, an electrostatic discharge (ESD) detector configured to detect an ESD when the scan data is acquired, and a data processor configured to process the scan data acquired when the ESD is detected according to an operation state of the scanner.

Abstract: A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value.

Abstract: A device includes an electronic display supported in a display chassis, a digitizer sensor overlaid on the electronic display, a circuit configured to detected touch interaction with the digitizer sensor based on output sampled and a display controller configured to control output on the electronic display. The electronic display includes an electrostatic discharge (ESD) shield layer. The ESD shield layer is electrically connected to device ground and the impedance to the device ground of the ESD shield layer is configured to be sensitive to pressure applied on the digitizer sensor during user interaction. The digitizer sensor output is sensitive to the change in the impedance of ESD shield layer to the device ground.

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

Abstract: An ESD protection circuit is disclosed, in which an RC trigger circuit and a transmission gate are used for determination of ESD protection triggering, and a silicon-controlled rectifier for ESD current conductance. The RC trigger circuit and the transmission gate allow improved trigger efficiency. In addition, the silicon-controlled rectifier incorporates first and second resistors, which can be implemented to have very low resistance values and are therefore able to effectively prevent the occurrence of latch-up during normal operation, as well as pull-up and pull-down transistors which can make an additional contribution to latch-up inhibition when turned on.

Abstract: A display device according to the present inventive concept includes: a display panel comprising a pixel electrode receiving a data voltage and a common electrode receiving a common voltage; and a touch sensor comprising a plurality of driving electrodes and a plurality of sensing electrodes, wherein the touch sensor applies a touch detection signal to the plurality of driving electrode and detects a touch location by receiving a sense signal from the plurality of sensing electrode in an active mode, and determines whether a touch is made by receiving sense signals of the plurality of sensing electrodes, that are fluctuated by a ripple of a common voltage applied to the common electrode according to driving of the display panel in an idle mode.

Abstract: A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected.

Abstract: A method for modeling electrostatic discharges. The method may include obtaining a circuit netlist for an integrated circuit. The circuit netlist may describe connection information for various electronic components within the integrated circuit. The method may further include obtaining, by removing a portion of the electronic components from the circuit netlist, a reduced netlist. The method may further include determining, using the reduced netlist, various circuit parameters regarding an electrostatic discharge event for the integrated circuit. The method may further include simulating, using the circuit parameters, a discharge path within the integrated circuit for the electrostatic discharge event.

Abstract: A surge absorber module includes a conductive bracket with an end fixed to a main body and electrically connected to a pin, and the other end electrically connected to a surge absorbing member through a hot melt member, and an elastic member with an end elastically abutting the main body and the other end elastically abutting the conductive bracket. The conductive bracket is elastically abutted by the elastic member to move horizontally in an accommodating space and disconnect the electrically connected surge absorbing member.

Abstract: An apparatus may include a bus that electrically couples an electrical load to redundant power feeds. The apparatus may also include at least one capacitive component electrically coupled between first and second rails of the bus via both a conductive path and a resistive path that has substantially greater resistance than the conductive path. In addition, the apparatus may include a switching mechanism electrically coupled between the first and second rails of the bus that causes the capacitive component to charge through the conductive path until a threshold voltage on the first rail of the bus is reached. When the threshold voltage on the first rail of the bus is reached, the switching mechanism may close the conductive path and force the capacitive component to charge through the resistive path. Various other systems and methods are also disclosed.

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

Abstract: An ESD protection device includes: a first insulating layer (2a); a second insulating layer (2b) stacked on the first insulating layer (2a); a first via conductor (6a) extending through the first insulating layer (2a) in a thickness direction; a discharge gap portion (10) provided so as to be in contact with the first via conductor (6a), between the first insulating layer (2a) and the second insulating layer (2b); a first wiring line (7a) that is arranged on a surface of the first insulating layer (2a) opposite to the discharge gap portion (10) and that is electrically connected to the first via conductor (6a); and a second wiring line (7b) that is arranged on one surface of the second insulating layer (2b) and that includes a portion facing the first via conductor (6a) with at least the discharge gap portion (10) interposed therebetween.

Abstract: Provided is a semiconductor integrated circuit device including: an output buffer circuit having a P channel transistor connected between a first power supply terminal and a signal terminal; a potential control circuit that supplies potential from the first power supply terminal or the signal terminal to a back gate of the P channel transistor according to the potential of the signal terminal; a first protection diode having an anode connected to the signal terminal; a common discharge line connected to a cathode of the first protection diode; an electrostatic discharge protection circuit connected between the common discharge line and a second power supply terminal; and a second protection diode having an anode connected to the second power supply terminal and a cathode connected to the signal terminal.

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract: A touch panel module including a touch panel and an electrostatic discharge (ESD) protection circuit is provided. The touch panel includes one or more conductive electrodes and one or more dummy electrodes. The one or more conductive electrodes include at least one of one or more driving electrodes and one or more sensing electrodes. The one or more dummy electrodes are configured to fill areas between the one or more conductive electrodes or areas outside the one or more conductive electrodes. The ESD protection circuit is electrically connected to at least one dummy electrode of the one or more dummy electrodes, and configured to provide an electrostatic discharging path to the at least one dummy electrode. Furthermore, an electrostatic discharging method of the touch panel module is also provided.

Abstract: The present disclosure provides a surge protection device including a ceramic substrate (1), at least one pair of discharge electrodes (31) disposed on a surface of the ceramic substrate (1) so as to face each other at end portions thereof with a space in between, outer electrodes (32) electrically connected to the corresponding discharge electrodes (31), and a discharge auxiliary electrode (4) disposed between the end portions of the pair of discharge electrodes (31) The discharge auxiliary electrode (4) contains crystalized glass and particles of conductive powder (40) dispersed apart from each other in the crystalized glass.

Abstract: In order to obtain a drive circuit of a power semiconductor device capable of making a fast response to a voltage fluctuation dV/dt and preventing a malfunction of the power semiconductor device while suppressing power consumption with a simple circuit configuration, a control circuit controlling ON and OFF switching of the power semiconductor device, a DC power supply supplying a voltage between control terminals of the power semiconductor device, and a switching element connected between the control terminals of the power semiconductor device are provided. The switching element turns ON in a case where a power supply voltage of the DC power supply drops or in a case where the voltage between the control terminals of the power supply device increases in a state where the power supply voltage of the DC power supply has dropped, and thereby causes a short-circuit between the control terminals of the power semiconductor device.

Abstract: An acoustic feedback system includes a memory and processor to receive at least one of a plurality of output signals from a plurality of sensors. The system determines whether an output signal has reached a first threshold, and sends an audible sound signal to a speaker(s) based on the first threshold. Thus, the acoustic feedback system utilizes output signals of various vehicle sensors and generates audible signals based on the sensor output signals.