With Specific Dielectric Material Or Layer Patents (Class 361/750)
  • Patent number: 6288343
    Abstract: Disclosed is a printed circuit board including a first layer having a first stacked region, a second stacked region spaced apart from the first stacked region by a selected distance, and a flexible connection part disposed between the first and second stacked regions, and extending to the first stacked region and the second stacked region with selected width and length, the flexible connection part having a conductive pattern layer for signal transmission between the first stacked region and the second stacked region; a pair of second layers disposed apart on an upper surface of each of the first and second stacked regions of the first layer and having a first signal pattern layer on both surfaces of each of the second layers, wherein the first signal pattern layer of the second layer is electrically connected to the conductive pattern of the flexible connection part, a pair of upper metal layers disposed on respective upper surfaces of the second layer, the upper metal layer interposing a first insulating ad
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: September 11, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hyun Ahn, Jong-Hyun Lee
  • Patent number: 6280851
    Abstract: Copper foil used in printed circuit boards is protected from contamination both prior to laying up the circuit board components and during processing by a multilayer protective film structure having a silicone adhesive disposed on one entire surface and a silicone release composition on the other entire surface.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: August 28, 2001
    Assignee: Sentrex Company, Inc.
    Inventors: Melvin Pasternack, Jurgen Matthes
  • Patent number: 6246009
    Abstract: A novel basestock composite comprising two copper conducting sheets bonded to insulator layers comprised of fiberglass sheets impregnated with an adhesive such as epoxy, wherein the insulator layers are both affixed to a release layer which is not coextensive with the borders of the insulator layers such that when the basestock is cut at a point internal to its borders and into the release layer the two basestock composites can be separated.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: June 12, 2001
    Assignee: Teledyne Industries, Inc.
    Inventors: Lee J. Millette, A. Roland Caron, Joseph A. Thoman
  • Patent number: 6228500
    Abstract: An adhesive composition, which is useful as an adhesive for FPC protective film and is particularly superior in dimensional stability and adhesion is described herein. The adhesive composition comprises a resin component containing an phenoxy resin, an epoxy resin and a curing agent, characterized in that said resin component further contains a polyester polyol and an inorganic colloid dispersed in said resin component.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: May 8, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Yuji Hiroshige, Kohichiro Kawate
  • Patent number: 6184577
    Abstract: In regard to a packaging substrate on which a semiconductor chip is mounted, the surface copper foil of a double-sided copper-clad glass epoxy resin laminated sheet is subjected to circuit formation and inner-layer bonding, then an epoxy resin adhesive film with copper foil is bonded to the surface of the inner-layer circuit by press lamination, and a through hole is formed through the sheet, followed by electroless copper plating, outer-layer circuit formation by the subtractive process, and solder coating to obtain the packaging substrate. The bump electrode of the semiconductor chip and the packaging substrate are connected through an adhesive film.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: February 6, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenzo Takemura, Itsuo Watanabe, Akira Nagai, Osamu Watanabe, Kazuyoshi Kojima, Akishi Nakaso, Kazunori Yamamoto, Yoshiyuki Tsuru, Teiichi Inada, Yasushi Shimada
  • Patent number: 6166915
    Abstract: A method of forming a circuit board includes, a) providing a temporary substrate; b) depositing an uncured electrically insulative circuit board material over the temporary substrate, the circuit board material adhering to the temporary substrate; c) substantially curing the uncured circuit board material into at least one self supporting sheet; d) providing circuit traces atop the cured self supporting sheet; e) mounting an electronic circuit component atop the cured self supporting sheet in electrical communication with the circuit traces; and f) peeling the temporary substrate and cured self supporting sheet from one another.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: December 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Rickie C. Lake, Joe Mousseau, Mark E. Tuttle
  • Patent number: 6159586
    Abstract: The present invention relates to a multilayer wiring substrate for mounting a semiconductor chip, etc. The multilayer wiring substrate is comprised of a plurality of double-sided circuit substrates, each comprised of an organic high molecular weight insulating layer and wiring conductor. An adhesive is used for laminating the double-sided circuit substrates. A Ni--Fe based alloy foil or a titanium foil is embedded within the organic high molecular weight insulating layer.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: December 12, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Yasushi Inoue, Masakazu Sugimoto
  • Patent number: 6157541
    Abstract: Two semiconductor memory chips are placed onto a flexible wiring and are shaped by simple folding of the flexible wiring about a central elastic line, into a space-efficient stack arrangement whose outer contacts are formed only at one marginal side. To form memory cards, a plurality of such stack arrangements can be placed onto a simply constructed printed board.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: December 5, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Juergen Hacke
  • Patent number: 6157548
    Abstract: An electrically shielded housing for an electrical device and method therefor having an insert member disposed in a cavity of a non-conductive housing body member. The insert member includes a conductive inner surface portion disposed adjacent an outer surface portion of the body member cavity. A non-conductive outer surface portion of the insert member forms a housing cavity for receiving an electrical device. The conductive inner surface portion of the insert member at least partially electrically shields the electrical device, and the non-conductive outer surface portion of the insert member insulates the electrical device from the conductive inner surface portion thereof.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: December 5, 2000
    Assignee: Illinois Tool Works Inc.
    Inventors: Peter Michael Frederick Collins, Terry Dean Thomason, Ralph A. Hausler
  • Patent number: 6147860
    Abstract: An external storage device includes an external storage device main includes a thin type external storage device module formed into a package sealed on one side from a storage element containing at least one non-volatile semiconductor memory device, and a flat type external connection terminal connected to an input/output terminal of the storage element and led and exposed to a backside of the module, and an external storage device unit that includes an external storage device main detachable section for engaging, insertedly attaching, and detaching the external storage device main, a resilient contact electrically connecting to the external connection terminal of the external storage device main, and at least a part of a circuit for driving and controlling the storage element.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 6137671
    Abstract: The present invention is directed towards an embedded electrical storage device in a layered electrical device, such as a printed circuit board or integrated circuit chip. An electrical energy storage device, having an outer surface, is embedded in the layered electrical device, either partially or fully is formed of at least two electrical conducting layers sandwiching a high capacity dielectric, and is connected to other circuitry on the layered electrical device. This arrangement may be used in numerous applications including use as storage and filter capacitors for power conditioning.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: October 24, 2000
    Assignee: Energenius, Inc.
    Inventor: Donald T. Staffiere
  • Patent number: 6122178
    Abstract: A PCMCIA electronics package adapted to enclose, and provides EMI shielding to, a printed circuit board (PCB). The PCB has an electrical connector adapted for plugging into a computer is at a one end and RF circuitry at the other end. Electronic components are disposed on an inner region of the surfaces of the PCB. The PCB has a ground plane conductor disposed therein. Electrically conductive strips are disposed on the surfaces of the PCB along opposing side edges and the other end of the PCB. A plurality of conductive vias pass through a portion of the PCB electrically connecting the electrical strip conductors to the ground plane conductor. A plurality of resilient, electrically conductive clips is provided. Each one of the clips has: a cup-shaped region disposed over a corresponding one of the PCB edges and the other end of the PCB. Side portions of the cup-shaped regions are in contact with conductive strips. The clips have an arm with a distal end elevated from the PCB.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: September 19, 2000
    Assignee: Raytheon Company
    Inventors: Macdonald J. Andrews, Richard G. Berard, Arnold E. VanDoren
  • Patent number: 6118665
    Abstract: A flexible printed circuit having wiring patterns printed on a flexible resin film, comprising a narrow flexible area having first wiring patterns and constituting a flexible wiring part and a broad connection area adapted to be adhered to a main board and having second wiring patterns connected to the first wiring patterns and adapted to be electrically connected to wiring patterns on the main board. The second wiring patterns serve to electrically connect the first wiring patterns of the flexible wiring part to the wiring patterns on the main board. Also included is a conductive adhesion surface formed on the broad connection area along a side of the main board, having a width larger than a width of the first wiring patterns, and extending from an inside of a region to an outside thereof. The region is defined in the broad connection area by extending a boundary of the flexible area into the broad connection area.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: September 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Katsuhiko Kishida, Katsunori Tanaka, Toshiya Onodera, Hirofumi Miyamoto
  • Patent number: 6104280
    Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: August 15, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake, Curtis M. Medlen
  • Patent number: 6075705
    Abstract: In an I/O card has a case having metallic top and bottom covers, a printed circuit board mounted in the case, a connector disposed in the case for connecting with a personal computer system, and a card side I/O connector disposed in the case for mating with a cable side I/O connector connected to external device, the card side I/O connector is provided with no shell but is in direct contact with the metallic top and bottom covers, so that the both covers came in direct contact with a metallic shell of the cable side I/O connector when the cable side I/O connector is mated with the card side I/O connector. In an embodiment, the top cover is provided with locking pieces which engages with elastic locks of the cable side I/O connector for locking a mating condition between the card side I/O connector and the cable side I/O connector.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: June 13, 2000
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventors: Keisuke Nakamura, Kayoko Gotou
  • Patent number: 6075707
    Abstract: A radio frequency identification tag is made with printed antenna coil integrated on a flexible substrate, and an integrated circuit area of the substrate adjacent the antenna coil for carrying circuit elements. The radio frequency identification tag is designed to be sufficiently robust to withstand the rigors of mail efficiency processing measurement applications.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: June 13, 2000
    Assignee: Kasten Chase Applied Research Limited
    Inventors: Donald Harold Ferguson, Mircea Paun
  • Patent number: 6061246
    Abstract: The printed circuit board and tape carrier package of an LCD module are replaced with a microelectronic package that includes a substrate and a layer integrally formed on the substrate that is flexible relative to the substrate. The flexible layer includes at least one flexible extension that extends beyond the substrate. A plurality of conductive lines are included on the substrate that extend onto the flexible layer and extend along the flexible layer onto the at least one flexible extension. The conductive lines on the flexible extension are electrically connected to the data lines, the gate lines or both. Accordingly, tape carrier packages need not be used so that cost may be reduced. Moreover, separate operations to connect tape carrier packages to printed circuits boards may be eliminated, thereby improving reliability and/or cost of the device.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: May 9, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-seob Oh, Jin-hyeok Park, Hyun-sang Cho
  • Patent number: 6054762
    Abstract: A paste of active metallic brazing material is applied to the entire surface of each side of aluminum nitride or alumina ceramic substrate 1; circuit forming copper plate 3 having a thickness of 0.3 mm is placed in contact with one surface of the substrate and a heat dissipating copper plate 4 having a thickness of 0.25 mm placed in contact with the other surface; the individual members are compressed together and heated at 850.degree. C.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: April 25, 2000
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Masami Sakuraba, Masami Kimura, Junji Nakamura, Masaya Takahara
  • Patent number: 6038133
    Abstract: A circuit component built-in module of the present invention includes an insulating substrate formed of a mixture comprising 70 wt % to 95 wt % of an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a principal plane of the insulating substrate, a circuit component arranged in an internal portion of the insulating substrate and electrically connected to the wiring patterns, and an inner via formed in the insulating substrate for electrically connecting the plurality of wiring patterns. Thus, a highly reliable circuit component built-in module having high-density circuit components can be obtained.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: March 14, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Kouichi Hirano
  • Patent number: 6033765
    Abstract: The present invention provides a printed circuit substrate comprising a lightweight prepreg and a conductive layer. The prepeg having uniform formation, low linear thermal expansion coefficient and good mechanical strength, comprising a porous para-oriented aromatic polyamide film and a thermoplastic resin and/or a thermosetting resin, the porous para-oriented aromatic polyamide film being impregnated with the thermoplastic resin and/or the thermosetting resin, a process for producing the same, and a printed circuit substrate/board using the same.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: March 7, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tsutomu Takahashi, Yoshifumi Tsujimoto, Hiroaki Kumada, Hiroyuki Sato
  • Patent number: 6008982
    Abstract: A low profile electrical distribution center comprises a plurality of thin bus assemblies that are stacked one upon another. Each bus assembly comprises stamped metal circuit components having planar bus portions sandwiched between thin flexible upper and lower sheets of insulation material that are bonded together. The stamped metal circuit components have male blade terminals that extend up or down from the bus portions. The thin flexible sheets of insulation material are die cut to facilitate manufacture and assembly of the stamped metal circuit components from a one piece stamped metal blank.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: December 28, 1999
    Assignee: General Motors Corporation
    Inventor: Randall Kent Smith
  • Patent number: 6007668
    Abstract: A TAB (tape automated bonding) tape of high precision is formed without the deformations of its conductor pattern and the like and which is hermetically sealed with resin. The method for producing a TAB tape includes punching required holes, such as a device hole 14 and the like, in a metal plate 10 coated with an insulating adhesive layer 12 over the area where a conductor pattern is to be formed; and forming a required conductor pattern 24 by bonding a conductor metal foil onto the adhesive layer and by etching the conductor metal foil. Thus, the material cost of this TAB tape can be reduced and the production of this tape is facilitated.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: December 28, 1999
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kotaro Kodani, Kazuo Koyanagi, Kiyokazu Sato
  • Patent number: 6002590
    Abstract: A circuit board has traces attached to a flexible trace surface such that the traces can be displaced in a direction of thermal expansion of a component attached to the traces without causing the failure of the solder joint between the component and the trace. In one embodiment, the printed circuit board substrate is etched away in areas not covered by the traces such that flexible protuberances are formed from the substrate underneath the traces. In one method for constructing such a circuit board, a conductive layer is deposited on the printed circuit board substrate. The conductive layer is then etched to form conductive traces. The printed circuit board substrate is then selectively etched using the traces as a mask for etching the printed circuit board substrate. In a second printed circuit board embodiment, a flexible layer of a material is deposited onto the printed circuit board substrate. The traces are then formed on top of the flexible layer.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: December 14, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Kevin G. Duesman
  • Patent number: 5995370
    Abstract: An effective heat-sinking arrangement is realized for circuit elements used in a portable type information terminal having a small restricted space therein. Wherein, a first substrate has a cavity formed in its insulating layer extending to an earthing layer and filled with a silver paste to form a seat for mounting a CPU that can thus thermally contact with the earthing layer, and a second substrate has a cavity formed in an insulating layer in which cavity a heat-conducting cushion bonded to the top of the CPU is fitted for creating the heat-conductive route between the CPU and the earthing layer of the second substrate.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: November 30, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshihiro Nakamori
  • Patent number: 5995374
    Abstract: A substrate unit is constituted by a printed substrate on which electronic parts such as a relay block is mounted, and at least printed circuit conductors and terminals in the printed substrate and relay block are buried in a sealing resin material hardened in a bag-like body of a thin resin film set in an injection mold, and the hardened sealing resin material is then released from the injection mold together with the bag-like body.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: November 30, 1999
    Assignee: Yazaki Corporation
    Inventors: Masataka Suzuki, Hiroyuki Ashiya, Yayoi Maki, Atsushi Masuda
  • Patent number: 5973927
    Abstract: A mounting structure for an integrated circuit device comprises a first substrate, a second substrate and an insulator. The first substrate contains conductive wiring electrically connected to the integrated circuit device. The first substrate is mounted on the second substrate which have a ground pattern. The insulator is provided between the conductive wiring and the ground pattern.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Shinji Tanaka
  • Patent number: 5973923
    Abstract: A package for power converters in which a multilayers circuits board holds the components. The winding of the magnetic elements are incorporated in the multilayers circuit board. The top and some portion of the bottom layer are also support for electronic components. Some of the components are placed on the top layer, which may not be utilized for magnetic winding, reducing the footprint of the magnetic elements to the footprint of the magnetic core. The power dissipating devices placed on pads which have a multitude of copper coated via connecting the top to bottom layers. Through these via the heat is transferred from the power devices to the other side of the PCB. In some of the embodiment of this invention the heat can be further transferred to a metal plate connected to the multilayers circuit board via a thermally conductive insulator. The baseplate has cutouts or cavities to accommodate the magnetic cores.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: October 26, 1999
    Inventor: Ionel Jitaru
  • Patent number: 5965273
    Abstract: A polymeric composition which has a dielectric constant K' greater than 4 at 20.degree. C. which varies little with temperature is made from a polymer or mixture of polymers and a ceramic or a mixture of ceramics, where the polymer or mixture of polymers has a dielectric constant K' in the range of about 1.5 to about 3.5 and a temperature coefficient of dielectric constant TCK' that is negative and is between 0 and about -300 ppm/degree C.; and the ceramic includes a first ceramic, which may be one ceramic or a mixture of ceramics, each having a dielectric constant in the range of about 15 to about 200 and a TCK' that is positive and is between zero and about 3000 ppm/degree C.; and an optional second ceramic, which may be one ceramic or a mixture of ceramics, each having a dielectric constant in the range from about 3 up to about 15 and a TCK' that is positive and is between zero and about 300 ppm/degree C.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: October 12, 1999
    Assignee: Hoechst Celanese Corporation
    Inventors: Lakshaman M. Walpita, Michael R. Ahern
  • Patent number: 5956233
    Abstract: A high density single inline memory module (140) comprising a printed circuit board (132) and at least one integrated circuit module (130) attached to the first side (134) of the printed circuit board (132), wherein the integrated circuit modules (130) each including first and second integrated circuit packages (30) stackably and electrically connected together is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Chee Kiang Yew, Kian Teng Eng, Sian Yong Khoo, Bok Leng Ser
  • Patent number: 5901050
    Abstract: In a wired base plate for an electronic part, an infinite number of metallic posts made of copper are provided to a lid joining section of a plural wire layer portion, which section includes a lid joining surface area to which a lid is joined. The metallic posts supports a pressure applied thereto from a lid at the time of mounting of the wired base plate on a circuit board and prevent the plural wire layer portion having a plurality of conductor wire layers and a plurality of resinous insulation layers, from being deformed by compression. A package for an electronic part having such a wired base plate is also provided.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: May 4, 1999
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Ryuji Imai
  • Patent number: 5892663
    Abstract: A device for protecting against electrical shock or other hazards from electrical components on a card includes a thin relatively flat one piece member cut and scored to form folding lines, integral latching tabs and natural hinges therein. When placed on the card and folded along the scored lines and natural hinges a protective cover for at least the pin sides and circuit sides of electrical components (modules) is provided. The device is ideally suited to protect electrical components, in situ, on a circuit card.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: April 6, 1999
    Assignee: International Business Machines Corporation
    Inventors: Nancy J. Bolinger, Andre Byungyup Minn, Challis Llewellyn Purrington, Sr., Franklin Gerald Darroch
  • Patent number: 5889234
    Abstract: A dielectric member with an integral, electrically conductive surface is made by molding a substrate from a zirconia alloy powder using a tape casting process. The resulting green substrate is sintered and after sintering may be cut to the final desired size and shape. Once the insulating ceramic substrate has been formed, the surface of the substrate is modified using infrared laser energy. Through the impingement of infrared laser radiation upon the surface of the ceramic substrate, an electrically conductive region is produced on the surface of the substrate. In such manner, the entire surface can be made electrically conductive or a particular pattern can be traced. As an integral part of the substrate, the surface will not delaminate from the substrate. Further, because the modified surface region and the substrate are both a zirconia, the coefficients of thermal expansion of the substrate and the modified surface region will be closely matched.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: March 30, 1999
    Assignee: Eastman Kodak Company
    Inventors: Syamal K. Ghosh, Gregory S. Jarrold, Dilip K. Chatterjee, David C. Press
  • Patent number: 5889104
    Abstract: A low dielectric constant material is provided for use as an insulation element in an electronic device, such as but not limited to an integrated circuit structure for example. Such a low dielectric constant material may be formed from an aqueous fluoropolymer microemulsion or microdispersion. The low dielectric constant material may be made porous, further lowering its dielectric constant. The low dielectric constant material may be deposited by a spin-coating process and patterned using reactive ion etching or other suitable techniques.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: March 30, 1999
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: C. Thomas Rosenmayer
  • Patent number: 5861664
    Abstract: In an LSI package, terminal resistance elements are formed of resistive paste which, consisting of a mixture of fine powder of either oxidized metal or carbon and fine powder of glass, is buried and sintered in a ceramic wiring board in the direction to penetrate it. Front side wiring, connecting the parts of the terminal resistance elements exposed on the front face of the ceramic wiring board to input/output circuits of the LSI chip to be mounted on the front face of the ceramic wiring board, is formed on the front face of the ceramic wiring board and in the top layer of the ceramic wiring board. Back side wiring, connecting the parts of the terminal resistance elements exposed on the back face of the ceramic wiring board to a voltage clamp wiring network, is formed on the back face of the ceramic wiring board.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: January 19, 1999
    Assignee: NEC Corporation
    Inventor: Tatsuo Inoue
  • Patent number: 5856913
    Abstract: A semiconductor power module has semiconductor components mounted on a substrate. The semiconductor components are in electrical contact with the substrate. Internal circuit wiring is achieved by using one or more flexible circuit boards. The flexible circuit board(s) contact the semiconductor components and also provide external connection elements. Hermetical encapsulation is achieved by lamination, and height equalization of the different circuit regions is achieved by using geometrically preformed prepregs in conjunction with the flexible circuit board and the substrate.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: January 5, 1999
    Assignee: Semikron Elektronik GmbH
    Inventor: Heinrich Heilbronner
  • Patent number: 5851646
    Abstract: The present invention provides a lightweight prepreg having uniform formation, low linear thermal expansion coefficient and good mechanical strength, comprising a porous para-oriented aromatic polyamide film and a thermoplastic resin and/or a thermosetting resin, the porous para-oriented aromatic polyamide film being impregnated with the thermoplastic resin and/or the thermosetting resin, a process for producing the same, and a printed circuit substrate/board using the same.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: December 22, 1998
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tsutomu Takahashi, Yoshifumi Tsujimoto, Hiroaki Kumada, Hiroyuki Sato
  • Patent number: 5848462
    Abstract: An insulating film 3 is provided with an opening 4 whose size is substantially equivalent to or slightly smaller than the outer configuration of electronic component 5. A conductive pattern 2 is formed on insulating substrate 1. After forcibly inserting the main body of electronic component 5 into said opening 4, terminals 6 are put between insulating film 3 and insulating substrate 1 and disposed in such a manner that terminals 6 are brought into contact with conductive pattern 2. Then, insulating film 3 is connected with insulating substrate 1 by fusing them in a region surrounding terminals 6, thereby firmly fixing terminals 6 of electronic component 5 on conductive pattern 2.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: December 15, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Sera, Hideki Mitsuoka, Yoshiro Sano, Tetsutaro Nasu
  • Patent number: 5840402
    Abstract: A metallized laminate material for the manufacture of high performance, high density printed wiring boards and the like includes an ordered distribution of via holes electrically interconnecting opposing conductive layers on a dielectric polymeric film substrate. Furthermore, opposing photoresist layers substantially cover the conductive layers and vias. The conductive material in the conductive layers and the vias is bonded adhesivelessly to the substrate to provide a high degree of delamination resistance. The production of metallized laminate material is preferably carried out in a roll-to-roll process suitable for high volume, low cost production. In use, an end user may manufacture customized printed wiring boards in small volume runs from the laminate material with a reduced amount of equipment, expertise and cost.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: November 24, 1998
    Assignee: Sheldahl, Inc.
    Inventors: Sidney J. Roberts, Eugene T. Selbitschka, Glenn W. Gengel, Brent N. Sweitzer
  • Patent number: 5837367
    Abstract: The invention relates to a memory card and its method of manufacture. The memory card has a flexible composite substrate formed from a top film, a base film, and an adhesive layer deposited between and bonding together the base film and the top film. Preferably, the thickness of such composite substrate is between 8 and 12 mils. A layer of metal is adhered to the exposed surface of the top film. A circuit layer is provided to form at least one site on the memory card which is readable by an external reading device. A protective layer is provided to overlie and protect the circuit layer of the memory card.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: November 17, 1998
    Assignee: Interprint Formularios Ltda.
    Inventors: Fernando Ortiz, Jr., James T. Faris
  • Patent number: 5834101
    Abstract: A metal base board comprising a metal plate, a circuit conductor section, and an insulating layer provided between the circuit conductor and the metal plate wherein the insulating layer comprises an organic insulating material with flaky inorganic fillers added therein and the flaky inorganic fillers are stacked in the insulating layer in a stratified state.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Satoru Hayashi
  • Patent number: 5827605
    Abstract: The present invention provides a multilayer ceramic substrate and a method of producing the same which can prevent occurrence of cracks when laminating different ceramic substrates or due to subsequent heat shock, and which has excellent moisture resistance and insulation properties and high reliability. The ceramic multilayer substrate has two ceramic substrates of different thermal expansion coefficients laminated by at least two glass layers of different thermal expansion coefficients which are between the thermal expansion coefficients of the ceramic substrates so that the thermal expansion coefficient changes stepwise between the ceramic substrates. The differences in thermal expansion coefficient between the ceramic substrate and the glass layer which are adjacent to each other, and between the adjacent glass layers are preferably not more than 1.times.10.sup.-6 /.degree. C.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: October 27, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuyoshi Nishide, Hiroji Tani
  • Patent number: 5828555
    Abstract: A multilayer printed-circuit board includes at least one inner-layer signal line, first and second ground layers between which the inner-layer signal line is sandwiched via a frame member made of an insulating material in a thickness direction of the multilayer printed-circuit board, and metallic wall members which are provided on inner walls of slits formed in the frame member and extending along the inner-layer signal line. The first and second ground layers and the metallic wall members shielding the inner-layer signal line.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: October 27, 1998
    Assignee: Fujitsu Limited
    Inventor: Takumi Itoh
  • Patent number: 5818697
    Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gregg Joseph Armezzani, Robert Nicholas Ives, Mark Vincent Pierson, Terry Alan Tull
  • Patent number: 5814393
    Abstract: A raw material plastic film like a band stretched in two directions with a machine direction as a longitudinal direction of stretch and a transverse direction as a lateral direction of stretch is prepared. One standard line parallel with the machine direction of stretch is assumed on a film face of the raw material plastic film. An area due to cut a cover layer plastic film and an area due to cut a base layer plastic film (the two areas are of almost the same shape) are assumed to be on the standard line in a state in which the areas are aligned in orientation. However, both an arbitrary point of the area due to cut and the point of the area due to cut corresponding thereto need to be on the standard line. A cover layer plastic film and a base layer plastic film are cut out from the two areas due to cut. Metal electric circuit is formed on a surface of the base layer plastic film via an adhesive layer. The metal electric circuit has a plastic deformation component of 0.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: September 29, 1998
    Assignee: Nitto Denko Corporation
    Inventors: Chiharu Miyaake, Toshihiko Sugimoto, Yousuke Miki
  • Patent number: 5796050
    Abstract: A circuit board assembly which includes a flexible printed circuit bonded to a substrate by an adhesive that is curable upon exposure to actinic radiation of a preselected wavelength is provided. The flexible circuit includes a dielectric layer made from a material that is transmissive to actinic radiation of a preselected wavelength and a conductive layer disposed on a surface of the dielectric layer. The conductive layer has an opening therethrough to allow passage of the actinic radiation through the flexible circuit. Preferably, the opening is in the region of the conductive layer that lacks metal tracings. The substrate of the assembly includes a top surface defining a mating region and a channel and a side surface defining a port that is in communication with the channel. The channel of the substrate is aligned and coincident with the opening of the conductive layer. The adhesive is disposed within the channel.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: August 18, 1998
    Assignee: International Business Machines Corporation
    Inventor: Jeffrey Scott Campbell
  • Patent number: 5789121
    Abstract: The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: Douglas Adam Cywar, Charles Robert Davis, Thomas Patrick Duffy, Frank Daniel Egitto, Paul Joseph Hart, Gerald Walter Jones, Edward McLeskey
  • Patent number: 5784782
    Abstract: A method for making a printed circuit with a cavity is disclosed. The method comprises the step of laying a sticker sheet on a first, metallized dielectric layer and laying a second, metallized dielectric layer on the sticker sheet. The second metallized dielectric layer and the sticker sheet each have a window which is registered with the other window forming a cavity. Next, a flexible release layer is laid above the second metallized dielectric layer and a thermosetting visco-plastic material is laid on the release layer over the cavity. Next, the first and second metallized dielectric layers, sticker sheet, release layer and visco-plastic material are laminated by heat and pressure to cure the sticker sheet and thereby bind the first and second metallized dielectric sheets to each other. During the lamination step, the sticker sheet flows to the perimeter of the cavity.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: July 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Christina Marie Boyko, Donald Seton Farquhar, Robert Maynard Japp, Michael Joseph Klodowski
  • Patent number: 5780145
    Abstract: A molding resin composition containing, in a resin, a filler comprising a globular powder of which mean particle diameter is not smaller than 0.1 .mu.m and not greater than 1.5 .mu.m (x component), a globular powder of which mean particle diameter is not smaller than 2 .mu.m and not greater than 15 .mu.m (y component) and a globular powder of which mean particle diameter is not smaller than 20 .mu.m and not greater than 70 .mu.m (z component), wherein proportions of the x, y and z components based on the total volume of x, y and z components are not smaller than 10% by volume and not greater than 24% by volume, not smaller than 0.1% by volume and not greater than 36% by volume and not smaller than 57% by volume and not greater than 76% by volume, exhibits an excellent fluidity even when loaded with a high percentage of filler. Further, their cured products are lowered in the moisture absorption and thermal expansion coefficient of which increases result from the resin itself present in the cured product.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: July 14, 1998
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasuhiro Hirano, Masatsugu Akiba, Yutaka Shiomi, Noriaki Saito
  • Patent number: 5776662
    Abstract: To inhibit the migration of conductive layers in a multilayer chip carrier, e.g., a multilayer printed circuit board, an optically cured layer 13, which is an anti-migration layer, is formed in an insulating layer 12 located between a first conductive layer 8 and a second conductive layer 6. Such a structure is formed by thinning, e.g., grinding down, a first insulating layer, leaving about half the thickness of the first insulating layer. This first insulating layer is selectively optically irradiated with actinic radiation to form an optically cured layer. Via holes are etched into the non-irradiated portions of the first insulating layer. Thereafter, a second insulating layer is formed on the first insulating layer, and it too is selectively optically irradiated with actinic radiation. Via holes are etched into the non-irradiated portions of the second insulating layer, directly over the via holes in the first insulating layer, and the second insulating layer is also thinned.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: July 7, 1998
    Assignee: International Business Machines Corporation
    Inventors: Masaharu Shirai, Yutaka Tsukada
  • Patent number: 5774342
    Abstract: Thin circuit pathways of an electronic circuit are integral with thick terminal pins. The thin and thick portions are stamped, formed and chemically etched from a single sheet of copper or copper alloys, and mounted on a substrate to eliminate the need of a separate header. Components are soldered to the thin pathways in the conventional manner and a housing is molded to the circuit or a preformed housing is attached to the circuit. In another embodiment, a filtered header which contains thin circuit pathways integral with thick terminal pins is formed in the same manner and includes filtering components.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: June 30, 1998
    Assignee: Delco Electronics Corporation
    Inventors: Scott David Brandenburg, Jeffery Ralph Daanen