Printed Circuit Board Patents (Class 361/748)
  • Patent number: 10342116
    Abstract: A high-frequency module includes a wiring board; a plurality of components mounted on an upper surface of the wiring board; a sealing resin layer that is stacked on the upper surface of the wiring board and that has a step; a groove that is formed in the sealing resin layer to intersect with the step when the wiring board is viewed in plan view, and that extends between predetermined components; and a shield wall disposed in the groove and formed with a conductor. The groove includes a first portion at an upper surface side of the wiring board and a second portion at an upper surface side of the sealing resin layer, the second portion being continuous from the first portion. An area of the second portion is larger than an area of the second portion.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yoshihisa Masuda
  • Patent number: 10334082
    Abstract: An extremely high frequency (EHF) protocol converter may include a transducer, an EHF communication circuit, a protocol conversion circuit, and a circuit port. The transducer may be configured to convert between an electromagnetic EHF data signal and an electrical EHF signal. The EHF communication circuit may be configured to convert between a baseband data signal and the electrical EHF signal. The protocol conversion circuit may be adapted to convert between the baseband data signal having data formatted according to a first data protocol associated with a first external device and a second baseband data signal having data formatted according to a second data protocol associated with a second external device. The second data protocol may be different from the first data protocol. The circuit port may conduct the second baseband data signal to the second external device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 25, 2019
    Assignee: Keyssa, Inc.
    Inventors: Gary D. McCormack, Roger Isaac, Eric Almgren
  • Patent number: 10321574
    Abstract: An electronic component-embedded substrate includes a core substrate, a cavity penetrating the core substrate, a wiring layer formed on one surface of the core substrate, a support pattern extending over the cavity and configured to divide the cavity into a plurality of component embedding areas, an insulation wall portion arranged on a part of the support pattern in the cavity and formed of the same material as the core substrate, a plurality of electronic components each of which is mounted in each of the plurality of component embedding areas, and an insulating material filling an inside of the cavity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 11, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junji Sato, Katsuya Fukase
  • Patent number: 10306757
    Abstract: A circuit board includes an insulation layer, a signal line formed over the insulation layer and extending in a direction X, and a conductor layer formed under the insulation layer. The insulation layer has periodic dielectric-constant distribution in a direction Y orthogonal to the direction X. The conductor layer includes a slit at a position corresponding to the signal line. The slit expands an electric field produced between the signal line and the conductor layer; causes less difference in dielectric constants of the insulation layer in the vicinity of the signal line (the difference is caused by the positional relationship between the signal line and the dielectric-constant distribution of the insulation layer); and reduces difference in signal transmission speeds caused by the positional relationship.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 28, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Taiga Fukumori
  • Patent number: 10297275
    Abstract: An apparatus according to one embodiment includes a module having an array of first read transducers each having a tunnel valve structure and a second read transducer coupled to the array of first read transducers, the second read transducer having a tunnel valve structure. The apparatus also includes a controller, and a cable coupling the read transducers to the controller, thereby forming a plurality of circuits extending from the controller, each circuit corresponding to one of the transducers. Resistances of the circuits are about the same.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Robert E. Fontana, Jr., Calvin S. Lo
  • Patent number: 10290697
    Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10277116
    Abstract: This on-vehicle power conversion apparatus is provided with: a power conversion circuit to which DC power is inputted; and a noise reduction unit that is configured to reduce common-mode noise and normal-mode noise which are included in the DC power and that is provided to the input side of the power conversion circuit. The noise reduction unit is provided with: a core having a first core part and a second core part; a common-mode chalk coil having a first winding wire wound around the first core part and a second winding wire wound around the second coil part; and a smoothing capacitor that constitutes a low-pass filter circuit cooperatively with the common-mode chalk coil. The power conversion apparatus is further provided with a damping unit provided at a position intersecting the magnetic path of a magnetic flux leakage.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 30, 2019
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Atsushi Naito, Fumihiro Kagawa, Yoshiki Nagata, Shunsuke Ambo, Keiji Yashiro, Kazuhiro Shiraishi
  • Patent number: 10271432
    Abstract: To reduce, when a single encapsulated circuit module has electronic components that are mutually influenced by their electromagnetic waves, the mutual influence, an embodiment provides an encapsulated circuit module M having a substrate 100 on which a number of electronic components 200 are mounted. An electronic component 200A is a high frequency oscillator. A metal side wall 320 of a partition member is provided on the substrate 100. One surface of the substrate 100 is entirely covered with a first resin 400 together with the electronic components 200 and the side wall 320. The first resin 400 is covered with a metal shield layer 600 for shielding electromagnetic waves. The electronic component 200A is surrounded by the side wall 320 and the shield layer 600.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 23, 2019
    Assignee: MEEKO ELECTRONICS CO., LTD.
    Inventor: Satoru Miwa
  • Patent number: 10238016
    Abstract: A chassis includes a flash module comprising a cover and an integrated connector, a metal stiffener, an electromagnetic interference (EMI) gasket, and a midplane. The flash module is connected to the midplane using the integrated connector, the integrated connector extends past the cover of the flash module, and, when the flash module is connected to the midplane, the cover of the flash module is in direct contact with the EMI gasket, in which the metal stiffener is interposed between the EMI gasket and the midplane.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Christopher Frank, Timothy Olesiewicz, Clifford Willis
  • Patent number: 10192691
    Abstract: An electricity storage unit of the present disclosure includes: electricity storage device; holder for holding this electricity storage device; bottomed tubular case for housing electricity storage device and holder; and cover for covering opening of case. At least a part of cover is inserted into case. With this configuration, since a surface on which a joint between cover and case is formed can be disposed on an opening side of case, it is possible to suppress intrusion of a foreign substance, such as a water droplet.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 29, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kiyoshi Wakinaka, Yohsuke Mitani, Kazuki Morita
  • Patent number: 10194519
    Abstract: Provided is a chip mounter, an electronic circuit substrate, and a power module, where the chip mounter prevents foreign substances from a chip-mounter installation environment, dust generated from members, and dust generated from the chip mounter, thereby preventing failures caused by the foreign substances. The chip mounter takes out a chip component accommodated in a packing tape. The packing tape has a pocket. The pocket has a bottom surface provided with a through hole. The chip mounter includes a tape travelling rail, a sucking-and-mounting arm, and a cavity cleaning mechanism. The cavity cleaning mechanism includes an intake hole disposed upstream of a suction point, in a location of the tape travelling rail, on which the carrier tape with a cover tape attached thereto travels so as to overlap the through hole. The cavity cleaning mechanism takes in the inside of the pocket through the intake hole and the through hole.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuya Ueda, Takahiko Anan
  • Patent number: 10175810
    Abstract: A touchscreen panel includes touch sensors on a base film and routing wires connected to the touch sensors, wherein the base film has a main area and a tail area protruding from the main area, the main area includes an active region where the touch sensors are placed and a bezel region located on the outside of the active region, and the routing wires pass through the bezel region and the active region, and connect terminals provided at one end of the tail area and the touch sensors.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 8, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sunggon Hong, Jaedo Lee, Namseok Lee, Dongjoong Cha
  • Patent number: 10158187
    Abstract: A conductor module attachment structure includes a case having a connection conductor, a recessed groove that is provided protrusively on an outer wall of the case, a protector that extends along the recessed groove and is formed into a U-shape and that is configured that an opening portion of a U-groove of the protector is closed by an inner wall face of the recessed groove when the protector is inserted into the recessed groove, a voltage detecting line that is routed in the U-groove of the protector, a voltage detecting terminal that is connected to one end of the voltage detecting line, a terminal retaining portion that is provided on the protector and positions the voltage detecting terminal contactably with the connection conductor.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 18, 2018
    Assignee: YAZAKI CORPORATION
    Inventor: Takahiro Chaen
  • Patent number: 10129972
    Abstract: An apparatus, includes a substrate, an electronic component disposed over the substrate, and a frame element disposed over the substrate. The frame element provides structural rigidity to the apparatus. The apparatus also includes an encapsulating material disposed over an upper surface of the substrate, the electronic component and the frame element. An electrically conductive layer is disposed over the encapsulating material.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 13, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Martin Fritz, Bernhard Gebauer, Lueder Elbrecht, Martin Handtmann, Oliver Wiedenmann, Sergej Scherer
  • Patent number: 10115540
    Abstract: An electronic device includes a support member, an ornamental member that is assembled to face one face of the support member, and an operating member that is disposed on the support member to be partially exposed to the outside through the ornamental member. The operating member includes a body that is positioned on one face of the support member to be exposed through the ornamental member, and at least one pair of fastening pieces, each of which extends from the body to be fastened to the support member. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kyung-Pil Kim, Myung-Hyo Bae, Sang-Hun Park, Jong-Hyun Lee, Ju-Ho Yi
  • Patent number: 10095280
    Abstract: A chassis includes a midplane defining a plurality of expansion sockets on one side and one or more motherboard sockets on the other. A modular motherboard is removably inserted in the chassis and engages the one or more motherboard sockets. An expansion card may engage with one or more of the motherboard sockets simultaneously. The expansion sockets are arranged in a coplanar and collinear manner to enable a planar expansion card to simultaneously insert within multiple expansion sockets. The motherboard allocates lanes to the expansion card in response to detecting a number of sockets occupied by the expansion card.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 9, 2018
    Assignee: Ciena Corporation
    Inventors: Raleigh Bettiga, Colin Wilson, Wayde Jaskela
  • Patent number: 10070542
    Abstract: An electronic circuit unit in which a mold exclusion part, having a rear surface side covered by mold resin and a front surface side exposed from an outer case, is provided at a part of a plate surface of a circuit board which is mounted with electronic components and is covered by the outer case formed by the mold resin. The outer case is multi-material molded using plural kinds of resin having different fluidities. A rear wall of the outer case located on the rear surface side of the mold exclusion part is made of one of the plural kinds of the resin having a fluidity higher than a fluidity of another one of the plural kinds of the resin constituting the other portion of the outer case.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 4, 2018
    Assignee: YAZAKI CORPORATION
    Inventor: Ken Ito
  • Patent number: 10037938
    Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keung Beum Kim, Hyunjong Moon, Seung-Yong Cha
  • Patent number: 10034380
    Abstract: An intermediate connection layer interposed between a wiring substrate and an electronic part includes a rigid substrate and a flexible substrate. A plurality of conductor portions are formed on opposed principal surfaces of the respective flexible and rigid substrates. The rigid substrate is provided with an opening, and a fuse portion on the flexible substrate faces the opening. The flexible substrate and the rigid substrate are bonded together with solders. The respective rigid and flexible substrates are separately made, solder pastes are applied to the rigid substrate, both substrates are overlaid on each other, and the solder pastes are heated and solidified to make the intermediate connection layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 24, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroki Sakamoto
  • Patent number: 10024345
    Abstract: A mounting device for fastening a printed circuit board onto a carrier is disclosed. The mounting device comprises at least one bolt that can be screwed onto the printed circuit board, having at least one fastening wing, wherein the fastening wing has at least one interlocking component. Furthermore, the mounting device comprises at least one bolt receiver that is or can be integrated in the carrier. The bolt is or can be disposed in the bolt receiver such that it can be displaced in the direction of a displacement axis that is oriented substantially perpendicular to a main extension plane of the printed circuit board. The bolt receiver comprises at least one groove for receiving at least one subsection of the fastening wing having the interlocking component. The interlocking component is designed to interlock in the groove when the bolt disposed in the bolt receiver is subjected to a predetermined torque.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: July 17, 2018
    Assignee: ZF Friedrichshafen AG
    Inventor: Karl-Heinz Müller
  • Patent number: 10026660
    Abstract: A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 17, 2018
    Assignee: VEECO PRECISION SURFACE PROCESSING LLC
    Inventors: Laura Mauer, John Taddei, John Clark, Elena Lawrence, Eric Kurt Zwirnmann, David A. Goldberg, Jonathan Yutkowitz
  • Patent number: 10021790
    Abstract: A module includes a PCB including a substrate, a component pad and at least one wire pad, an SMT component mounted to a component pad, a wire fence, a mold compound and a top conductive layer. Each wire pad is connected to ground by a corresponding via extending through the substrate, and the wire fence includes wire loops connected to each wire pad. The mold compound is disposed over the PCB, the SMT component and the wire fence, and defines multiple holes extending partially through the mold compound to top-edges of the wire loops, respectively, where a conductive material fills the holes. The top conductive layer is disposed over the mold compound, and is in electrical contact with the conductive material filling the holes. The wire fence, the conductive material, and the top conductive layer provide shielding of the SMT component from electromagnetic radiation.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 10, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jin Jeong, Chris Chung, Nitesh Kumbhat, Ashish Alawani
  • Patent number: 10021368
    Abstract: A mobile terminal including a front body including a touch screen located on a front side of the mobile terminal; a rear body located at a rear side of the mobile terminal, the rear body including at least one hole; a bracket accommodated between the front body and the rear body, the bracket formed as a unibody, the bracket including third and fourth holes corresponding to the at least one hole; a first camera coupled with the bracket, the first camera positioned at the third hole of the bracket; a second camera coupled with the bracket, the second camera positioned at the fourth hole of the bracket; a camera flash positioned between the first and second cameras; a main printed circuit board (PCB) including electronic components and electronic circuits for operation of the mobile terminal; a camera PCB coupled with the first and second cameras; and a connector extended from the camera PCB and electrically connected to the main PCB.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 10, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Ramchan Woo, Byungjoon Kim, Jinho Jang, Chiyoung Kim, Jaeyeol Kim
  • Patent number: 9991291
    Abstract: An array substrate is disclosed, which includes a display region and a drive circuit region; the drive circuit region includes GOA units, the GOA unit including a substrate, a gate electrode layer, an insulation layer, an active layer and a source/drain electrode layer, and the drive circuit region further includes a gate wire connecting to the gate electrode layer, and a source/drain layer wire at the same layer with the source/drain electrode layer, wherein the area between the portions of the gate wire and the source/drain layer wire which intercross with each other is only formed with the insulation layer. A manufacturing method of an array substrate and a display apparatus including the array substrate is further disclosed.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 5, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhilian Xiao, Haisheng Zhao, Chong Liu, Zhilong Peng
  • Patent number: 9986082
    Abstract: An interface device and method between an electronic device and an external device using an ear jack of a smart device are disclosed in order to implement an interface that is capable of automatically recognizing an ear jack insertion type appcessory. The interface device includes: an electronic device including an ear jack including a plurality of audio signal input and output terminals; an external device including an interface unit including a connector unit configured to be inserted into the ear jack, the connector unit including a plurality of terminals that correspond to the plurality of audio signal input and output terminals provided in the ear jack of the electronic device, respectively; and a recognizing unit on the connector unit of the interface unit configured to recognize whether the external device is connected to the ear jack of the electronic device through a plurality of detections.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changsu Lee, Sungsoo Moon, Kemsuk Seo, Bongjae Rhee, Sangmoon Lee
  • Patent number: 9960501
    Abstract: The present invention presents an electronic device. The electronic device includes a socket and a supplementary antenna. The socket is disposed on the electronic device, wherein the socket includes an accommodating portion for accommodating an external wireless communication module inserted from the outside. The supplementary antenna is disposed in the electronic device, wherein when the wireless communication module is completely inserted into the accommodating portion, the main antenna of the wireless communication module and the supplementary antenna become electromagnetically coupled; and wherein when the wireless communication module is completely inserted into the accommodating portion, the electronic device transmits/receives wireless signals using the main antenna and the supplementary antenna together.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 1, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Tsung-Ying Hsieh, Li-Cheng Shen, Chung-Ting Hung
  • Patent number: 9920231
    Abstract: Provided is a thermal compound composition having heat dissipation and electrical insulation properties, where the thermal compound composition includes a Cu—CuO composite filler having a Cu core and a shell composed of CuO having a whisker crystal structure. The CuO having the whisker crystal structure is prepared by reacting Cu particles in a basic solution so that an outer shell thereof is grown into whisker-shaped CuO.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: March 20, 2018
    Assignee: YOUNGYIEL PRECISION CO., LTD.
    Inventors: Dong-Wook Chu, Jae-Uk Chu, Dong-Woo Lee, Chang-Hyun Um
  • Patent number: 9888586
    Abstract: According to embodiments, an electronic device includes: a housing including a face facing a first direction; a circuit board including first and second board faces substantially parallel to the face, and a side board face facing a second direction, the circuit board disposed within the housing; a first component disposed in a first region of the first board face; a second component disposed in a second region of the second board face overlapping with the first region; a first shield including a first side wall formed facing the second direction, the first shield covering the first region; a second shield including a second side wall formed facing the second direction, the second shield covering the second region; and a bonding material formed between the first side wall or second side wall and the side board face. The electronic device as described above may be variously implemented according to embodiments.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Je Bang, Yong-Won Lee, Jeong-Ung Kim, Jae-Heung Ye
  • Patent number: 9848499
    Abstract: A method of producing a printed circuit board (10) with a plurality of inlays (21, 22, 23, 24), having the following steps: supplying a plurality of inlays (21, 22, 23, 24), of which at least one inlay has at least one positioning element (21.1, 21.2; 22.1 to 22.7; 23.1, 23.2; 24.1, 24.2); building up a layer sequence from a plurality of printed-circuit-board layers, with at least one recess (14) for accommodating inlays, wherein, prior to the step of the plurality of inlays (21, 22, 23, 24) being inserted, the recess (14) is defined in an uppermost layer (12) by a frame made of non-conductive printed-circuit-board material; inserting the plurality of inlays (21, 22, 23, 24) into the recess (14) defined by the frame; covering the inlays (21, 22, 23, 24) with a non-conductive printed-circuit-board material; laminating the layer sequence, and removing at least the positioning elements (21.1, 21.2; 22.1 to 22.7; 23.1, 23.2; 24.1, 24.2) which establish a conductive contact between neighboring inlays.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: December 19, 2017
    Assignees: SCHWEIZER ELECTRONIC AG, CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Thomas Gottwald, Bernd Reisslöhner, Thomas Rall, Roland Brey, Gerald Hauer, Tobias Steckermeier
  • Patent number: 9836095
    Abstract: Microelectronic devices including an electromagnetic shield over a desired portion of a substrate. The magnetic shield is formed of conductive particles within a selectively curable layer, such as a solder resist material. After application to the substrate, the conductive particles are allowed to settle to form a conductive structure to serve as an electromagnetic shield. The electromagnetic shield can be formed primarily over regions of the substrate containing conductive traces coupled in the package to communicate signals presenting a risk of causing electromagnetic interference with other devices.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Eng Huat Goh, Khang Choong Yong, Boon Ping Koh, Wil Choon Song
  • Patent number: 9823846
    Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Dexter Tamio Chun, Suryanarayana China Chittuluri, Yanru Li
  • Patent number: 9786747
    Abstract: A wiring substrate includes an insulation layer having an electronic component mounting area, and a wiring layer embedded in the insulation layer, the wiring layer having a first surface exposed from the insulation layer, to which a terminal of an electronic component is to be connected, a second surface opposite to the first surface, which is covered by the insulation layer, and a side surface. The second surface has a roughened surface and the side surface has a roughened surface, and a surface roughness of the second surface of the wiring layer is greater than a surface roughness of the side surface.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 10, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Hironari Kojima
  • Patent number: 9786577
    Abstract: A power-module substrate including a circuit layer having a first aluminum layer bonded on one surface of a ceramic substrate and a first copper layer bonded on the first aluminum layer by solid-phase-diffusion bonding, and a metal layer having a second aluminum layer made from a same material as the first aluminum layer and bonded on the other surface of the ceramic substrate and a second copper layer made from a same material as the first copper layer and bonded on the second aluminum layer by solid-phase-diffusion bonding, in which a thickness t1 of the first copper layer is 1.7 mm to 5 mm, a sum of the thickness t1 of the first copper layer and a thickness t2 of the second copper layer is 7 mm or smaller, and a ratio t2/t1 is larger than 0 and 1.2 or smaller except for a range of 0.6 to 0.8.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: October 10, 2017
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 9767961
    Abstract: The present invention relates to a composite electronic component having a dielectric body portion inside of which a conductive body is provided, and a magnetic body portion inside of which a conductive body is provided. In the present invention, a layer made of a metal material is arranged between the dielectric body portion and the magnetic body portion as an intermediate layer.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 19, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Naoto Ohira, Natsumi Shimogawa, Hirofumi Yamaguchi, Tsutomu Nanataki
  • Patent number: 9742086
    Abstract: A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The flexible printed wiring board (1) further includes reinforcement layers (31, 32) that are disposed at the other surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component, and that are formed integrally with the wirings (9).
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: August 22, 2017
    Assignees: FUJIKURA LTD., DDK LTD.
    Inventors: Yuki Ishida, Masayuki Suzuki, Yuki Nakano, Harunori Urai, Norifumi Nagae
  • Patent number: 9723724
    Abstract: A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: August 1, 2017
    Assignee: Sony Corporation
    Inventors: Shun Mitarai, Shusaku Yanagawa, Shinji Rokuhara, Shuichi Oka
  • Patent number: 9717146
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 25, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Patent number: 9655241
    Abstract: A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The flexible printed wiring board (1) further includes reinforcement layers (31, 32) that are disposed at the other surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component, and that are formed integrally with the wirings (9).
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 16, 2017
    Assignees: FUJIKURA LTD., DDK LTD.
    Inventors: Yuki Ishida, Masayuki Suzuki, Yuki Nakano, Harunori Urai, Norifumi Nagae
  • Patent number: 9653385
    Abstract: A lead frame has a metal base, a silver-plated layer, and a silver oxide layer. The silver-plated layer is formed between the metal base and the silver oxide layer. The silver oxide layer has a polar outer surface and a thickness of equal to or more than 1.3 nanometers. The silver oxide layer is beneficial to increase the adhesive strength between the lead frame and the molding compound and avoid delamination of the molding compound from the lead frame, so the lead frame of the present invention can pass a more severe moisture sensitivity level when exposed to the environment.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: May 16, 2017
    Assignee: SDI Corporation
    Inventor: Ya-Cheng Fang
  • Patent number: 9635752
    Abstract: The present disclosure relates to the field of circuits, and provides a printed circuit board (PCB) and an electronic device. The PCB includes a substrate and a wiring layer arranged at the substrate. The wiring layer includes a digital region and an analog region, and a gap region is defined between the digital region and the analog region. The substrate is provided with a hole in the gap region, and the digital region and the analog region of the wiring layer are connected through a magnetic bead.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yue Wu, Yan Ren, Zifeng Wang
  • Patent number: 9598776
    Abstract: Micron-sized metal particles in an ink or paste composition are deposited onto a substrate and then photosimered. The substrate may comprise a polymeric material. The polymeric substrate may have a coefficient of thermal expansion greater than two times the coefficient of thermal expansion of the photosimered ink or paste composition.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 21, 2017
    Assignee: PEN Inc.
    Inventors: Ovadia Abed, Valerie Kaye Ginsberg, James P. Novak
  • Patent number: 9601853
    Abstract: A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The wirings (9, 11) are disposed at the other surface side of the base substrate (3). The flexible printed wiring board (1) further includes reinforcement layers (31, 32) that are disposed at the one surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component, and that are formed integrally with the pads (15a).
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: March 21, 2017
    Assignees: FUJIKURA LTD., DDK Ltd.
    Inventors: Yuki Ishida, Masayuki Suzuki, Yuki Nakano, Harunori Urai, Norifumi Nagae
  • Patent number: 9570795
    Abstract: A multi-functional, multi-layer film or skin which may be used as a covering for a structure or platform incorporates an integrated photovoltaic element and an integrated RF antenna element. The film or skin is suitable for use in various applications, including those involving autonomous, self-powered, mobile communication systems and especially for use as a skin or covering for solar powered aircraft and UAVs. Planar PV cells and planar RF antenna are used to facilitate their integration into the film or skin. The PV cells and RF antenna are configured to face operate outward from opposite faces of the skin. The film or skin addresses potential problems arising from conflicting directional requirements for PV orientation and antenna pointing on mobile platforms. This is accomplished by employing wide angle AR coatings on the PV elements and electrical controls to steer the RF antenna.
    Type: Grant
    Filed: November 30, 2014
    Date of Patent: February 14, 2017
    Assignee: SUNLIGHT PHOTONICS INC.
    Inventors: Allan James Bruce, Sergey Frolov, Michael Cyrus
  • Patent number: 9538661
    Abstract: An electronic device module includes a wiring board having a first surface including first and second electrodes formed thereon and a second surface opposite to the first surface, a supporting member attached to the second surface of the wiring board, a first electronic unit mounted on the first surface of the wiring board and electrically connected to the first electrode, and a second electronic unit mounted on the first surface of the wiring board and electrically connected to the second electrode. The wiring board includes a wiring extending from the first electronic unit to a position closer to the second electronic unit, and a reinforcement layer disposed between the first and second electronic units and apart from the wiring in a thickness direction of the wiring board.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Yamamoto, Keiko Kaji, Kota Tokuda, Takahisa Funayama
  • Patent number: 9502565
    Abstract: A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuo-Cheng Ching
  • Patent number: 9497849
    Abstract: A printed wiring board includes a core substrate, first and second buildup structures on surfaces of the core, respectively, and first and second solder-resist layers on the first and second structures, respectively. The core includes insulative substrate, conductive layers on surfaces of the substrate and through-hole conductor connecting the conductive layers, the first structure includes interlayer insulation layer and conductive layer in the first structure, the second structure includes interlayer insulation layer and conductive layer in the second structure, a thickness between the outer surfaces of the first and second solder-resist layers is set in range of from 150 ?m or greater and less than 380 ?m, and at least one of the core, first and second structures, and first and second solder-resist layers includes reinforcing material in amount such that the board includes the material in amount in range of from 20 to 35 vol. %.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 15, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Furusawa
  • Patent number: 9465267
    Abstract: A display device includes: a substrate; electrode terminals for external connection; an insulating film on the respective electrode terminals, the insulating film provided with openings which expose part of the respective electrode terminals, the insulating film covering the other portion of the respective electrode terminals; surface conductive films which are disposed so as to correspond to the respective openings, and are connected to part of the respective electrode terminals; and a circuit board disposed so as to oppose the substrate, the circuit board including circuit electrode terminals which are connected to the surface conductive films through a conductive bonding member so as to oppose the respective openings, the surface conductive films extending from an inside of an opening corresponding thereto to a surface of an insulating film corresponding thereto, peripheral edges of the respective surface conductive films being positioned beyond a peripheral edge of a circuit electrode terminal correspondi
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 11, 2016
    Assignee: Kyocera Corporation
    Inventors: Minoru Shibano, Ryoichi Yokoyama
  • Patent number: 9459747
    Abstract: A display device includes an array of display pixels having display pixel apertures that are periodic along two orthogonal directions, x and y, at spatial frequencies fx and fy, respectively. An array of electrodes is overlaid on the array of display pixel apertures. The array of electrodes is comprised of a metal mesh having openings that are periodic along a first direction u at an angle ?u relative to x, and along a second direction v at an angle ?v relative to y, and at spatial frequencies fu and fv. The array of electrodes is overlaid on the array of display pixels such that the parameter set {?u, fx, fu, ?v, fy, fv} satisfies specific geometric criteria in order to minimize perceptible moiré patterns.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 4, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Sean M. Donnelly, Jason D. Wilson
  • Patent number: 9455209
    Abstract: A circuit module includes: a wiring substrate including a mounting surface having first and second areas and a terminal surface on the other side of the mounting surface; a plurality of electronic components mounted on the first and second areas; a sealing layer that covers the plurality of electronic components, is formed of an insulation material, and includes a groove portion formed along a boundary between the first and second areas; a conductive shield including a first shield portion that covers an outer surface of the sealing layer and a second shield portion provided in the groove portion; and a conductive layer including a wiring portion that is provided on the mounting surface and electrically connects the terminal surface and the second shield portion, and a thickening portion that is provided in the wiring portion and partially thickens a connection area of the wiring portion with the second shield portion.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 27, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Eiji Mugiya, Masaya Shimamura, Kenzo Kitazaki, Takehiko Kai
  • Patent number: 9455228
    Abstract: This is directed to self-shielded components and methods for making the same. A self-shielded component can include an electromagnetic interference (EMI) shield that contains circuitry within a shielded space defined by the EMI shield. Self-shielding can be achieved by interfacing a conformal shield layer to a ground layer disposed on or within a substrate of the self-shielded component. The combination of the conformal shield layer and the around layer can form a boundary of the shielded space that envelops circuitry requiring shielding. This enables the self-shielded component to be mounted to a circuit board without requiring a shield can or other processing to impart EMI shielding. In addition, the self-shielded components include the benefits of EMI shielding while simultaneously decreasing space requirements.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: September 27, 2016
    Assignee: APPLE INC.
    Inventors: Altan N. Yazar, Kiavash Baratzadeh, Michael J. Reilly, Sean A. Mayo