Printed Circuit Board Patents (Class 361/748)
  • Patent number: 11139230
    Abstract: A flip-chip package substrate and a method for preparing the same in accordance with the present disclosure includes stacking a reinforcement layer on two opposing sides of a middle layer in order to increase the rigidity of the flip-chip package substrate, and promoting a thin middle layer, wherein the sizes of the end faces of conductive portions can be minimized according to needs. This increases the number of electrical contacts possible in a unit area and enables the creation of finer line pitch and higher layout density of the circuit portions, thereby satisfying the need for packaging of high integration/large scale chips while preventing warpage from occurring in the electronic packages.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 5, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11122682
    Abstract: Tamper-respondent assemblies and fabrication methods are provided which utilize liquid crystal polymer layers in solid form. The tamper-respondent assemblies include a circuit board, and an enclosure assembly mounted to the circuit board to enclose one or more electronic components coupled to the circuit board within a secure volume. The assembly includes a tamper-respondent sensor that is a three-dimensional multilayer sensor structure, which includes multiple liquid crystal polymer layers, and at least one tamper-detect circuit. The at least one tamper-detect circuit includes one or more circuit lines in a tamper-detect pattern disposed on at least one liquid crystal polymer layer of the multiple liquid crystal polymer layers. Further, a monitor circuit is provided disposed within the secure volume to monitor the at least one tamper-detect circuit of the tamper-respondent sensor for a tamper event.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. Busby, John R. Dangler, Mark K. Hoffmeyer, William L. Brodsky, William Santiago-Fernandez, David C. Long, Silvio Dragone, Michael J. Fisher, Arthur J. Higby
  • Patent number: 11011476
    Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 18, 2021
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Paolo Crema, J├╝rgen Barthelmes, Din-Ghee Neoh
  • Patent number: 11004782
    Abstract: A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yusuke Harada, Mamoru Yamagami
  • Patent number: 10998653
    Abstract: An edge connector includes a first row of golden fingers and a second row of golden fingers. The first row of golden fingers is adjacent to a plugging end of the edge connector, and the second row of golden fingers is adjacent to the first row of golden fingers. In a plugging direction of the edge connector, each golden finger in the first row of golden fingers has a first end proximate to the plugging end and a second end opposite to the first end. A first end of a grounded golden finger in the first row of golden fingers is protruded from other golden fingers, and second ends of two or more than two golden fingers in the first row of golden fingers are not aligned with each other.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 4, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Fei Yu, Shiping Cheng
  • Patent number: 10966341
    Abstract: A lightweight and low-cost electromagnetic pulse (EMP) protection rack includes a front door, a rear door disposed to face the front door, a left outer wall disposed between the front door and the rear door, a right outer wall disposed to face the left outer wall, a top outer wall positioned on top parts of the front door, the rear door, the left outer wall, and the right outer wall, a bottom outer wall disposed to face the top outer wall, and a main frame disposed to connect, into a single unit, the front door, the rear door, the left outer wall, the right outer wall, the top outer wall and the bottom outer wall, wherein at least one of the front door and the rear door is implemented as a roller blind having a shielding member.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 30, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kibaek Kim, Daeheon Lee, Minseok Yoon, Seungkab Ryu
  • Patent number: 10950687
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 16, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Patent number: 10945358
    Abstract: Provided is a flexible electromagnetic wave shielding material. An electromagnetic wave shielding material according to an embodiment of the present invention is implemented to include a conductive fiber web including a conductive composite fiber including a metal shell part covering an outside of a fiber part such that the conductive composite fiber forms multiple pores; and a first conductive component provided in at least some of the pores. The electromagnetic wave shielding material is so excellent in flexibility, elasticity, and creasing/recovery that the electromagnetic wave shielding material may be freely changed in shape, and can be brought in complete contact with a surface where the electromagnetic wave shielding material is intended to be disposed even if the surface has a curved shape such as an uneven portion or a stepped portion, thus exhibiting excellent electromagnetic wave shielding performance.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 9, 2021
    Assignee: Amogreentech Co., Ltd.
    Inventors: In Yong Seo, Ui Young Jeong, Jun Woo Lee
  • Patent number: 10886851
    Abstract: A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 5, 2021
    Assignee: Apple Inc.
    Inventor: Jay B. Fletcher
  • Patent number: 10886239
    Abstract: A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 5, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Hubert Teyssedre
  • Patent number: 10880999
    Abstract: A display panel includes: a display substrate having a display area, and a pad area disposed on at least one side of thereof; and a plurality of pad groups arranged on the pad area in a first direction and including: a first pad group having a plurality of first pads, at least some of the plurality of first pads have a first inclination with respect to a reference line extending in a second direction different from the first direction, and the plurality of first pads being spaced from each other at a first pitch; and a second pad group having a plurality of second pads, at least some of the plurality of second pads having a different second inclination with respect to the reference line, and the plurality of second pads being spaced from each other at a second pitch different from the first pitch.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-mo Chung, Tak-young Lee, Joosun Yoon
  • Patent number: 10865141
    Abstract: A synthetic quartz glass lid for use in optical device packages is prepared by furnishing a synthetic quartz glass lid precursor comprising a synthetic quartz glass substrate (1) and a metal or metal compound film (2), and forming a metal base adhesive layer (3) on the metal or metal compound film (2). The metal or metal compound film contains Ag, Bi, and at least one element selected from P, Sb, Sn and In.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 15, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Harunobu Matsui, Daijitsu Harada, Masaki Takeuchi
  • Patent number: 10802547
    Abstract: Apparatuses and associated methods for mounting PCBs and other electronics boards in portable medical equipment and/or other portable and non-portable electronic devices are disclosed herein. In some embodiments, the technology disclosed herein can provide PCB mounting systems that isolate the PCB from detrimental shock, vibration, and/or strain, while also providing electrical ground paths that greatly reduce EMI and other electrical disturbances. Some embodiments of the mounting systems described herein include both elastomeric (e.g., rubber) components and resilient metallic grounding members that, when assembled together, provide favorable shock mounting as well as robust electrical grounding without the inconvenience of using separate shock mounts, grounding straps, etc.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 13, 2020
    Assignee: FUJIFILM SONOSITE, INC.
    Inventor: Ken Dickenson
  • Patent number: 10786981
    Abstract: An automated masking system includes a substrate loading apparatus designed to hold a plurality of substrates, a first masking material application station designed to automatically apply a first masking material to a portion of the substrate, and a second masking material application station designed to automatically apply a second masking material to a portion of the substrate, the second masking material being different than the first masking material. The system includes a first dispensing apparatus and a second dispensing apparatus that move relative to the substrate in a repeatable motion. The substrate moves automatically from the first masking material application station to the second masking material application station.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 29, 2020
    Inventors: Robert Askin, Joshua Su, Melon Yu, Alex Anderson, Wei Li, Wan-Man Liu, Zhi-Guang Chen
  • Patent number: 10790222
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 29, 2020
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10763647
    Abstract: An assembly contains a housing defining an internal space of the assembly, an electronic circuit arranged in the internal space, and a protection strip arranged in the internal space for protecting the electronic circuit against external influences. Accordingly, the protection strip forms a ground conductor that is electrically connected to the housing and to a ground connection of the electronic circuit. Furthermore, a method for producing the assembly is disclosed.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 1, 2020
    Assignee: BIOTRONIK SE & Co. KG
    Inventor: Rolf Klenner
  • Patent number: 10765014
    Abstract: The present invention relates to a substrate unit and a substrate assembly, and a camera module using the same. The present invention may comprise: a first substrate part having rigidity; a second substrate part stacked on one surface of the first substrate part and having flexibility; a third substrate part extending outwardly from the second substrate part and having flexibility; and a reinforcing part which is disposed at a portion where the edge portions of the first substrate part and the third substrate part meet, the reinforcing part having a recessed portion which is formed by recessing the first substrate part inwardly so as to inhibit interference between the first substrate part and the third substrate part. The present invention is capable of resolving the interference between a rigid PCB and a flexible PCB and the tearing thereof by providing a reinforcing part in a connection portion of the rigid PCB and the flexible PCB.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 1, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyun Woo Ryou
  • Patent number: 10756003
    Abstract: A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Corning Incorporated
    Inventors: Daniel Wayne Levesque, Jr., Garrett Andrew Piech, Aric Bruce Shorey
  • Patent number: 10720277
    Abstract: Systems and methods are described for a ferrite arrangement that mitigates dimensional-tolerance effects on performance of a wireless charging pad, such as a WEVC pad. These systems and methods include a power-transfer structure having ferrite bars arranged to form ferrite strips in a staggered pattern to provide a path for magnetic flux induced by a magnetic field. The staggered pattern includes a series of ferrite strips that alternate defined starting-point locations at opposing sides of the power-transfer structure. Ending-point locations of the ferrite strips are not defined, but are based on an accumulation of lengthwise dimensional tolerances of the ferrite bars used to form the ferrite strips. Using the staggered pattern in a base power-transfer structure defines a coupling range for coupling with a vehicle power-transfer structure and a range limit for associated magnetic field emissions by the base power-transfer structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 21, 2020
    Assignee: WiTricity Corporation
    Inventors: Mickel Bipin Budhia, Chang-Yu Huang, Nicholas Athol Keeling, Michael Le Gallais Kissin
  • Patent number: 10680311
    Abstract: A communications terminal includes a mainboard, a conductor bezel, a first conductor part, and a second conductor part, where a first location on the conductor bezel is electrically connected to a ground terminal on the mainboard, a second location on the conductor bezel is electrically connected to a ground terminal on the mainboard, the second conductor part is electrically connected to a fourth location on the conductor bezel, and a radio frequency port on the mainboard is electrically connected to a third location on the conductor bezel using the first conductor part; and the fourth location and the third location on the conductor bezel are between the first location and the second location. The communications terminal is conducive to reducing antenna assembly complexity and reducing manufacturing costs.
    Type: Grant
    Filed: August 30, 2014
    Date of Patent: June 9, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shuhui Sun, Zhenghao Li, Huiliang Xu, Yi Fan, Bo Meng, Dongxing Tu
  • Patent number: 10656027
    Abstract: An electronic device includes a printed circuit board (PCB), a control circuit, and a sensing circuit. The control circuit is configured to determine whether over temperature occurs at one or more detecting points arranged at a first surface of the printed circuit board according to at least one voltage signal. The sensing circuit is arranged at a second surface opposite to the first surface of the printed circuit board and configured to sense the temperature of the one or more detecting points and correspondingly output the voltage signal to the control circuit.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 19, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shang-Feng Yang, Xin-Hung Lin
  • Patent number: 10622604
    Abstract: Provided herein are battery packs for electric vehicles. A battery pack can include a housing having cavities. The battery pack can include electrode structures having a first tab terminal and a second tab terminal. A cover can be disposed over the housing. The cover can include first junction connectors extending between a first surface of the cover and a second surface of the cover. The first tab terminal of each electrode structure can be welded to respective first junction connectors.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: April 14, 2020
    Assignee: SF Motors, Inc.
    Inventors: Ying Liu, Derek Nathan Wong, Chien-Fan Chen, Yifan Tang
  • Patent number: 10600640
    Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Stratio, Inc.
    Inventors: Woo-Shik Jung, Yeul Na, Youngsik Kim, Jae Hyung Lee, Jin Hyung Lee
  • Patent number: 10594122
    Abstract: A circuit board includes: a bus bar; a first prepreg that is overlaid on the bus bar; and a sheet-like leakage prevention portion that is overlaid on the surface of the first prepreg and suppresses leakage of the first prepreg to the outside.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 17, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Yukinori Kita
  • Patent number: 10558096
    Abstract: A circuit section of a display device is provided with a display element section on which a plurality of display elements are arranged at positions overlapped with a display region on which a display functional layer is formed, an input section for transmitting a signal for driving the display functional layer to the display element section and a lead-out wiring section for electrically connecting the display element section to the input section. Moreover, the lead-out wiring section is provided with a plurality of stacked wiring layers, and the plurality of wiring layers include a first wiring layer on which a plurality of first wirings having a first wiring width and a second wiring layer on which a plurality of second wirings having a first wiring width that is narrower than the first wiring width are formed.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 11, 2020
    Assignee: Japan Display Inc.
    Inventor: Nobuyuki Ishige
  • Patent number: 10546880
    Abstract: An array substrate includes a display region and a non-display region arranged adjacent to the display region. A plurality of signal connection lines is arranged at the non-display region, and each signal connection line is configured to connect a signal source and a signal line at the display region. At least one signal connection line includes a main line portion and at least one resistance adjustment portion connected in parallel to the main line portion.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 28, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianbo Xian, Jian Xu, Yong Qiao, Yongda Ma, Hongfei Cheng
  • Patent number: 10534494
    Abstract: A detection device includes a substrate; a plurality of first conductive thin wires provided in a plane parallel to the substrate and extending in a first direction; a plurality of second conductive thin wires provided in the same layer as that of the first conductive thin wires and extending in a second direction forming an angle with the first direction; first groups that are disposed in first strip-like regions respectively having a first width, each of the first groups including at least two of the first conductive thin wires displaced from one another in the second direction; and second groups that are disposed in second strip-like regions respectively having a second width, each of the second groups including at least two of the second conductive thin wires displaced from one another in the first direction.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 14, 2020
    Assignee: Japan Display Inc.
    Inventors: Koji Ishizaki, Hayato Kurasawa
  • Patent number: 10537024
    Abstract: A process for fabricating a printed circuit assembly is presented. The process includes providing a first base substrate having a first surface and a second surface opposite to the first surface; providing a flexible circuit layer including a first region having a first set of signal traces and a second region having a second set of signal traces, wherein the first region and the second region are separated by a first intermediate region; disposing the first region of the flexible circuit layer on the first surface of the first base substrate; bending the flexible circuit layer at the first intermediate region to surround a thickness side of the first base substrate; and disposing the second region of the flexible circuit layer on the second surface of the first base substrate. A printed circuit assembly is also presented.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 14, 2020
    Assignee: General Electric Company
    Inventor: Joseph Alfred Iannotti
  • Patent number: 10515906
    Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Patent number: 10514789
    Abstract: An integrated touch display panel and display device are disclosed. The integrated touch display panel comprises a touch emitting electrode array, a touch sensing electrode array, a black matrix, and color filters. The forward projection of any one of the touch sensing electrodes to the touch emitting electrode array at least partially overlaps with any one of the touch emitting electrodes. The black matrix comprises a plurality of black matrix rows and a plurality of black matrix columns. The color filters are separated by each of the black matrix rows and each of the black matrix columns, to form a plurality of array arrangements of display pixels. The touch sensing electrode is a mesh electrode, and the black matrix at least partially covers an orthogonal projection of the mesh electrodes to the black matrix.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 24, 2019
    Inventors: Xiaojing Zhan, Zhiwei Zheng, Wenqiang Yang, Kangpeng Yang, Ying Sun, Yumin Xu
  • Patent number: 10511281
    Abstract: An acoustic wave resonator includes a substrate; a resonating part disposed on a first surface of the substrate and including a first electrode, a piezoelectric layer, and a second electrode; and a cap disposed on the first surface of the substrate and including an accommodating part accommodating the resonating part. The resonating part is configured to be operated by either one or both of a signal output from a first device substrate disposed facing a second surface of the substrate on an opposite side of the substrate from the first surface of the substrate and a signal output from a second device substrate disposed on the cap.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: December 17, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ho Soo Park, Jea Shik Shin, Sang Uk Son, Yeong Gyu Lee, Moon Chul Lee, Duck Hwan Kim, Chul Soo Kim
  • Patent number: 10499495
    Abstract: A circuit board includes a first row terminal group including terminal parts aligned in a predetermined direction and a second row terminal group including terminal parts aligned in parallel with and arranged in a zig-zag pattern with respect to the first row terminal group. The first row terminal group includes first row projecting terminal parts protruding toward the second row terminal group further than another terminal parts included in the first row terminal group, the second row terminal group includes second row projecting terminal parts projecting toward the first row terminal group further than another terminal parts included in the second row terminal group, and the first row projecting terminal parts and the second row projecting terminal parts are overlapped with and spaced apart from each other in the predetermined direction.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 3, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masaki Nakayama
  • Patent number: 10496137
    Abstract: Apparatuses and associated methods for mounting PCBs and other electronics boards in portable medical equipment and/or other portable and non-portable electronic devices are disclosed herein. In some embodiments, the technology disclosed herein can provide PCB mounting systems that isolate the PCB from detrimental shock, vibration, and/or strain, while also providing electrical ground paths that greatly reduce EMI and other electrical disturbances. Some embodiments of the mounting systems described herein include both elastomeric (e.g., rubber) components and resilient metallic grounding members that, when assembled together, provide favorable shock mounting as well as robust electrical grounding without the inconvenience of using separate shock mounts, grounding straps, etc.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 3, 2019
    Assignee: FUJIFILM SONOSITE, INC.
    Inventor: Ken Dickenson
  • Patent number: 10488898
    Abstract: Thermal management devices for a computing device are described herein. A thermal management device includes a layer of a first material included in a dynamic portion of the thermal management device and a static portion of the thermal management device. The dynamic portion of the thermal management device is bendable relative to the static portion of the thermal management device when the thermal management device is physically connected to a display and a chassis of the computing device, and the display rotates relative to a chassis. The layer of material has a first side and a second side. The second side is opposite the first side. The thermal management device also includes a first layer of a second material and a second layer of the second material physically connected to the first side and the second side of the static portion of the layer of the first material, respectively.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Ketan R. Shah
  • Patent number: 10477707
    Abstract: A disclosed expansion card may include a printed circuit board and a hardware accelerator. The hardware accelerator may be disposed on the printed circuit board and may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may also include an edge connector, disposed on a connecting edge of the printed circuit board, that may couple the hardware accelerator to the central processing unit via a computing bus. The edge connector may also include a primary pinout and a secondary pinout that may each conform to a compact pinout specification that may be more compact than a pinout specification defined for the computing bus. Various other systems and methods are also disclosed.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 12, 2019
    Assignee: Facebook, Inc.
    Inventors: Christian Markus Petersen, William Christie Arnold, Hao Shen, Austin Joel Cousineau
  • Patent number: 10461035
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Patent number: 10446461
    Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Adel A. Elsherbini, Joshua D. Heppner, Shawna M. Liff
  • Patent number: 10433469
    Abstract: A semiconductor package including a package substrate including a ground layer, a first segment of which is exposed to outside the package substrate, a semiconductor chip on the package substrate, and a functional layer including a conductive polymer and an adhesive polymer, covering the semiconductor chip, and being in contact with the first segment of the ground layer may be provided.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joungphil Lee
  • Patent number: 10426036
    Abstract: A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: September 24, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Songlin Li, Pengbo Tian, Qingyun Wang, Liang Xu
  • Patent number: 10406890
    Abstract: A circuit assembly (20) provided with: a circuit board (21); a capacitor (30) connected to the circuit board (21); and a circuit casing (20C) configured to house the circuit board (21) and the capacitor (30). The capacitor (30) is provided with: a component body (31) including a pair of connection terminals (32A and 33A) to be fixed to the circuit board (21); and a first fixing unit (41) and a second fixing unit (42) configured to fix the component body (31) to the circuit casing (20C) at both sides. The connection terminals (32A and 33A) are disposed with a fixed line (L1) connecting the first fixing unit (41) and the second fixing unit (42) interposed therebetween, and both of the pair of connection terminals (32A and 33A) protrudes sideward from the component body (31) between a first surface of the circuit board (21) and the circuit casing (20C), and extends toward the circuit board (21).
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 10, 2019
    Assignee: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD.
    Inventors: Shunsuke Yakushiji, Takayuki Takashige, Hiroto Higuchi
  • Patent number: 10410884
    Abstract: A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Sony Corporation
    Inventors: Shun Mitarai, Shusaku Yanagawa, Shinji Rokuhara, Shuichi Oka
  • Patent number: 10383298
    Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Atsushi Morishima
  • Patent number: 10388754
    Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: August 20, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 10342116
    Abstract: A high-frequency module includes a wiring board; a plurality of components mounted on an upper surface of the wiring board; a sealing resin layer that is stacked on the upper surface of the wiring board and that has a step; a groove that is formed in the sealing resin layer to intersect with the step when the wiring board is viewed in plan view, and that extends between predetermined components; and a shield wall disposed in the groove and formed with a conductor. The groove includes a first portion at an upper surface side of the wiring board and a second portion at an upper surface side of the sealing resin layer, the second portion being continuous from the first portion. An area of the second portion is larger than an area of the second portion.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yoshihisa Masuda
  • Patent number: 10334082
    Abstract: An extremely high frequency (EHF) protocol converter may include a transducer, an EHF communication circuit, a protocol conversion circuit, and a circuit port. The transducer may be configured to convert between an electromagnetic EHF data signal and an electrical EHF signal. The EHF communication circuit may be configured to convert between a baseband data signal and the electrical EHF signal. The protocol conversion circuit may be adapted to convert between the baseband data signal having data formatted according to a first data protocol associated with a first external device and a second baseband data signal having data formatted according to a second data protocol associated with a second external device. The second data protocol may be different from the first data protocol. The circuit port may conduct the second baseband data signal to the second external device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 25, 2019
    Assignee: Keyssa, Inc.
    Inventors: Gary D. McCormack, Roger Isaac, Eric Almgren
  • Patent number: 10321574
    Abstract: An electronic component-embedded substrate includes a core substrate, a cavity penetrating the core substrate, a wiring layer formed on one surface of the core substrate, a support pattern extending over the cavity and configured to divide the cavity into a plurality of component embedding areas, an insulation wall portion arranged on a part of the support pattern in the cavity and formed of the same material as the core substrate, a plurality of electronic components each of which is mounted in each of the plurality of component embedding areas, and an insulating material filling an inside of the cavity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 11, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junji Sato, Katsuya Fukase
  • Patent number: 10306757
    Abstract: A circuit board includes an insulation layer, a signal line formed over the insulation layer and extending in a direction X, and a conductor layer formed under the insulation layer. The insulation layer has periodic dielectric-constant distribution in a direction Y orthogonal to the direction X. The conductor layer includes a slit at a position corresponding to the signal line. The slit expands an electric field produced between the signal line and the conductor layer; causes less difference in dielectric constants of the insulation layer in the vicinity of the signal line (the difference is caused by the positional relationship between the signal line and the dielectric-constant distribution of the insulation layer); and reduces difference in signal transmission speeds caused by the positional relationship.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 28, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Taiga Fukumori
  • Patent number: 10297275
    Abstract: An apparatus according to one embodiment includes a module having an array of first read transducers each having a tunnel valve structure and a second read transducer coupled to the array of first read transducers, the second read transducer having a tunnel valve structure. The apparatus also includes a controller, and a cable coupling the read transducers to the controller, thereby forming a plurality of circuits extending from the controller, each circuit corresponding to one of the transducers. Resistances of the circuits are about the same.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Robert E. Fontana, Jr., Calvin S. Lo
  • Patent number: 10290697
    Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10277116
    Abstract: This on-vehicle power conversion apparatus is provided with: a power conversion circuit to which DC power is inputted; and a noise reduction unit that is configured to reduce common-mode noise and normal-mode noise which are included in the DC power and that is provided to the input side of the power conversion circuit. The noise reduction unit is provided with: a core having a first core part and a second core part; a common-mode chalk coil having a first winding wire wound around the first core part and a second winding wire wound around the second coil part; and a smoothing capacitor that constitutes a low-pass filter circuit cooperatively with the common-mode chalk coil. The power conversion apparatus is further provided with a damping unit provided at a position intersecting the magnetic path of a magnetic flux leakage.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 30, 2019
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Atsushi Naito, Fumihiro Kagawa, Yoshiki Nagata, Shunsuke Ambo, Keiji Yashiro, Kazuhiro Shiraishi