Matrix Assembly Patents (Class 361/805)
  • Patent number: 9750135
    Abstract: A system compatible for use with ATCA includes a chassis comprising a first and a second plurality of slots for receiving circuit boards. The chassis further includes a midplane having a front surface and a back surface. The midplane extends between the first plurality of slots and the second plurality of slots. The midplane has a first plurality of connectors affixed to the front surface and has a second plurality of connectors affixed to the back surface. Each connector is arranged to accept a circuit board. The midplane forms an interconnection scheme such that one of the first plurality of slots is directly connected to one of the second plurality of slots. The one of the first plurality of slots and the one of the second plurality of slots extend in opposite directions from their respective connections on the midplane.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 29, 2017
    Assignee: NetScout Systems Texas, LLC
    Inventors: Ryan L. Pipkin, John P. Curtin, Yen W. Chang, William Kelly, Brian Haarberg, Daniel Gray
  • Patent number: 9159514
    Abstract: A relay connector assembly configured to electrically connect a power supply and a load includes a housing having a bottom configured to be mounted to a circuit board, the housing having contact cavities. Power contacts are received in corresponding contact cavities and held by the housing. The power contacts have relay tab ends and terminating ends having interfaces configured to be terminated to high current power conductors of either the power supply or the load. A relay is coupled to the housing. The relay has coil contacts configured to be electrically connected to a coil circuit of the circuit board used to energize the relay. The relay has relay tabs being terminated to the relay tab ends of corresponding power contacts. The relay electrically connects corresponding power contacts when the relay is energized.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 13, 2015
    Assignee: TYCO ELECTRONICS CORPORATION
    Inventors: Ronald Martin Weber, Christopher George Daily, Matthew Edward Mostoller
  • Patent number: 9099826
    Abstract: An electrical bridge is provided for electrically connecting first and second electronic modules that include first and second external chassis, respectively. The electrical bridge includes a rigid housing extending along a fixed path from a first end to a second end, and first and second electrical contacts held by the housing. The first and second electrical contacts are positioned at the first and second ends, respectively, of the housing. An electrical pathway is defined within the housing from the first electrical contact to the second electrical contact such that the first and second electrical contacts are electrically connected. The first and second ends of the housing are configured to be mounted to the first and second external chassis, respectively, such that the first and second electrical contacts are configured to mate with, and thereby electrically connect to, the first and second electronic modules, respectively.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: August 4, 2015
    Assignee: Tyco Electronics Corporation
    Inventors: Robert Paul Nichols, Brian Patrick Costello
  • Patent number: 8988888
    Abstract: A meter device which can be mounted and removed easier than conventional meter devices. A meter device is provided with a display plate, a circuit board, a middle case which is disposed on the front surface side of the circuit board and on which the display plate is mounted, an upper case which is disposed on the front surface side of the middle case and through which the front surface can be seen, and a lower case which covers the middle case and the circuit board. A flange section which is sandwiched and held between the upper and lower cases is provided to the peripheral edge of the middle case. One of the upper case and the lower cases is provided with engagement sections, and engagement sections which engage with the engagement sections are provided to the other of cases so as to correspond to the engagement sections.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 24, 2015
    Assignee: Nippon Seiki Co., Ltd.
    Inventors: Satoshi Sano, Yuichiro Nakamura, Katsuhito Umezawa
  • Patent number: 8913394
    Abstract: The present invention can facilitate the coupling between electrical components and a circuit board after the circuit board is inserted into a housing of an electronic device. An electrical component can be integrated with a flexible circuit of another electrical component. The flexible circuit can be electrically and mechanically coupled to the circuit board after the circuit board is inserted into the housing. Alternatively, electrical contacts can be disposed on a body of the electrical component and a complementary set of electrical contacts can be disposed on the circuit board. When the circuit board is disposed within a receptacle of the electrical component, the electrical contacts on the electrical component are coupled directly to the electrical contacts on the circuit board.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: Douglas Joseph Weber, Pinida Jan Moolsintong, Robert Sean Murphy, Stephen Brian Lynch
  • Patent number: 8379391
    Abstract: A memory module with attached transposer and interposers to provide additional surface area for the placement of memory devices is disclosed. The memory module includes a memory board with a first surface, a second surface and an edge with a set of electrical contacts. A transposer is attached to each surface of the memory board, and an interposer is attached to each transposer on the opposite surface of the transposer from the memory board. The interposer has space to allow placement of memory devices on both a first surface between the interposer and the memory board, and on a second surface of the interposer away from the memory board.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: February 19, 2013
    Assignee: Smart Modular Technologies, Inc.
    Inventors: Mike H. Amidi, Robert S. Pauley, Satyanarayan Shivkumar Iyer
  • Publication number: 20120236525
    Abstract: GateWay (GW) having a shape of a substantially-flat rectangular parallelepiped and including terminals on one wide surface or both wide surfaces, GWs are stacked on each other so as to connect first corresponding terminals while connecting second corresponding terminals. The corresponding terminals are connected inside each GW, and are connected with each other via a component for transmitting a communication signal through a communication line and via a relay processing section for executing a relaying process for the communication signal. By stacking GWs on each other, the function of a multi-bus GW can be realized.
    Type: Application
    Filed: November 30, 2010
    Publication date: September 20, 2012
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO WIRING SYSTEMS, LTD.
    Inventor: Hiroshi Okada
  • Patent number: 8169296
    Abstract: A switch matrix module (600) includes programmable stub breakers (508-512, 514-518) which can break off the bus and isolate unused portion of the switch matrix. Using three-way stub breakers (508-512, 514-518) at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, allows for the formation of very large matrices which have improved operational performance.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 1, 2012
    Assignee: EADS North America, Inc.
    Inventors: Gary Carlson, Jeffrey Norris, Randy Raasch, Long Ta
  • Patent number: 8144475
    Abstract: The present invention can facilitate the coupling between electrical components and a circuit board after the circuit board is inserted into a housing of an electronic device. An electrical component can be integrated with a flexible circuit of another electrical component. The flexible circuit can be electrically and mechanically coupled to the circuit board after the circuit board is inserted into the housing. Alternatively, electrical contacts can be disposed on a body of the electrical component and a complementary set of electrical contacts can be disposed on the circuit board. When the circuit board is disposed within a receptacle of the electrical component, the electrical contacts on the electrical component are coupled directly to the electrical contacts on the circuit board.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: March 27, 2012
    Assignee: Apple Inc.
    Inventors: Douglas Joseph Weber, Pinida Jan Moolsintong, Robert Sean Murphy, Stephen Brian Lynch
  • Patent number: 7936063
    Abstract: A carrier assembly for an integrated circuit is disclosed. The carrier assembly has a retainer with electrical contacts for receiving the integrated circuit, and island defining portions arranged about the retainer. Each island defining portion is connected to neighboring island defining portions through a serpentine member. This connection allows resilient deflection between the island defining portions.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: May 3, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7892626
    Abstract: A substrate with plane patterns formed in a liquid process wherein the plane patterns are formed based on a combination of plane shapes by which a difference in internal pressure of a solution between any two points of the solution is small, the solution being ejected onto the substrate so as to form the plane patterns by the liquid process.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: February 22, 2011
    Assignee: Future Vision Inc.
    Inventors: Makoto Abe, Hiroki Kaneko, Takuya Takahashi, Etsuko Nishimura, Yoshitaka Tsutsui, Takaaki Suzuki
  • Patent number: 7838989
    Abstract: A semiconductor component for radio-frequency applications has at least one substrate and one chip, and with contact pads is disclosed. In one embodiment, bonding wires connect the contact pads on the chip to the contact connecting pads. Signals are passed via these contact pads such that signals at high frequencies are passed via one or more contact pads and signals at low frequencies are passed via one or more contact pads. The chip is shifted on the substrate from a central position with respect to the totality of the contact connecting pads, so that the bonding wires for those contact pads via which signals at a high frequency are passed are shorter than bonding wires for those contact pads via which signals at low frequencies are passed.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: November 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Mario Engl, Horst Theuss
  • Patent number: 7764505
    Abstract: The invention relates to a joint which can be subjected to the temperature influences of an external medium (20) and joins an especially ceramic component (2) to an especially metallic component (1). Said joint consists of a first adhesive joint (14) between the metallic component and the ceramic component, and a second adhesive joint (22), the adhesive (16) of the second joint having a higher elasticity than that (10) of the first adhesive joint (14), and the second joint being arranged in such a way that it prevents direct contact between the first adhesive joint (14) and an external medium (20). The inventive joint can preferably be used, for example, preferably in a sensor module of a measuring appliance which can be introduced into a medium to be analyzed.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: July 27, 2010
    Assignee: Testo AG
    Inventors: Mike Muhl, Andreas Derr, Gerd Heckelmann, Heinz Oswald, J├╝rgen Hall
  • Patent number: 7733668
    Abstract: A hybrid integrated circuit device includes: an insulating substrate (1) having a lower surface formed with wiring patterns including ends arranged along ends of the lower surface at a predetermined pitch (P); electronic components (3) mounted on the surfaces of the insulating substrate to be connected to the wiring patterns; a pair of insulating legs (2) arranged at the ends of the lower surface of the substrate (1), each insulating leg extending in parallel to the lower surface of the substrate (1); and a plurality of terminal electrodes (5) formed on each leg at the pitch and extending perpendicularly to the substrate, where the plurality of terminal electrodes are connected to the wiring patterns on the lower surface of the substrate (1). Each leg has a surface bonded to the substrate and formed with electrode films connected to the terminal electrodes.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 8, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Seitaro Mizuhara, Naoya Tanaka
  • Patent number: 7705452
    Abstract: A carrier assembly for an integrated circuit is described. The assembly includes a retainer for receiving the integrated circuit, and island defining portions surrounding the retainer. Each island defining portion is connected to neighboring island defining portions through a serpentine member. This arrangement allows resilient deflection between the island defining portions.
    Type: Grant
    Filed: November 23, 2008
    Date of Patent: April 27, 2010
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7660127
    Abstract: The present invention can facilitate the coupling between electrical components and a circuit board after the circuit board is inserted into a housing of an electronic device. An electrical component can be integrated with a flexible circuit of another electrical component. The flexible circuit can be electrically and mechanically coupled to the circuit board after the circuit board is inserted into the housing. Alternatively, electrical contacts can be disposed on a body of the electrical component and a complementary set of electrical contacts can be disposed on the circuit board. When the circuit board is disposed within a receptacle of the electrical component, the electrical contacts on the electrical component are coupled directly to the electrical contacts on the circuit board.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: February 9, 2010
    Assignee: Apple Inc.
    Inventors: Douglas Joseph Weber, Pinida Jan Moolsintong, Robert Sean Murphy, Stephen Brian Lynch
  • Patent number: 7479697
    Abstract: Provided is a carrier assembly for an integrated circuit. The assembly includes a carrier having a matrix of island contacts interconnected by respective serpentine members to allow resilient deflection between such contacts, said matrix surrounding a passage defined through the carrier. The assembly also includes a retainer for operatively locating the integrated circuit within said passage so that the integrated circuit is electrically connected to the carrier.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: January 20, 2009
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7445457
    Abstract: A midplane has plated through holes (PTHs) which form a first profile and a second profile. The first profile has (i) an overlapping portion which overlaps at least part of the second profile and (ii) a non-overlapping portion which does not overlap any part of the second profile. A first connector mounts to a first side of the midplane over the first profile, and a second connector mounts to a second side of the midplane over the second profile. At least one PTH is a shared PTH which resides in both the first and second profiles and which engages a pin of the first connector and a pin of the second connector. Additionally, at least one PTH is a non-shared PTH which resides in the non-overlapping portion of the first profile and which engages a pin of the first connector without engaging any pins of the second connector.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 4, 2008
    Assignee: EMC Corporation
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki, Michael L. Schillinger
  • Patent number: 7411134
    Abstract: Electrical mounting boards and methods for their fabrication and use are disclosed herein. In particular, such mounting boards embodiments utilize hybrid ground lines interconnected through a substrate core to form multilayer ground grids. Such hybrid ground lines include groups of substantially parallel ground lines configured such that the groups of ground lines are positioned in transverse arrangement with other groups of ground lines formed on the same level. Such implementations have many uses, including, but not limited to, the ability to more efficiently route signal lines and connect electrical components on a circuit board.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: August 12, 2008
    Assignee: Apple Inc.
    Inventors: Robert Steinfeld, Cheung-Wei Lam
  • Patent number: 7397001
    Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: July 8, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Norman Lee Owen
  • Patent number: 7321497
    Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units (101a-101n), a circuit board (102) and a connection unit (103), the circuit board (102) having a basic board element (200) and a plurality of additional board elements (201-204), the plurality of additional board elements (201-204) being connected to the basic board element (200) by means of connecting elements (301-304) and the circuit units being arranged on the additional board elements (201-204) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board (201-204) and the connection unit (103).
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: January 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Sven Boldt, Erwin Thalmann
  • Patent number: 7247941
    Abstract: A printed circuit board (PCB) assembly includes a PCB. An integrated circuit (IC) carrier defines a receiving zone to receive an IC. The carrier has a plurality of island portions about the receiving zone. Each island portion includes a solder member for contacting the PCB. A plurality of resilient serpentine members interconnect neighboring island portions so that at least some relative displacement of the PCB and the carrier is accommodated by the serpentine member, thereby alleviating strain imparted to the solder member.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 24, 2007
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7199306
    Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: April 3, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Norman Lee Owens
  • Patent number: 7139648
    Abstract: The invention relates to an apparatus for actuating a control element, for example, an air flap, for a heating or air-conditioning system (34) in a motor vehicle, having an actuating drive (32), an electrical circuit (1) which controls the actuating drive (32), and a control section (36) for inputting control commands. The actuating drive (32), the circuit (1) and the control section (36) are connected to one another via at least one electrical cable (3). In order to provide an improved apparatus for actuating a control element, particularly with regard to reducing the production costs, the circuit (1) is arranged outside the actuating drive (32) and outside the control section (36) and, in particular, is preferably integrated in the databus (3). This allows identical actuating drives to be used cost-effectively for the different control elements.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: November 21, 2006
    Assignee: Behr GmbH & Co.
    Inventors: Ralf Martin, Klaus Waibel
  • Patent number: 7031170
    Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Frank Daeche, Franz Petter
  • Patent number: 6831233
    Abstract: A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: December 14, 2004
    Assignee: Intel Corporation
    Inventor: Dustin P. Wood
  • Patent number: 6787984
    Abstract: A wiring substrate for a display panel having a plurality of wiring electrodes thereon includes an airtight container formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes. The airtight container has an image forming member therein, in which an average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while an average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20040066642
    Abstract: A breadboard comprising a plate made of an insulating material and having a connection strip portion including a grouping of at least three rows of sets of at least three spaced apart holes in each set in the plate, the centers of the holes in each set being spaced from each other by a predetermined distance defined as a space, groups of at least three connector clips in the plate each connected in at least a three gang grouping, each referred to as a conductive strip which is aligned with and beneath one of the rows of sets of pinholes with all conductive strips being electrically isolated from each other, and all the strips in each row being offset from the conductive strip in an adjacent row by the predetermined distance and the sets being aligned in each row, end-to-end, with one space between end holes of two adjacent sets in a row, and each row being offset or staggered from each adjacent row by at least one space such that an array of spaces is formed, with each interior space in the middle row forming
    Type: Application
    Filed: September 16, 2003
    Publication date: April 8, 2004
    Inventor: Paul A. Swetland
  • Patent number: 6710265
    Abstract: A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates (12) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board (11) has a thickness (26) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: March 23, 2004
    Assignee: Motorola, Inc.
    Inventor: Norman Lee Owens
  • Patent number: 6542952
    Abstract: A PCI computer system includes component boards (130) adjacent to and coupled to a PCI bus (120), a controller board (310) coupled to the PCI bus, a transition module (140) coupled to the PCI bus, a switching matrix (150, 151) coupled to the transition module, and an I/O module (160, 161) coupled to the component boards and the controller board via the switching matrix, the transition module, and the PCI bus. A method of operating the PCI computer system includes transmitting a first signal from one of the component boards, transmitting a second signal from the I/O module, transmitting a third signal from the controller board in response to the first and second signals to configure the switching matrix to make the pin-out configuration of the one of the component boards compatible with the I/O module, and transmitting a first set of data between the component board and the I/O module.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: April 1, 2003
    Assignee: Motorola, Inc.
    Inventor: Gary E. Western
  • Patent number: 6535397
    Abstract: An interconnect structure interconnects electronic modules and includes a backplane assembly formed from a substantially rigid backplane plate that carries RF connectors and a digital motherboard having digital connectors for mating with digital connectors of electronic modules. A controlled impedance interconnect circuit is positioned on the rear surface of the backplane plate and interconnects the RF connectors carried by the backplane plate and digital connectors of the digital motherboard. A rack receives the backplane assembly and supports a plurality of electronic modules that are interconnected to each other via the backplane assembly.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: March 18, 2003
    Assignee: Harris Corporation
    Inventors: William Clark, Douglas Heckaman, Edward Bajgrowicz
  • Patent number: 6496377
    Abstract: A vehicle electric power distribution apparatus is provided which includes a plurality of vertically stacked conductive circuit layers, each layer including an array of contact pads, a layer of electrically insulating plastic material between each of the conductive circuit layers, at least some of the contact pads are electrically connected to selected other contact pads of the same conductive circuit layer via integrally formed conductive traces. In addition to the stacked circuit layers the apparatus includes a plurality of conductive pins providing electrical contact between selected contact pads of different selected conductive circuit layers.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: December 17, 2002
    Assignee: CooperTechnologies Company
    Inventors: Lawrence R. Happ, Jacek Korczynski, Willaim R. Bailey, Alan Lesesky
  • Patent number: 6485309
    Abstract: The present invention is a method and apparatus for interconnection system. A first connector located on a first card provides first contacts for first signal traces on the first card. The first connector has a first housing enclosing the first contacts and a first extension portion. A second connector located on a second card provides second contacts for second signal traces on the second card. The second connector has a second housing enclosing the second contacts. The second connector is coupled to the first connector when the first and second housings are mated such that the first and second cards are substantially perpendicular to each other, the second card is aligned on the first extension portion.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: November 26, 2002
    Assignee: Nortel Networks Limited
    Inventor: Philip K. Edholm
  • Patent number: 6445578
    Abstract: An enclosure for a data storage system comprises at least first and second cast magnesium parts joined by rivets, each of which is made of a suitable material that provides compressive strength superior to that of the cast magnesium. Each rivet is of a height or thickness equal to the sum of the thickness of the parts to be riveted. Each such rivet has flat end surfaces and its body is peripherally concave between its ends. The rivet is embedded in the two parts, and the parts flow radially against the concave body of the rivet. No drilling is required, and the parts are held in carefully defined position while being joined, so that the assembled enclosure satisfies strict dimensional tolerances.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: September 3, 2002
    Assignee: Eurologic Systems
    Inventors: Michael Stephen Bell, Grant Edward Carlson
  • Patent number: 6423909
    Abstract: A circuit board including differential bus traces on or buried within both sides of the board, interconnecting electronic devices such as disk drives, processors, and connectors for external cables. Via fields, which mimic the size and configuration of the device and cable connector fields, are located between each connector on the board. The via fields link bus traces on or within one side of the board with respective bus traces on or within the other side of the board. The via fields may include subtle, unequal undulations in the trace patterns to provide equalization in the lengths of all trace pairs. The via fields and the connector fields both include repetitive conductor order reversals in the trace connections on opposing sides of the board, to reduce crosstalk between channels. The via fields may be oriented parallel with respect to collinearly arranged devices, or orthogonal with respect to devices or connectors which are parallel.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: July 23, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Carl R. Haynie, David Dickey, James J. deBlanc
  • Patent number: 6388200
    Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: May 14, 2002
    Assignee: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Publication number: 20010040049
    Abstract: A circuit board assembly containing two pluralities of busbars or wires arranged in a lattice configuration, there being electrical continuity at each of the intersecting points. Slits are provided on each of the busbars which engage each other to complete the lattice. In the case of wires, they are bonded to each other. The conductive member thus formed may be sandwiched between two insulative films and is placed on an insulative plate which, in turn, is enclosed by an electrical connection box. The configuration provides substantial advantages in economy of production, simplified equipment required, and ease of altering the circuitry.
    Type: Application
    Filed: July 10, 2001
    Publication date: November 15, 2001
    Inventors: Tatsuya Sumida, Masanobu Sato, Kazuhiro Aoki
  • Publication number: 20010040050
    Abstract: A circuit board assembly containing two pluralities of busbars or wires arranged in a lattice configuration, there being electrical continuity at each of the intersecting points. Slits are provided on each of the busbars which engage each other to complete the lattice. In the case of wires, they are bonded to each other. The conductive member thus formed may be sandwiched between two insulative films and is placed on an insulative plate which, in turn, is enclosed by an electrical connection box. The configuration provides substantial advantages in economy of production, simplified equipment required, and ease of altering the circuitry.
    Type: Application
    Filed: July 10, 2001
    Publication date: November 15, 2001
    Applicant: Sumitomo Wiring Systems, Ltd.
    Inventors: Tatsuya Sumida, Masanobu Sato, Kazuhiro Aoki
  • Patent number: 6303871
    Abstract: An organic land grid array having multiple built up layers of metal sandwiching non-conductive layers, having a staggered pattern of degassing holes in the metal layers. The staggered pattern occurs in two substantially perpendicular directions. Traces between the metal layers have reduced impedance variation due to the degassing hole pattern.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: October 16, 2001
    Assignee: Intel Corporation
    Inventors: Longqiang Zu, Huong Do
  • Patent number: 6297460
    Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: October 2, 2001
    Assignee: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Patent number: 6255600
    Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: July 3, 2001
    Assignee: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Patent number: 6049043
    Abstract: A printed circuit board has a plastic carrier plate and a one-piece pressed screen forming interconnects of the electrical circuit that are firmly mechanically connected to one another via preferably hot-stamped or ultrasound-deformed plastic webs. The interconnects have connector tabs bent off at a right angle and contact tabs for contacting the plug-in base and the relays to be accepted and also have stamped-out contact profiles for the connection to electrical components. The plugged-on relays and components are preferably connected to the interconnects welding. A two-sided access to parting locations in the pressed screen is made for tools on the basis of recesses in the carrier plate.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: April 11, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Vinko Tonejc
  • Patent number: 6037677
    Abstract: A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Gottschall, Roger P. Gregor, James P. Libous
  • Patent number: 5956232
    Abstract: Chip-support arrangement (23) with a chip support (23) for the manufacture of a chip casing, said chip support being provided on a support foil (20) with conducting paths (21) which are connected on the front side of the support foil facing a chip (39) to contact-surface metallizations (40) of the chip and which with their free ends form a connection-surface arrangement (42) distributed in planar manner for the purpose of connection to an electronic component or a substrate, whereby the conducting paths (21) are arranged on the reverse side of the support foil (20), recesses (28) in the support foil (20) are provided in the region of the contact-surface metallizations (40), the conducting paths for forming the connection-surface arrangement (42) are covered with a perforated mask (36) and the thickness (s) of the support foil is smaller than or substantially equal to the height (h) of the contact-surface metallizations (40) on the surface of the chip.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: September 21, 1999
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Elke Zakel, David Lin, Jorg Gwiasda, Andreas Ostmann
  • Patent number: 5887158
    Abstract: A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: March 23, 1999
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Stephen P. Sample, Terry L. Goode
  • Patent number: 5748450
    Abstract: In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: May 5, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Young-Gon Kim, Dong-You Kim
  • Patent number: 5644115
    Abstract: A matrix of three pole, high speed, low current relays for connecting test equipment to a device under test is provided with improved interconnect buses. The relays are mounted in rows and columns with their three pairs of leads extending vertically. An input interconnect bar having three conductors extends horizontally along each row of relays, each conductor being connected to a respective one of each pair of leads. A bottom interconnect bar having three buses extends perpendicular to the top interconnect bars along each column of relays, each bus being connected to a respective one of the leads. The ends of the leads are aligned at a 45.degree. angle with respect to the interconnects. The interconnect bars are enclosed in shielding guard tubes and are removable to permit replacement of the relays.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: July 1, 1997
    Assignee: Keithley Instruments, Inc.
    Inventor: William Knauer
  • Patent number: 5640308
    Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: June 17, 1997
    Assignee: Aptix Corporation
    Inventors: Robert Osann, Jr., George A. Shaw, Jr., Amr M. Mohsen
  • Patent number: 5633479
    Abstract: Signal wiring layers are formed between a power supply layer and a ground layer, which have conductor patterns each constituted by a plurality of parallel strip-shaped conductors. The above layers are isolated from each other by insulating layers. The signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the power supply layer, and the signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the ground layer.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: May 27, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naohiko Hirano
  • Patent number: 5585602
    Abstract: A method for forming one or more conductive paths by providing a first pattern of pre-formed conductive elements and a second pattern of preformed conductive elements in a substrate and forming, at a single level, one or more lateral conductive links between selected ones of the first and second conductive elements to provide a selected configuration of one or more conductive paths.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: December 17, 1996
    Assignee: Massachusetts Institute of Technology
    Inventor: Joseph B. Bernstein