Matrix Assembly Patents (Class 361/805)
  • Patent number: 5572409
    Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: November 5, 1996
    Assignee: Prolinx Labs Corporation
    Inventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang
  • Patent number: 5512782
    Abstract: A semiconductor device for converting DC input power to AC output power includes a package having a rectangular shape with four side edges and containing a plurality of semiconductor chips therein. Two pairs of positive and negative terminals of DC input terminals are situated on the side edges to face to each other such that the same polar terminals in the positive and negative terminals face to each other. AC output terminals and control terminals are arranged on the side edges where the DC input terminals are not formed.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: April 30, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shinichi Kobayashi
  • Patent number: 5481073
    Abstract: The basic element of a modular, bidirectional broadband programmable switch system is a switch module having a thin rectangular housing with a single first connector preferably in the center of an elongated rear face and n second connectors equally spaced along the elongated front face. Broadband switches within the module selectively connect the single first connector with any one of the second connectors to provide an n.times.1 or 1.times.n switch. Up to n of the switch modules can be stacked side-by-side with an additional module extending transversely with its n second connectors connected to the first connectors on the stacked modules to provide an n.sup.2 .times.1 or 1.times.n.sup.2 switch. The first connectors on the additional modules of two such stacks can be connected to provide an n.sup.2.times.n.sup.2 switch.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: January 2, 1996
    Assignee: Quintech, Inc.
    Inventors: Samuel Singer, Francis J. DeSantis, Harry Krasnikoff
  • Patent number: 5438166
    Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: August 1, 1995
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: David H. Carey, Barry H. Whalen
  • Patent number: 5410107
    Abstract: An electrical interconnection medium having first and second overlying interconnection layers, each interconnection layer including parallel conductors, the conductors of the first and second interconnection layers being oriented orthogonal to each other, the conductors being interconnected so as to form at least two electrical planes, the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: April 25, 1995
    Assignee: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Patent number: 5390081
    Abstract: Fault-tolerant power distribution system for back-mounted hardware in which a backplane arrangement delivers alternative sources of system power in a prioritized pattern to each of a plurality of fault-tolerant electronic cards via a plurality of system slots, each slot including a power port having electrical contacts in a common system pinout, and the cooperating system cards have electrical contacts in the same common system pinout. Any of the system cards can be installed in any system slot and will receive the system power in one of a plurality of fault-tolerant prioritizations.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: February 14, 1995
    Assignee: Stratus Computer, Inc.
    Inventor: Keith St. Pierre
  • Patent number: 5352123
    Abstract: A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: October 4, 1994
    Assignee: Quickturn Systems, Incorporated
    Inventors: Stephen P. Sample, Terry L. Goode
  • Patent number: 5309327
    Abstract: A circuit board assembly system for manufacturing a prototype printed circuit board having a matrix formed in it. A base board having a connection matrix that matches the matrix of the printed circuit board is hinged to a frame having tracks for receiving the printed circuit board, so that the printed circuit board is locatable in a fixed position in relation to the printed circuit board with their respective matrices matching. Component leads may be inserted into the connection matrix through the printed circuit board to form a circuit, which may be tested. The base board may be pivoted away from the printed circuit board to allow the leads to be soldered. The printed circuit board may then be removed from the base board. A cover that is latchable onto the printed circuit board may be used to prevent components from being accidentally removed from the printed circuit board.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: May 3, 1994
    Assignee: Platform Systems Inc.
    Inventor: Cody Z. Slater
  • Patent number: 5289340
    Abstract: An electronic device has a rack accommodating a mother board and a first and a second printed circuit board (PCB) group mounted on the mother board. The PCBs belonging to one of the first and second groups are mounted on the mother board in an upper half of the rack while having the surfaces thereof positioned substantially parallel to the side walls of the rack. The PCBs belonging to the other group are mounted on the mother board in a lower half of the rack while having the surfaces thereof held substantially horizontal. If necessary, a third group of PCBs are positioned above one of the first and second PCB groups and mounted on the mother board with their surfaces held substantially horizontal. The wiring network between the first and second (and third) PCB groups is formed on the surface of the mother board by printing. Two electric fans may be respectively located between the first and second PCB groups and between the third and first (or second) PCB groups.
    Type: Grant
    Filed: June 24, 1992
    Date of Patent: February 22, 1994
    Assignee: NEC Corporation
    Inventor: Yuuki Yoshifuji
  • Patent number: 5278727
    Abstract: A high density electrical interconnection device provides a uniform complementary pattern of thieving lines on both X and Y interconnect layers of the high density device to provide for uniform plating of the copper conductors, as well as reducing both nonuniformity and the amount of contraction and expansion of the insulating substrate. The complementary line pattern of thieving lines is generated by computer-aided design techniques and also includes provisions for gaps in thieving lines in one layer so as to eliminate crossover coupling with another layer and provides for visual identification of the thieving lines by the use of an undulating pattern.
    Type: Grant
    Filed: March 25, 1992
    Date of Patent: January 11, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Scott M. Westbrook, Gelston Howell
  • Patent number: 5257166
    Abstract: There is provided a configurable electronic circuit board which comprises a board including many modular sockets in a minimum unit each having a size and the number of pins both standardized, the modular sockets being arranged regularly parallely and connected to each other at terminals thereof through simple wirings, a pin adapter composed of adapter pins insertable into the modular socket, of an adapter socket into which electronic circuit parts are insertable, and of socket wirings for making connection between the adapter socket and the adapter pins, a switching station adapter composed of adapter pins insertable into the modular socket, and of a wiring changeover switch and a fuse for determining the connection of wiring among the adapter pins, and a bypass adapter being inserted into a modular socket not used, and composed of adapter pins insertable into the modular socket, and of fixed wiring for simply bypass-connecting among the adapter pins, whereby an arbitrary circuit is realizable by inserting ea
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: October 26, 1993
    Assignee: Kawasaki Steel Corporation
    Inventors: Tomohiro Marui, Yoshihiro Ishida, Hiroyuki Oka, Izumi Hayashibara