Mounting Pad Patents (Class 361/808)
  • Publication number: 20080298038
    Abstract: A wiring board has predetermined numbers of wiring layers and insulating layers among the respective wiring layers. The wiring board has an external connecting pad and a surface plating layer for connecting to an external circuit is arranged on the external connecting pad. An area of an external connecting pad is smaller than an area of a surface plating layer thereof.
    Type: Application
    Filed: May 23, 2008
    Publication date: December 4, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kentaro Kaneko
  • Patent number: 7455915
    Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: November 25, 2008
    Inventor: Morgan T. Johnson
  • Publication number: 20080285250
    Abstract: A structural packaging assembly to support a multi-function optic chip or the like is mountable in a gyroscopic unit. An example assembly includes a housing mounted to a mounting plate. The chip is located in the housing, which in turn is coupled to a mounting plate. The housing may have a prescribed section modulus capable of sufficiently withstanding applied vibrations within a predefined vibrational range, such as a vibrational range at or below about 3500 Hz. The structural packaging assembly utilizes a mounting system with mounting feet that clamp to dowels, which in turn have been press fit into the mounting plate. In one embodiment, the mounting feet take the form of ā€œCā€ clamp mechanisms, which after being clamped to the dowels, allow for resonance dampening between the housing and the mounting plate.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Applicant: Honeywell International, Inc.
    Inventors: Andrew W. Kaliszek, Derek T. Mead, Jason C. Grooms, Michael D. Robbins, Christopher S. Herman
  • Patent number: 7448909
    Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 11, 2008
    Assignee: Molex Incorporated
    Inventors: Kent E. Regnier, David L. Brunker, Martin U. Ogbuokiri
  • Patent number: 7446403
    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: November 4, 2008
    Assignee: Entorian Technologies, LP
    Inventor: Julian Partridge
  • Patent number: 7440281
    Abstract: An apparatus for conducting heat from a computer component to a heat sink. The invention may include a thermal interface material (TIM). The invention may further include a seal or gasket that at least partially encloses the TIM. The gasket may facilitate retaining the TIM within its sidewall, and thus in place on or near a computer component. Generally, the gasket may be placed between the computer component (or a silicon board or other material upon which the computer component is located) and a heat sink. An insert may be placed within the gasket and define an aperture. The chip seats in the aperture and thus is spatially located with respect to the insert. The TIM abuts both the computer component and a heat sink. A desiccant may be located within the gasket and absorb any moisture diffusing or migrating through the gasket.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: October 21, 2008
    Assignee: Apple Inc.
    Inventors: Sean Ashley Bailey, Richard Lidio Blanco, Jr., David Edwards, Supratik Guha, Michael David Hillman, Yves C. Martin, Phillip Lee Mort, Roger Schmidt, Prabjit Singh, Ronald Jack Smith, Gregory L. Tice, Theodore Gerard van Kessel
  • Publication number: 20080253103
    Abstract: The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side walls formed around the base. In the step-to-step carriage in the post-production process of the manufacture of wafer level CSPs and on like occasions, the base supports not the organic film but the plurality of solder bumps. For this reason, it is made possible to prevent the organic film from being flawed or coming off and adhering to the product as foreign matter, and as a result the quality and yield of the wafer level CSPs (semiconductor devices) can be improved.
    Type: Application
    Filed: May 8, 2008
    Publication date: October 16, 2008
    Inventor: Noriyuki TAKAHASHI
  • Publication number: 20080239690
    Abstract: A wedge lock clamping assembly, system and method wherein the module to be clamped in a slot in a chassis has a pair of wedge surfaces oppositely inclined to spaced-apart side surfaces of the slot. The clamping assembly comprises a pair of wedge elements on opposite sides of a movement axis and each wedge element is configured to be disposed within the slot between a respective wedge surface of the module and a respective side surface of the slot. An actuator operates to forcibly urge the wedge elements along the movement axis for causing the wedge elements to be wedged between the respective wedge surfaces of the module and respective side surfaces of the slot for clamping the module in the slot.
    Type: Application
    Filed: July 18, 2007
    Publication date: October 2, 2008
    Inventors: Rex J. Harvey, Robert A. Frindt
  • Publication number: 20080232077
    Abstract: The present invention relates to a conversion substrate for a leadframe and the method for making the same. The conversion substrate comprises a core layer, a first copper layer, a first metal plating layer and a first brown/black oxide layer. The first copper layer is on a first surface of the core layer, and has a plurality of discontinuous sections. The first metal plating layer is on the first copper layer, and has a plurality of discontinuous sections. The first brown/black oxide layer is on the first copper layer, so as to protect the first copper layer. Thus, the polymeric solder mask is not used in the conversion substrate of the present invention, so that the metal plating layer will not be polluted, and the yield rate can be raised.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Che-Yuan Chang, Yao-Ting Huang
  • Patent number: 7414317
    Abstract: In the BGA package and its manufacturing method, a bonding pad is etched from the exposed surface to a part of the insulation layer-coated region so as to form a solder contact side having a dish configuration, which is planar at a bottom center and slanted at a periphery. With this bent structure of the dish configuration, the bonding pad provides an increased bonding area for the solder, so that the BGA package substrate is enhanced in reliability.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: August 19, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyo Soo Lee, Tae Gon Lee, Sung Eun Park
  • Patent number: 7411795
    Abstract: Provided is a desktop holder for a portable terminal. The desktop holder for a portable terminal includes a main body and a soft member. The soft member is elastically assembled with the main body, has an opening corresponding to a shape of any portable terminal selected out of various kinds of portable terminals, and holds a selected portable terminal on the main body.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: August 12, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: In-Gon Park, Chang-Soo Lee
  • Publication number: 20080158843
    Abstract: An electronic part having mounting terminals made of a thermally-meltable bonding material is mounted on a mounting board. A structural part is used for moving a height-adjusting member to a position under the electronic part in a process of heating and melting the thermally-meltable bonding material so as to maintain a predetermined distance between the electronic part and the mounting board.
    Type: Application
    Filed: October 4, 2007
    Publication date: July 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi SO, Yoshinori UZUKA, Osamu AIZAWA, Hideo KUBO
  • Patent number: 7365991
    Abstract: Circuit boards for lighting systems have identical LED landing zones printed on the board. Each zone includes at least two sets of LED contact pads. One pad set is configured to mate with contacts of an LED of a first structural type, e.g. from a first product line or manufacturer. The other pad set is configured to mate with contacts of an LED of a second type, e.g. from a different product line or manufacturer. The layout may enable an easy system re-design, e.g. to shift from one type of LED to another. Alternatively, the layout may enable one system to use LEDs of the two different types in a single LED set or array. Exemplary systems disclosed herein include an element for mixing light produced by LEDs mounted to the landing zones, such as an optical integrating cavity.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: April 29, 2008
    Assignee: Renaissance Lighting
    Inventors: Matthew H. Aldrich, Jack C. Rains, Jr.
  • Patent number: 7333771
    Abstract: A relatively low cost, easy to install and aesthetically pleasing cellular signal enhancer, also known as a wireless repeater, suitable for use in a home or business. The device includes a removable mounting pedestal that can be plugged into both an upper and a lower receptacle on a signal enhancer unit. This allows the signal enhancer unit to be installed with the same upright orientation when installed on an upper or a lower support surface, for example the bottom or top casing of a window frame. The mounting pedestal includes a power plug so that the mounting pedestal is removable and can be plugged into the upper or lower receptacles on the signal enhancer unit. Alternatively, the unit may include an orientation detector and an invertible display that inverts the symbols shown on the display in response to the detected orientation of the signal enhancer unit.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: February 19, 2008
    Assignee: Andrew Corporation
    Inventor: James William Maxwell
  • Patent number: 7298629
    Abstract: A circuit board has a plurality of pads arranged as a grid array in a quadrangle region. A surface mount type circuit component is connected to the circuit board through the pads. Each of pads arranged in the outermost side of the quadrangle region is formed in a substantially quadrangle shape in plan view.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: November 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Nakajima, Kana Onoko
  • Patent number: 7247931
    Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 24, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Chuan Kiak Ng, Ein Sun Ng, Yeu Wen Lee
  • Patent number: 7236372
    Abstract: A surface mounted power supply circuit apparatus, including a circuit substrate, circuit constituting parts mounted on the circuit substrate, and a sealing member provided on the circuit substrate for covering the circuit constituting parts, at least one portion of the circuit constituting parts being configured to be contained in a containing portion formed in the circuit substrate.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: June 26, 2007
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Michihiro Shirai
  • Patent number: 7212400
    Abstract: A fixing apparatus is for fixing a motherboard (60) in a chassis (20). The chassis includes a supporting board (30). The supporting plate includes a number of clips (36, 38), and a screw hole (391). The motherboard (60) defines a number of through holes (62) corresponding to a number of standoff (40) disposed on the supporting plate, a number of apertures (64), and a fixing hole (66). The through holes each include a circular hole (622), and a slot (624). The standoffs each comprise a head (42), a neck (44), and a base (46). The clips each include a shoulder (367, 387), and a catch (366, 386). The standoffs and the clips engage the through hole and the apertures of the supporting plate to attach the motherboard in the chassis. A stud extends through the fixing hole and engages the screw hole to secure the motherboard in the chassis.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: May 1, 2007
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chen-Lu Fan, Chien-Chung Liu, Li-Ping Chen
  • Patent number: 7120033
    Abstract: An electrically conducting bonding connection (B) is produced between an electronic circuit (S) arranged on an electrically conducting support plate (1) and the support plate (1) by providing a hole (4, 5), into which an electrically conducting bonding element (2) with a bondable surface (3) is pressed in such a way that the support plate (1) and the bonding element (2) enter into an electrically conducting and frictional connection; the bonding connection is subsequently produced with the bonding element (2).
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: October 10, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kurt Gross, Hans Rappl
  • Patent number: 7095625
    Abstract: An electronic component mounting circuit board for mounting an electronic component, comprises a circuit board, and connection pads provided on the circuit board, the connection pads being formed with a plurality of holes for inserting terminals of the electronic component.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: August 22, 2006
    Assignee: Fuji Xerox Co., Ltd
    Inventor: Kentaro Fukami
  • Patent number: 7057291
    Abstract: A method for assembling vertically mountable semiconductor devices includes positioning the semiconductor devices so that backsides thereof face one another and that edges of the vertically mountable semiconductor devices along which contacts are disposed are in alignment with each other. The backsides of the vertically mountable semiconductor devices are secured to one another with an adhesive. Individual devices, such as dice, may be positioned and secured to one another in this manner, or larger, multiple-device-carrying substrates, such as device-bearing wafers, may be positioned back-to-back and secured to one another. If the assembled semiconductor devices are carried by larger substrates, individual modules may be subsequently separated from each other.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 7045902
    Abstract: A circuitized substrate has contact pads for mounting a Surface Mount Device (SMD). First and second contact pads are located on a surface of the substrate corresponding to a first terminal and a second terminal of the SMD. The first and the second contact pads have a plurality of expanded portion or diminished portions to form bead receptacles at the facing corners thereof. When solder paste is reflowed to electrically connect the SMD, solder beads formed from the solder paste can be fixed on the bead receptacles. Therefore, there is no free solder bead on the substrate causing short circuit for semiconductor packages.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: May 16, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sheng-Tsung Liu
  • Patent number: 7031170
    Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Frank Daeche, Franz Petter
  • Patent number: 7019982
    Abstract: A foolproof polarity indication for poled electronics parts or devices to be mounted to a printed circuit board assures that the poled electronics parts and/or devices are correctly mounted with respect of their polarities to meet occasional requirements dependent on different specifications. Each pair of terminal holes is allotted to a given poled electronics part or device. Two symbols representative of such electronics part or device are arranged side by side on either side of a line drawn from one terminal hole to the other terminal hole. The poled electronics part or device symbols are of reversed polarities. This dual symbol arrangement is effective to draw a worker's attention in the mounting of electrode components in terms of their polarities. When extra components or dummy components are combined with such a poled component, they are encircled by a boundary line, thereby showing the correct polarity direction of the poled component with respect to whether it is enclosed or not.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: March 28, 2006
    Assignee: Orion Electric Co., Ltd.
    Inventor: Kazuyuki Nagata
  • Patent number: 7005586
    Abstract: In various embodiments, one or more connectors are configured to make electrical contact with side power and ground pads on a component. The connectors may include, in some embodiments, a conductive member and a compressible conductor for making electrical contact with the side pads. In some embodiments, the connectors are attached to a power board configured to be placed over a top of the component during use. In other embodiments, the connectors are attached to a socket into which the component is inserted during use. In still other embodiments, the connectors are attached to a motherboard to which the socket is attached.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 28, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Raymond S. Duley
  • Patent number: 7002813
    Abstract: An arrangement which has a panel-like electrical/electronic module, such as a solar power module, and a connection unit which are electrically connected to one another. The module and the connection unit each have an essentially flat printed conductor structure with connecting sections. The printed conductor structures are situated in parallel planes. The connecting sections are rigid electrical conductor sections and are bent out from the planes of the printed conductor structures of the connection unit and the module. The connecting sections of the connection unit are situated corresponding to the arrangement of the connecting sections of the module so that for the connection unit connected to the module each connecting section of the module is electrically connected to a respective connecting section of the connection unit and these adjoin one another in one section situated in a different spatial position than that of the planes of the printed conductor structures.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: February 21, 2006
    Assignees: Leopold Kostal GmbH & Co. KG, Solarworld AG
    Inventors: Eduard Bergmann, Herwig Rilling, Peter Westermayr, Clemens Hofbauer, Boris Klebensberger, Karsten Wambach
  • Patent number: 6994918
    Abstract: A component for use in manufacturing circuit boards, such as printed circuit boards, or flex substrates is adapted for use with pick-and-place equipment to provide a first material overlay disposed over a second material base layer. Such a component may include a first electrically conductive material disposed over a second electrically conductive material, and a soluble tape backing disposed over and attached to the second electrically conductive material. The component may be attached to a circuit board by solder relow, after which the soluble tape backing is removed. Although typical embodiments involve electrically conductive materials, it is noted that an electrically insulating material can also be disposed over and attached to an underlying material which itself is disposed on a circuit board.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: February 7, 2006
    Inventor: Morgan T. Johnson
  • Patent number: 6992898
    Abstract: A smart-card module is described which has a substrate film of an anisotropically conductive material and at least one semiconductor chip. The semiconductor chip has connection points. On one surface of the semiconductor film, contact areas are applied directly. The substrate film is disposed between the semiconductor chip and the contact areas in such a way that it connects the connection points of the semiconductor chip to the contact areas in a manner of a direct contact.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: January 31, 2006
    Assignee: Infineon Technologies AG
    Inventors: Erik Heinemann, Frank PĆ¼schner, Detlef Houdeau
  • Patent number: 6873037
    Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 29, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Publication number: 20040218375
    Abstract: The present invention provides a method of assembling a printed circuit board (PCB) module intended for attachment to another structure, such as another larger PCB. In particular, the invention provides a plurality of different mounting fixtures for a PCB for enabling the selective enhancement of the thermal characteristics of the module. One embodiment of the invention provides a module comprising a PCB having a circuit mounted thereon and fixtures that, when attached to the PCB, result in an open frame or a baseplate module. A preferred circuit for said inventive assembly is a power conversion module designed to be mounted on another PCB that requires such power conversion in close proximity to the circuit components on the other board.
    Type: Application
    Filed: May 2, 2003
    Publication date: November 4, 2004
    Inventor: Karl T. Fronk
  • Patent number: 6812570
    Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin and bismuth. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Zubair Khan, Maria Guardado, Charles Anderson
  • Patent number: 6785144
    Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6781223
    Abstract: This semiconductor device comprises a semiconductor chip, a signal lead connected to a signal electrode of the semiconductor chip, an external signal electrode connected with the signal lead, a ground lead extending along the signal lead, and a sealing resin sealing these elements. The external signal electrode is formed as a protruding electrode protruding from an undersurface of the sealing resin. One surface of the signal lead is exposed on the undersurface of the sealing resin.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Takayuki Mihara, Yuji Akasaki
  • Patent number: 6774317
    Abstract: A subtractively created interconnection scheme and apparatus, typically used with microelectronic devices, wherein a flexible support structure is attached to a conductive sheet. The conductive sheet is then selectively removed, preferably using an etching process, thereby producing a plurality of posts with tips which are substantially coplanar with respect to one another. Each post becoming an individual interconnection between the microelectronic device and a supporting substrate.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: August 10, 2004
    Assignee: Tessera, Inc.
    Inventor: Joseph C. Fjelstad
  • Patent number: 6771516
    Abstract: Methods and apparatuses for removably securing one or more computer circuit boards to a computer chassis. In one embodiment, the apparatuses include a bracket having attached sites that can be selectively aligned with corresponding fastening sites of one or more types of printed circuit boards. The circuit boards can be attached to the bracket without tools and without threaded fasteners, and the bracket can be attached to the chassis also without tools and with out threaded fasteners. The circuit boards can be grounded to the chassis solely through a compressible conductive gasket that extends between the chassis and input/output connectors of the printed circuit boards.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: August 3, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Leman, Gregory P. Johnson, R. Doug Smith, Craig L. Boe, Jacques Gagne, Philip Hartley
  • Patent number: 6757180
    Abstract: An electronic component base for an electronic component is disclosed to have a top wall adapted to accommodate an electronic component core, diagonally extended wire grooves in the top wall for guiding out lead wires of the loaded electronic component core, a bottom wall, a plurality of electrically conducting zones in the bottom wall, four peripheral walls, four chamfered angles alternatively connected between the peripheral walls, and four conducting side grooves respectively extended from the wire grooves to the electrically conducting zones for receiving the lead wires of the electronic component core from the wire grooves.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: June 29, 2004
    Assignee: Ferrico Corporation
    Inventors: Chien Yee Chiang, Ming-Tung Lai
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6735087
    Abstract: A surface-mounted module in which, after a module is assembled, each circuit element of the module can be evaluated. In addition, the whole module mounted on a substrate can be evaluated. The module including includes a module substrate; and circuit elements on the module substrate and insulated from one another, each circuit element having an independent function. Each circuit element, and the each circuit element has a terminal insulated from terminals of other circuit elements on a surface of the module substrate. A surface-mounted module further includes a base substrate that has a connection wiring to electrically connect two terminals on the module surface and supplies electric power to the module, and achieves functions by operating each circuit element connected via the wiring in response to the electric power supplied from the base substrate.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: May 11, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Inoue, Shigenori Nakatsuka
  • Patent number: 6731013
    Abstract: A wiring substrate of the present invention includes a terminal section, provided on a first surface of an insulating substrate, for wire or flip-chip bondings; a land section, provided on the insulating substrate, for an external connection terminal; wiring patterns, respectively provided on the first surface and a second surface on the other side of the first surface, for making electrical connection between the terminal section and the land section; and a support pattern, provided on the second surface corresponding in position to the terminal section, for improving bondings. The wiring substrate can relieve connection failure in bondings.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: May 4, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Juso, Yasuki Fukui, Yuji Yano, Seiji Ishihara
  • Publication number: 20040047138
    Abstract: An electronic component mounting circuit board for mounting an electronic component, comprises a circuit board, and connection pads provided on the circuit board, the connection pads being formed with a plurality of holes for inserting terminals of the electronic component.
    Type: Application
    Filed: March 11, 2003
    Publication date: March 11, 2004
    Applicant: Fuji Xerox Co., Ltd.
    Inventor: Kentaro Fukami
  • Patent number: 6687133
    Abstract: A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and “dog bones”. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: February 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Wee K. Liew, Hong T. Lim, Chengyu Guo
  • Patent number: 6677522
    Abstract: An electronic component such as a ceramic capacitor is coupled to a dielectric substrate package. Encapsulant material substantially surrounding the sides of the component, develops cracks therein, particularly near the corners of the component where CTE stresses are greatest. The cracks propagate downward into the dielectric substrate material and sever circuit lines in the substrate causing failure. A mounting pad for the component is extended from beneath the component to substantially beyond the outer periphery of the encapsulant material to prevent cracks from propagating into the dielectric material.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: January 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Charles F. Carey, Eric A. Johnson, Alfredo Migliore
  • Patent number: 6671174
    Abstract: A surge protector block assembly includes a plurality of individual 5-pin housing units which are formed integrally together. Each of the plurality of individual housing units has a plurality of surface mountable socket contacts for receiving corresponding pins of a surge protector module. A single and/or multi-layer printed circuit board is provided with a plurality of solder pads. Each of the plurality of individual housing units is surface mounted onto the solder pads of the single and/or multi-layer printed circuit board for electrical connection to corresponding ones of the plurality of the socket contacts.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: December 30, 2003
    Assignee: Illinois Tool Works Inc.
    Inventor: Richard H. Heidorn
  • Publication number: 20030117785
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Application
    Filed: February 12, 2003
    Publication date: June 26, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 6574118
    Abstract: A method for installing a printed circuit board assembly on a disk drive base plate is disclosed, as well as the corresponding structure used for this installation. Generally, the printed circuit board assembly includes a pair of bosses that are each disposed within a corresponding concave slot on the base plate. When installing the printed circuit board assembly, the bosses are disposed within their corresponding slot while the printed circuit is disposed at an angle relative to the base plate. Thereafter, the printed circuit board assembly is pivoted toward and into interfacing relation with the base plate at least generally about the bosses.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: June 3, 2003
    Assignee: Maxtor Corporation
    Inventors: Michael J. Russell, Herbert Ross Chessman, Gale D. Johnson
  • Publication number: 20030090884
    Abstract: A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 15, 2003
    Inventors: Sang-Do Lee, Yoon-Hwa Choi
  • Patent number: 6563203
    Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: May 13, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Kazuhiko Nishimura
  • Patent number: 6560117
    Abstract: Packaged microelectronic devices, interface substrates for packaging microelectronic devices, and methods of packaging single-die or stacked-die devices. One embodiment can include a die, an interface member having a die section attached to the die and an array section, and a casing encapsulating at least a portion of the die. The die section has a plurality of contacts coupled to bond-pads on the die, and the array section has an array of ball-pads coupled to the contacts by interconnecting circuitry in the interface member. The array section is folded over and/or under the die section, and the array section is attached to a backside of the die and/or a surface of the casing.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ow Chee Moon
  • Patent number: 6552910
    Abstract: A stacked-die assembly and a method of manufacturing a stacked-die assembly having a plurality of microelectronic devices. In one embodiment, a stacked-die assembly can include a first die, a second die juxtaposed to the first die, and an interface substrate coupled to the first and second dies. The first die can have a first integrated circuit and a first terminal array coupled to the first integrated circuit, and the second die can have a second integrated circuit and a second terminal array coupled to the second integrated circuit. The interface substrate can comprise a body, a first contact array on the body that is electrically coupled to the first terminal array of the first die, a second contact array on the body that is electrically coupled to the second terminal array of the second die, and at least one ball-pad array on the body.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: April 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Ow Chee Moon, Eng Meow Koon
  • Patent number: 6543738
    Abstract: A shock mount structure is shown that has one position wherein shock mount members positioned at the corners of the device are contained within the length, width, and height of the form factor with which the device complies and a second position wherein the elastomeric corner members violate the form factor, but are positioned to impact a planar surface, toward which the device is dropped, before any portion of the device, irrespective of the attitude of the device as it approaches the planar surface. To assure protection, the elastomeric corner shock mount elements are urged toward the second position by integral springs and are manually movable to the first position by overcoming the biasing force of the springs.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: April 8, 2003
    Assignee: International Business Machines Corporation
    Inventor: Gordon James Smith