Protection By Snubber Circuitry Patents (Class 361/91.7)
  • Patent number: 10957684
    Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 23, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Tobias Erlbacher, Andreas Schletz, Gudrun Rattmann
  • Patent number: 10877079
    Abstract: According to some aspects of the present disclosure, power modules having current sensing circuits, and corresponding sensing methods, are disclosed. Example power modules include a printed circuit board (PCB) having a PCB trace, an output choke inductor, and an output pin. The power module also includes a first sense terminal coupled to the PCB trace, a second sense terminal coupled to the output pin such that a resistance between the first sense terminal and the second sense terminal is defined by a resistance of the PCB trace and a resistance of the output pin, and a control coupled to the first sense terminal and the second sense terminal. The control is adapted to measure a voltage between the sense terminals, and to determine a current through the PCB trace and the output pin based on the measured voltage and the resistance between the sense terminals.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 29, 2020
    Assignee: Astec International Limited
    Inventors: Mao Xi Xiang, Jian Feng Lv, Chen Chen Zheng, Qian Feng
  • Patent number: 10756539
    Abstract: An electronic apparatus includes a first terminal that receives power supplied from an external apparatus, a second terminal that is used to determine a power supply capability of an external apparatus, an internal circuit that includes a communication control unit that communicates with an external apparatus via the second terminal, a capacitor that forms an AC coupling between the internal circuit and the second terminal, a route that bypasses the capacitor, a switch that causes the route to switch to a conductive state or a non-conductive state, and a control unit that controls the switch by determining whether a first voltage applied to the first terminal by the external apparatus exceeds a second voltage which can be applied to the internal circuit via the second terminal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 25, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takashi Morii
  • Patent number: 10511231
    Abstract: A resonant power converter includes an event generator and multiple separate resonant tanks configured as second harmonic filters. The event generator is configured to generate a predetermined resonant switching frequency to which the resonant tanks are tuned, to selectively apply voltage stress harmonic links using the resonant tanks, and to control zero voltage switching time and peak current through the switching devices. Configuring and operating the resonant power converter in the manner described herein enables the resonant power converter to maintain a substantially constant efficiency over varying input line voltage, making the efficiency of the resonant power converter substantially independent of the input line voltage value.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 17, 2019
    Assignee: Flex Ltd.
    Inventors: Mark Telefus, Nate Vince
  • Patent number: 9224726
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Matthijs Pardoen, Patrice Besse
  • Patent number: 9025290
    Abstract: A protective circuit includes a first jack, a second jack, a first control unit, a detecting circuit, and a logic control circuit. The first jack is connected to a power supply, and includes a grounding wire and a live wire. The second jack is connected to a load, and includes a grounding wire and a live wire. The first control unit includes a first relay, the first relay is connected to the live wire of the first jack and the live wire of the second jack. The detecting circuit detects whether the grounding wire of the first jack is grounded, and outputs indication signals accordingly. The logic control circuit outputs a control signal to the first control unit according to the indication signals to turn on/off the first relay, for allowing the live wire of the first jack to be connected to/disconnected from the live wire of the second jack.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 5, 2015
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Wan-Hong Zhang, Hong-Ru Zhu
  • Patent number: 9013848
    Abstract: A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct current in a forward conduction mode when an over-voltage condition occurs at a first terminal of the power transistor.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Sik K. Lui
  • Patent number: 8982520
    Abstract: A system and method for efficient input/output (I/O) port overvoltage protection of a high-speed port. An interfacing system for connecting peripheral devices to a computing system comprises ports for conveying serial communications bi-directional signals and an overvoltage protection circuit. The protection circuit prevents an overvoltage condition on one port in response to an overvoltage event on a corresponding second port. In one embodiment, the interfacing system connects USB peripheral devices to an automotive infotainment system comprising an automotive battery potiential greater than a USB power supply. In addition, the overvoltage protection circuit is able to transmit signals between the two ports without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: March 17, 2015
    Assignee: Standard Microsystems Corporation
    Inventors: Alexei A. Predtetchenski, Hans L. Magnusson
  • Publication number: 20150055262
    Abstract: A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 26, 2015
    Inventor: Kuo-Fan Lin
  • Patent number: 8958189
    Abstract: A high voltage semiconductor switch includes a first field-effect transistor having a source, a drain and a gate, and being adapted for switching a voltage at a rated high-voltage level, the first field-effect transistor being a normally-off enhancement-mode transistor, a second field-effect transistor having a source, a drain and a gate, connected in series to the first field-effect transistor, the second field-effect transistor being a normally-on depletion-mode transistor; and a control unit connected to the drain of the first field-effect transistor and to the gate of the second field-effect transistor and being operable for blocking the second field-effect transistor if a drain-source voltage across the first field-effect transistor exceeds the rated high-voltage level.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler, Anton Mauder
  • Publication number: 20150036253
    Abstract: The present invention discloses a lossless snubber circuit and an operation method thereof. The lossless snubber circuit includes a first snubber circuit. The first snubber circuit includes a first diode (D7) and a capacitor (C3). The capacitance of the capacitor (C3) is big enough so that a voltage spike generated at the moment when a switch transistor (Q1) is turned off is depressed by charging the capacitor (C3). When the switch transistor (Q1) is on, the electric charges released by the capacitor (C3) are directed to a first capacitor (C1) in a three-phase Vienna structure, so as to avoid the problem of voltage stress difference caused by the large quantity of electric charges released by the capacitor (C3) flowing back to the switch transistor (Q1).
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: Emerson Network Power Co., Ltd.
    Inventor: Meng Wang
  • Patent number: 8913362
    Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: December 16, 2014
    Assignee: Vixs Systems, Inc.
    Inventor: David Simmonds
  • Patent number: 8902557
    Abstract: A fault protector for an opto-electronic device includes a MOSFET having an integral body-diode. A capacitor is connected between a drain and a gate of the MOSFET, and a resistor is connected between the gate and a source of the MOSFET. The drain of the MOSFET is connectable to a first terminal of an opto-electronic device, and the source of the MOSFET is connectable to a second terminal of the opto-electronic device. The device overcomes problems of previously known techniques by preventing a reverse-bias voltage from exceeding an absolute maximum specified by a manufacturer, and also prevents ESD or other power-related faults from exceeding the maximum forward-bias voltage of the laser diode, while not adding significant resistance or capacitance to the laser diode, thereby not complicating the task of driving the laser diode.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: December 2, 2014
    Inventor: William R. Benner, Jr.
  • Publication number: 20140313628
    Abstract: A high voltage direct current (HVDC) hybrid circuit breaker is provided. The circuit breaker includes a solid-state main breaker, a mechanical fast disconnector and a solid-state auxiliary breaker connected in series, the series-connection of the disconnector and the auxiliary breaker being connected in parallel to the main breaker, a snubber circuit including a capacitor, and a switching device being arranged for disconnecting the snubber capacitor in response to the auxiliary breaker being opened. By disconnecting the snubber capacitor, an uncontrolled discharging of the capacitor through the disconnector and the main breaker, and the resulting non-zero current flowing through the disconnector during the breaking action, may be avoided. Further, a method of an HVDC hybrid circuit breaker is provided.
    Type: Application
    Filed: November 18, 2011
    Publication date: October 23, 2014
    Applicant: ABB Technology AG
    Inventors: Jürgen Häfner, Arman Hassanpoor
  • Publication number: 20140240883
    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.
    Type: Application
    Filed: May 12, 2014
    Publication date: August 28, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
  • Patent number: 8755163
    Abstract: A three-phase AC power controller has three strands, each having an input and an output. Five pairs of valves are connected antiparallel for rotating field reversal. The first input is connected to the first output by way of a first pair, the second input is connected to the second output by way of a second pair and to the third output by way of a third pair, and the third input is connected to the second output by way of a fourth pair and to the third output by way of a fifth pair. An RC half-branch is connected as a snubber circuit to each input and to each output. These RC half-branches are each interconnected via a transverse connection.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 17, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Grammenos Nicoltsios, Heinz Pichorner
  • Patent number: 8576528
    Abstract: A matrix converter includes a plurality of semiconductor switch modules, and a plurality of snubber modules each having a plurality of capacitors and a plurality of diodes. Each of the snubber modules has a terminal group projecting outward, a first terminal, and a second terminal. The first and second terminals project from positions different from the terminal group, and are connected to an external circuit provided outside the matrix converter. Terminals of the terminal group are connected to terminals of a corresponding semiconductor switch module. The first terminals of the plurality of snubber modules are connected to one another via a first bus bar, and the second terminals are connected to one another via a second bus bar.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Sumiaki Nagano, Makoto Kojyo, Takahiro Uchino
  • Patent number: 8570780
    Abstract: A semiconductor device includes: a parallel connection structure 1 between a first node and a second node; a first snubber device and a second snubber device having a clamp level that is the same as or higher than the output voltage of a power source section. One terminal of the first snubber device is connected through the first node to one end of the parallel connection structure, the opposite terminal of the first snubber device is connected through a third node to one terminal of the second snubber device, and the opposite terminal of the second snubber device is connected through the second node to the opposite end of the parallel connection structure. Electric power is fed back to the power source section through the second and third nodes.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinsuke Godo, Atsunobu Kawamoto
  • Publication number: 20130063853
    Abstract: A snubber circuit includes: a capacitor including a first terminal and a second terminal, where the first terminal of the capacitor is electrically connected to a first terminal of the snubber circuit; and a Bipolar Junction Transistor (BJT), where one of the emitter and the collector of the BJT is electrically connected to the second terminal of the capacitor, and the other one of the emitter and the collector of the BJT is electrically connected to a second terminal of the snubber circuit. The snubber circuit can be electrically connected in parallel to an active component or a load to protect the circuitry connected to the load, and more particularly to absorb spike or noise generated during high-frequency switching of the active component to recycle energy, in order to achieve the goal of reducing spike voltages and enhancing efficiency.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 14, 2013
    Inventor: Kuo-Fan Lin
  • Publication number: 20120287540
    Abstract: An overvoltage protection method and circuit includes a positive supply input node, an output node, and a negative supply node. The overvoltage protection circuit further includes a first functional circuit configured to turn ON a MOSFET and maintain it in a low resistance state. A second functional circuit is configured to detect an overvoltage and control the gate of the MOSFET to regulate a voltage at the output node. A third functional circuit is configured to provide a startup wherein the overvoltage protection circuit is not damaged and/or to regulate an operating voltage such that an overvoltage does not appear on the overvoltage protection circuit. The external components include the MOSFET, which has a gate coupled to the output of the charge pump of the overvoltage protection circuit.
    Type: Application
    Filed: March 19, 2012
    Publication date: November 15, 2012
    Inventors: Robert Curtis DOBKIN, David Henry SOO
  • Patent number: 8116052
    Abstract: A protection ability of a power supply control circuit is improved so as to protect an output transistor against a back electromotive voltage from a load, a dump surge voltage, and a positive spike surge voltage which has a smaller energy but is higher than the dump surge voltage. The power supply control circuit includes: an output MOS transistor (power semiconductor device) connected between a first power supply terminal and an output terminal; a load connected to the output terminal; a first dynamic clamping circuit for controlling a voltage difference between a first power supply line and the output terminal; and a first switch connected between the first dynamic clamping circuit and the output MOS transistor, in which a conductive state is determined according to a result of comparison between a reference voltage and a voltage at the output terminal.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Nakahara
  • Publication number: 20120019970
    Abstract: A matrix converter includes a plurality of semiconductor switch modules, and a plurality of snubber modules each having a plurality of capacitors and a plurality of diodes. Each of the snubber modules has a terminal group projecting outward, a first terminal, and a second terminal. The first and second terminals project from positions different from the terminal group, and are connected to an external circuit provided outside the matrix converter. Terminals of the terminal group are connected to terminals of a corresponding semiconductor switch module. The first terminals of the plurality of snubber modules are connected to one another via a first bus bar, and the second terminals are connected to one another via a second bus bar.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 26, 2012
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Sumiaki NAGANO, Makoto KOJYO, Takahiro UCHINO
  • Patent number: 7995318
    Abstract: Power at a selected frequency in the high frequency region of the spectrum is supplied by a power converter having a wide range of input voltages. The power converter uses a source oscillator and a NOR gate. The source oscillator generates a rectangular wave at the selected frequency and supplies that signal to one of the NOR gate inputs. The rectangular wave is differentiated and the differentiated signal is supplied to the second NOR input along with a feedback signal from an amplifier controlled by the NOR gate's output.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 9, 2011
    Inventor: Murray F Feller
  • Patent number: 7924540
    Abstract: A main transistor and a reverse current prevention transistor are provided in series between an input terminal and an output terminal. An input diode is provided between a connection point of the reverse current prevention transistor and the main transistor and a reference voltage terminal in such a direction that the anode becomes the reference voltage terminal side. A control unit controls the gate voltage of the main transistor according to a DC voltage. The reverse current prevention transistor is arranged in such a direction that the anode of its body diode becomes the input terminal side. The reverse current prevention transistor is biased to be turned on in a normal state that the input terminal becomes high potential and the reference voltage terminal becomes low potential.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: April 12, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Yoichi Tamegai
  • Publication number: 20100259860
    Abstract: An overvoltage protection circuit includes an output transistor coupled between a power supply and an output terminal, the output terminal including a terminal for being coupled to a load and a dynamic clamping circuit and a clamp selection transistor coupled in series between the power supply terminal and a control terminal of the output transistor. The clamp selection transistor is coupled between the dynamic clamping circuit and a control terminal of the output transistor. In addition, the clamp selector transistor includes an N-channel type transistor, a control terminal of the N-channel type transistor being coupled to a ground potential.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 14, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Osamu Souma
  • Patent number: 7751157
    Abstract: In one embodiment, a protection circuit includes a linear regulator remains enabled during a portion of a time while limiting an output voltage of the linear regulator to a first value.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 6, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Paolo Migliavacca
  • Patent number: 7738226
    Abstract: Integrated snubber device on a semiconductor basis for wiring an electric network for absorbing electric energy from an electric energy store, of an electric network, including at least two terminals for being connected to the electric network to be wired, an electric resistor structure, and a reactance structure, which are connected between the terminals.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: June 15, 2010
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Sven Berberich, Martin Maerz
  • Publication number: 20100103706
    Abstract: A circuit arrangement for limiting excessive voltages by a forward delay time of a first diode is described. The first diode is alternately switched in a non-conducting direction and a conducting direction by switching a circuit element. The first diode is series-connected to a first capacitor and a pre-charging circuit is provided for the first capacitor, the pre-charging circuit charging the first capacitor while the first diode is switched in the non-conducting direction. The pre-charging circuit charges the first capacitor more strongly than an excessive voltage of the first diode with regard to the amount.
    Type: Application
    Filed: December 7, 2007
    Publication date: April 29, 2010
    Inventor: Harald Weinmeier
  • Patent number: 7706115
    Abstract: Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.
    Type: Grant
    Filed: November 3, 2007
    Date of Patent: April 27, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Wen-Ching Hsiung, Jeng-Dau Chang, Chia-Liang Lai, Kuan-Yu Chen
  • Patent number: 7701241
    Abstract: A circuit for protecting a DUT is disposed in parallel with a DUT which is supplied with current via wirings and switchable between conducting and non-conducting state. The circuit is switchable between conducting and non-conducing state and switched from non-conducting state to conducting state as the DUT is switched from conducting state to non-conducting state.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: April 20, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Yasunori Kumagai, Dai Shinozaki, Shigekazu Komatsu, Katsuaki Sakamoto
  • Patent number: 7616421
    Abstract: An interface system may be used to connect an electrical device to an electrical bus. The interface system may include a first end and a second end in electrical communication with the first end. Where the interface system is used to connect an electrical device to an electrical bus, the first end may be connected to the electrical bus and the second end may be connected to the electrical device. The interface system may also include a reverse current blocking circuit configured to block current from flowing from the second end to the first end. Additionally, the interface system may include a discharge circuit electrically connected between the first end and the second end for discharging the blocked current.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 10, 2009
    Assignee: Caterpillar Inc.
    Inventor: Christopher D. Hickam
  • Patent number: 7609494
    Abstract: A powered device includes a voltage protection circuit, two outputs, a switch, and a snubber circuit. The two outputs of the integrated circuit may be coupled to an external transformer. The snubber circuit of the integrated circuit is responsive to the switch and is coupled with respect to the two outputs to direct energy from at least one of the two outputs to the voltage protection circuit.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 27, 2009
    Assignee: Silicon Laboratories, Inc.
    Inventor: Richard Bruce Webb
  • Publication number: 20090128973
    Abstract: A protection ability of a power supply control circuit is improved so as to protect an output transistor against a back electromotive voltage from a load, a dump surge voltage, and a positive spike surge voltage which has a smaller energy but is higher than the dump surge voltage. The power supply control circuit includes: an output MOS transistor (power semiconductor device) connected between a first power supply terminal and an output terminal; a load connected to the output terminal; a first dynamic clamping circuit for controlling a voltage difference between a first power supply line and the output terminal; and a first switch connected between the first dynamic clamping circuit and the output MOS transistor, in which a conductive state is determined according to a result of comparison between a reference voltage and a voltage at the output terminal.
    Type: Application
    Filed: October 28, 2008
    Publication date: May 21, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Akihiro Nakahara
  • Patent number: 7525781
    Abstract: A snubber circuit for use with an integrated power supply control circuit incorporating a transformer and a lateral power MOSFET on a single silicon chip. A capacitor is provided in circuit with the MOSFET and first resistor and diode are in series with each other and the capacitor. A second resistor and diode are also in series with each other and the capacitor. The diodes provide for first current flow in one and an opposite direction and the resistors provide first and second levels of resistance respectively for damping and turn on. In another embodiment, first and second resistors are provided in series with the capacitor, and a diode is connected across one of the resistors.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: April 28, 2009
    Assignee: The Berquist Torrington Company
    Inventor: Haroon I. Yunus
  • Patent number: 7511976
    Abstract: Self-powered supplies are presented for powering a power converter switch driver with power obtained from an associated snubber circuit, in which a supply circuit and a snubber circuit are connected in a series path across the switch terminals with the supply circuit receiving electrical power from the snubber and providing power to the switch driver.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 31, 2009
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Navid Reza Zargari, Bin Wu, Weiqian Hu
  • Publication number: 20080297964
    Abstract: A first bypass circuit has first and second nodes. The first load circuit is connected between the first node and a signal input terminal of the second drive circuit. The second load circuit has substantially the same impedance as the first load circuit, and is connected between the second node and the reference potential terminal of the second drive circuit. The first drive circuit has the same reference potential as the input buffer. The second bypass circuit passes a signal of a predetermined frequency or higher between a current path formed between the first load circuit and the signal input terminal of the second drive circuit and a current path formed between the second load circuit and the reference potential terminal of the second drive circuit. The first bypass circuit passes a signal of a predetermined frequency or higher between the first and second nodes.
    Type: Application
    Filed: November 1, 2007
    Publication date: December 4, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kazuaki HIYAMA
  • Publication number: 20080285196
    Abstract: Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.
    Type: Application
    Filed: November 3, 2007
    Publication date: November 20, 2008
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Wen-Ching Hsiung, Jeng-Dau Chang, Chia-Liang Lai, Kuan-Yu Chen
  • Patent number: 7388765
    Abstract: A method and an arrangement for controlling phase-specific thyristors of a half-controlled network bridge, the method comprising identifying a thyristor to be controlled on the basis of the magnitude of phase voltage, controlling the thyristor by switching on a voltage in its gate current circuit to achieve a gate current. The controlling of the thyristor comprises the steps of leading the gate current through an inductive component of the gate current circuit to the gate of the thyristor, determining the magnitude of the gate current, alternately switching off the voltage in the gate current circuit, when the gate current is higher than a preset limit, and switching on the voltage in the gate current circuit, when the gate current is lower than a preset limit.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 17, 2008
    Assignee: ABB Oy
    Inventor: Alpo Kaulio
  • Patent number: 7385833
    Abstract: A snubber circuit and corresponding power converter topology for controlling the voltage across the resonant capacitor at turn on of a control switch so as to suppress a spike at the switch caused by the large current pulse and parasitic inductance of the power converter. The suppression of the spike reduces conduction losses and increases efficiency. According to one embodiment, the snubber circuit in a boost converter topology includes a second winding tapped from the main boost inductor and connected in series with a first diode and a second diode. A resonant capacitor and the second diode are connected in a series combination which is in parallel with the main boost diode. The second winding is connected in series with the first diode and the second diode between the output terminals of the converter. Alternatively, the snubber circuit is used in flyback, buck, and forward converter topologies.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: June 10, 2008
    Assignee: Astec International Limited
    Inventor: Lee Tai Keung
  • Patent number: 7369378
    Abstract: A surge protective circuit and a noise filter circuit are provided in a power-supplying line, the surge protective circuit is adapted for protecting a switching device from surge voltage generated during operation of an electric motor and the noise filter circuit is adapted for absorbing noise generated during operation of the switching device, each of the surge protective circuit and the noise filter circuit include a plurality of elements, wherein at least one of the plurality of the elements constructing the surge protective circuit is used as at least one of the plurality of the elements constructing the noise filter circuit in common with each other.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: May 6, 2008
    Assignee: Calsonic Kansei Corporation
    Inventors: Hideki Sunaga, Kaoru Tanaka
  • Publication number: 20070274014
    Abstract: Integrated snubber device on a semiconductor basis for wiring an electric network for absorbing electric energy from an electric energy store, of an electric network, including at least two terminals for being connected to the electric network to be wired, an electric resistor structure, and a reactance structure, which are connected between the terminals.
    Type: Application
    Filed: April 3, 2007
    Publication date: November 29, 2007
    Inventors: Sven Berberich, Martin Maerz
  • Publication number: 20070188957
    Abstract: The invention relates to an energy transfer circuit. The energy transfer circuit has a first electromagnetic induction device, electrically connected to a first power supply node; a first switch circuit for connecting the first electromagnetic induction device and a second power supply node according to a first control signal; a snubber electrically connected between the first electromagnetic induction device and the second power supply node; a second electromagnetic induction device, coupled to the first electromagnetic induction device and electrically connected to the snubber and the second power supply node; and a third electromagnetic induction device coupled to the first and second electromagnetic induction devices and electrically connected to an output port of the energy transfer circuit.
    Type: Application
    Filed: October 24, 2006
    Publication date: August 16, 2007
    Inventors: Hsiang-Chung Weng, Hsiang-Jui Hung, Sun-Chen Yang
  • Patent number: 7190564
    Abstract: A snubber circuit for use with an integrated power supply control circuit incorporating a transformer and a lateral power MOSFET on a single silicon chip. A capacitor is provided in circuit with the MOSFET and first resistor and diode are in series with each other and the capacitor. A second resistor and diode are also in series with each other and the capacitor. The diodes provide for first current flow in one and an opposite direction and the resistors provide first and second levels of resistance respectively for damping and turn on.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 13, 2007
    Assignee: The Bergquist Torrington Company
    Inventor: Haroon I. Yunus
  • Patent number: 7177128
    Abstract: It is an object of the invention to realize a snubber module which is small in size, and which can be easily handled, thereby miniaturizing a power conversion apparatus. In the invention, a snubber module (10) is configured so that twelve snubber diodes and a snubber capacitor which constitute a snubber circuit for suppressing a surge voltage are enclosed in a resin mold (101), and a P-side lead wire (103) and an N-side lead wire (104) which are two capacitor external terminals that are connected respectively to two terminals of the snubber capacitor, and six diode external terminals (102) which are connected respectively to connecting portions where respective two of the twelve snubber diodes are connected to each other are exposed from the resin mold (101).
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: February 13, 2007
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Eiji Yamamoto, Hidenori Hara
  • Patent number: 7139157
    Abstract: A field effect transistor (FET) is used as the protection circuit. The gate is grounded through an electrical element. The voltage source is connected to the drain of the FET. The load is connected to the source of the FET. At low input voltages, the FET conducts in body diode mode. At higher input voltages, the FET turns “on” and conducts more efficiently.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: November 21, 2006
    Assignee: Kyocera Wireless Corp.
    Inventor: John P. Taylor
  • Patent number: 7133268
    Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Rex M. Teggatz, Wayne Tien-Feng Chen, Joseph Devore
  • Patent number: 7099134
    Abstract: An apparatus for preventing a boost converter from an abnormal operation is provided. The boost converter includes a transformer, a full-wave rectifier circuit electrically connected to a secondary winding of the transformer, an output filter inductor, an output filter capacitor, a clamping circuit having two clamping diodes with two anodes electrically connected to each other to form a common-anode terminal, a first clamping capacitor with a first terminal electrically connected to a node joining the filter inductor and the filter capacitor, and a second terminal electrically connected to the common-anode terminal, and an energy recycle circuit, and the apparatus includes a controllable voltage source having a first terminal electrically connected to the node and a second terminal electrically connected to the energy recycle circuit.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: August 29, 2006
    Assignee: Delta Electronics Inc.
    Inventors: Jianping Ying, Teng Liu, Xingkuan Guo, Jianhong Zeng
  • Patent number: 7072162
    Abstract: A bi-directionally driven forward converter for neutral point clamping in a modified sine wave inverter maintains wave shape integrity when the half bridge output is subjected to loads of varying impedances. This bi-directionally driven forward converter is supported by a dual primary coupled to a common secondary transformer of which both primaries are wound in opposition to each other. A high frequency snubbing pulse generator outputs a series of pulses coincidental with the turn off of the half bridge power transistors and pending the polarity of the modified sine wave output would permit current flow through either of the two primary windings. Given that the transformer secondary voltage is ultimately rectified, filtered, and tied to the input of the inverter itself, reflects back an impedance to the primary winding that is non-dissipative.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 4, 2006
    Inventor: James D'Amato
  • Patent number: 7054127
    Abstract: A cable device includes an integrated surge protection circuit. In the event that, communication signals conveyed by the cable include (potentially damaging) transient voltages, the surge protection circuit integrated in the cable suppresses the transient voltages at a distance from a corresponding electronic circuit to which the cable is attached. Consequently, potentially damaging voltage transients imparted on the communication signals are clamped before reaching potentially sensitive inputs of the electronic circuit.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: May 30, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Stephen A. Scearce, Pongsak Sriwudhthanun, James C. Q. Tran
  • Patent number: 7009828
    Abstract: Self-quenching switching elements are connected in series in a semiconductor switching device. Snubber circuits including a diode, a capacitor, and a non-linear circuit are connected in parallel with the respective semiconductor switching elements. In the snubber circuit, the diode and the capacitor are connected in series, and the non-linear circuit is connected in parallel with the capacitor. The non-linear circuit includes an impedance element, a Zener diode, and a controlling semiconductor element and draws current through the controlling semiconductor element when applied voltage exceeds the Zener voltage of the Zener diode. The Zener voltage is larger than a divided voltage applied to the semiconductor element during a fault in a power system.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: March 7, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Ito, Akihiko Iwata, Akihiro Suzuki