Resistive Patents (Class 365/100)
  • Patent number: 11200956
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Larry J. Koudele, Bruce A. Liikanen, Michael Sheperek
  • Patent number: 11177014
    Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Walter Di Francesco, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey Scott McNeil, Jr.
  • Patent number: 11145344
    Abstract: A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first read operation and the state determined during the second read operation are different, and programing one or more memory cells of a second OTP anti-fuse based on a bit position of the identified uncertain bit of the first OTP anti-fuse.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventor: Xiaojun Lu
  • Patent number: 11139006
    Abstract: A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 5, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Chun Chen, Chun-Hung Lin
  • Patent number: 11094879
    Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
  • Patent number: 11094387
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 11088145
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first transistor on the substrate, wherein the first transistor includes a first source/drain electrode in the substrate. The semiconductor device further includes a second transistor on the substrate, wherein the second transistor includes a second source/drain electrode. The semiconductor device further includes an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate, and a sidewall of the insulating layer above the substrate is aligned with a sidewall of the insulating layer within the substrate.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Patent number: 11043268
    Abstract: A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Baek, Jinyoung Kim, Junho Shin
  • Patent number: 11017286
    Abstract: A neuromorphic device may include a pre-synaptic neuron, a row line extending in a row direction from the pre-synaptic neuron, a post-synaptic neuron, a column line extending in a column direction from the post-synaptic neuron, and a synapse disposed at an intersection region between the row line and the column line. The synapse may include a first node electrically connected with the row line, a second node electrically connected with the column line, and a variable resistor and a first transistor electrically coupled between the first node and the second node. The variable resistor and the first transistor may be electrically connected with each other in parallel.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 10930345
    Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
  • Patent number: 10930846
    Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Thomas R. Omstead, Cole S. Franklin
  • Patent number: 10903271
    Abstract: A multi-layer cross point memory array includes a plurality of layers, each in turn with a plurality of word lines; a plurality of intersecting lines intersecting the word lines at a plurality of points; and a plurality of memory element-transistor stacks. Each of the latter is formed on the intersecting lines; each stack in turn includes a memory element; and a complementary pair of parallel-connected field effect selection transistors including a p-FET and an n-FET, each of which has a gate, a first drain-source terminal connected to a corresponding one of the intersecting lines, and a second drain-source terminal connected to a corresponding one of the memory elements. The gate of the p-FET and the gate of an n-FET in an adjacent stack are connected to the same word line; and the mirror image is true for the n-FET and a p-FET in the adjacent stack on the opposite side.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10902912
    Abstract: An electrochemical device includes an enclosure formed over a structure and defining an area between vertical portions of the enclosure. An electrochemical channel structure includes an electrolyte formed within the area wherein the electrolyte is protected from exposure on sidewalls of the electrolyte by the enclosure.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, John Rozen, John A. Ott
  • Patent number: 10860292
    Abstract: The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 8, 2020
    Assignee: POLITECNICO DI MILANO
    Inventors: Daniele Ielmini, Simone Balatti, Stefano Ambrogio
  • Patent number: 10812084
    Abstract: A security primitive for an integrated circuit comprises an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration. The floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs).
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 20, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Dmitri Strukov, Hussein Nili Ahmadabadi, Mohammad Reza Mahmoodi, Zahra Fahimi
  • Patent number: 10804322
    Abstract: A cross-point array device includes a substrate, a first conductive line disposed over the substrate and extending in a first direction, a plurality of pillar structures disposed on the first conductive line, each of the pillar structure comprising a memory electrode, a resistive memory layer disposed along surfaces of the pillar structures, a threshold switching layer disposed on the resistive memory layer, and a second conductive line electrically connected to the threshold switching layer and extending a second direction that is not parallel to the first conductive line.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae Jung Ha
  • Patent number: 10796757
    Abstract: A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shingo Nakazawa
  • Patent number: 10770143
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Patent number: 10770140
    Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Brent Buchanan, Le Zheng
  • Patent number: 10726890
    Abstract: A resistive memory apparatus including a memory cell array and a voltage selector circuit is provided. The memory cell array includes a plurality of memory cells. The voltage selector circuit is coupled to the memory cell array. The voltage selector circuit performs a voltage applying operation on the memory cells via a plurality of different signal transmission paths. Each of the signal transmission paths passes one of the memory cells. IR drops of two of the signal transmission paths are substantially identical, and signal transmission directions thereof are different. In addition, an operating method of a resistive memory apparatus is also provided.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 28, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Lih-Wei Lin, Yu-Cheng Chuang, Sung-Yi Lee
  • Patent number: 10718676
    Abstract: Various embodiments may provide a pressure sensing electronic device. The electronic device may include a tactile sensor configured to determine an external pressure. The electronic device may also include a memory device electrically coupled to the tactile sensor. The memory device may be configured to switch from a first state to a second state upon the external pressure determined by the tactile sensor exceeding a predetermined threshold when a writing current flows through the tactile sensor and the memory device.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 21, 2020
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Xiaodong Chen, Bowen Zhu
  • Patent number: 10700131
    Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 30, 2020
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, C. Rinn Cleavelin
  • Patent number: 10692930
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jong Won Lee, Gianpaolo Spadini, Derchang Kau
  • Patent number: 10672468
    Abstract: According to one embodiment, a memory device includes a first circuit including a resistance change memory element capable of setting a low resistance state or a high resistance state according to a falling speed of an applied voltage, and a first rectifier element connected in series to the resistance change memory element, and a second circuit including a current source, and a second rectifier element connected in series to the current source, the second circuit having a mirror relationship with the first circuit.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 10643119
    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
  • Patent number: 10600801
    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Byoungkeun Son, Hyejin Cho
  • Patent number: 10600958
    Abstract: The invention is directed to a resistive memory device comprising a control unit for controlling a memory cell of the memory device. The memory cell includes a first terminal, a second terminal and a phase change segment comprising a phase-change material. The phase change segment is arranged between the first terminal and the second terminal. The phase change material is antimony. The phase change segment retains an amorphous region during a write operation. The control unit, during the write operation, applies an electrical programming pulse to the terminals to cause a portion of the phase change segment to transition from a crystalline phase to an amorphous phase comprising the amorphous region. A trailing edge duration of the electrical programming pulse is adjusted based on ambient temperature to prevent re-crystallization of the amorphous region. Shorter trailing edge durations are used at increasing ambient temperatures.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Vara S. P. Jonnalagadda, Benedikt J. Kersting, Wabe W. Koelmans, Martin Salinga, Abu Sebastian
  • Patent number: 10546634
    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
  • Patent number: 10535411
    Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 14, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Dunga, Anubhav Khandelwal, Changyuan Chen, Biswajit Ray
  • Patent number: 10497872
    Abstract: Examples herein relate to negative differential resistance devices. An example negative differential resistance device includes a first electrode and a first negative differential resistance device coupled to the first electrode. A second negative differential device is be coupled to the first negative differential resistance device. The second NDR device is different from the first NDR device. A second electrode is coupled to the second NDR device, and is electrically coupled with the first NDR device and the first electrode.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 3, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Kumar, Kate Norris
  • Patent number: 10475924
    Abstract: A ferroelectric memory device includes a substrate, a ferroelectric layer, a variable resistive memory layer and a gate electrode which are sequentially stacked on a surface of the substrate. The ferroelectric layer has any one of a plurality of different remanent polarization values depending on a resistive state of the variable resistive memory layer.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10468099
    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Yachuan Pang, Bin Gao, He Qian
  • Patent number: 10424372
    Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato
  • Patent number: 10403683
    Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.
    Type: Grant
    Filed: March 23, 2019
    Date of Patent: September 3, 2019
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, C. Rinn Cleavelin
  • Patent number: 10403682
    Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Morin, Philippe Brun, Laurent-Luc Chapelon
  • Patent number: 10388373
    Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato
  • Patent number: 10374008
    Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Jun Seong, Soon-Oh Park
  • Patent number: 10360977
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Patent number: 10318170
    Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Patent number: 10304532
    Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Adam Johnson
  • Patent number: 10289341
    Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
  • Patent number: 10262734
    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 10261977
    Abstract: A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 16, 2019
    Assignee: University of Rochester
    Inventors: Eby Friedman, Isaac Richter, Xiaochen Guo, Mohammad Kazemi, Kamil Pas, Ravi Patel, Engin Ipek, Ji Liu
  • Patent number: 10262730
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 10249368
    Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
    Type: Grant
    Filed: February 10, 2018
    Date of Patent: April 2, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10249682
    Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 2, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luiz M. Franca-Neto, Mac D. Apodaca, Christopher J. Petti
  • Patent number: 10224371
    Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U??(1) (where 0.05?X?0.1, 0.15?Y?0.25, 0.7?Z?0.8, X+Y+Z=1, 0.45?a?0.6, and 0.08?U?0.2).
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Zhe Wu, Dong-ho Ahn, Hideki Horii, Soon-oh Park, Jeong-hee Park, Jin-woo Lee, Dong-jun Seong, Seol Choi
  • Patent number: 10200014
    Abstract: There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 5, 2019
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Federico Alessandro Fabrizio Beffa
  • Patent number: 10186318
    Abstract: A sense amplifier of a resistive memory is controlled by a bit line and a reference line. A voltage sense amplifier has a bit-line input node and a reference input node. A margin enhanced pre-amplifier includes a bit-line two-terminal switching element, a bit-line capacitor, a bit-line three-terminal switching element, a reference two-terminal switching element, a reference capacitor and a reference three-terminal switching element. A read voltage difference between the voltage level of the bit line and the reference line is generated. The bit-line two-terminal switching element, the bit-line three-terminal switching element, the reference two-terminal switching element and the reference three-terminal switching element are synchronizedly switched so as to generate a margin enhanced difference between the voltage level of the bit-line input node and the voltage level of the reference input node. The margin enhanced difference is equal to or greater than three times the read voltage difference.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 22, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tzu-Hsien Yang, Meng-Fan Chang
  • Patent number: 10176868
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson