Resistive Patents (Class 365/100)
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Patent number: 10424372Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.Type: GrantFiled: April 19, 2018Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Paolo Amato
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Patent number: 10403682Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.Type: GrantFiled: May 1, 2018Date of Patent: September 3, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Pierre Morin, Philippe Brun, Laurent-Luc Chapelon
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Patent number: 10403683Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.Type: GrantFiled: March 23, 2019Date of Patent: September 3, 2019Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, C. Rinn Cleavelin
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Patent number: 10388373Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.Type: GrantFiled: April 19, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Paolo Amato
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Patent number: 10374008Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.Type: GrantFiled: July 20, 2017Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jun Seong, Soon-Oh Park
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Patent number: 10360977Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.Type: GrantFiled: March 30, 2018Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
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Patent number: 10318170Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.Type: GrantFiled: January 2, 2018Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
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Patent number: 10304532Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.Type: GrantFiled: December 28, 2017Date of Patent: May 28, 2019Assignee: Micron Technology, Inc.Inventor: Adam Johnson
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Patent number: 10289341Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Patent number: 10262734Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.Type: GrantFiled: October 30, 2017Date of Patent: April 16, 2019Assignee: Micron Technology, Inc.Inventor: Jun Liu
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Patent number: 10261977Abstract: A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.Type: GrantFiled: May 4, 2017Date of Patent: April 16, 2019Assignee: University of RochesterInventors: Eby Friedman, Isaac Richter, Xiaochen Guo, Mohammad Kazemi, Kamil Pas, Ravi Patel, Engin Ipek, Ji Liu
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Patent number: 10262730Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: GrantFiled: January 12, 2018Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
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Patent number: 10249368Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.Type: GrantFiled: February 10, 2018Date of Patent: April 2, 2019Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 10249682Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.Type: GrantFiled: August 23, 2017Date of Patent: April 2, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Luiz M. Franca-Neto, Mac D. Apodaca, Christopher J. Petti
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Patent number: 10224371Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U??(1) (where 0.05?X?0.1, 0.15?Y?0.25, 0.7?Z?0.8, X+Y+Z=1, 0.45?a?0.6, and 0.08?U?0.2).Type: GrantFiled: February 1, 2017Date of Patent: March 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Zhe Wu, Dong-ho Ahn, Hideki Horii, Soon-oh Park, Jeong-hee Park, Jin-woo Lee, Dong-jun Seong, Seol Choi
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Patent number: 10200014Abstract: There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.Type: GrantFiled: July 8, 2016Date of Patent: February 5, 2019Assignee: MediaTek Singapore Pte. Ltd.Inventor: Federico Alessandro Fabrizio Beffa
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Patent number: 10186318Abstract: A sense amplifier of a resistive memory is controlled by a bit line and a reference line. A voltage sense amplifier has a bit-line input node and a reference input node. A margin enhanced pre-amplifier includes a bit-line two-terminal switching element, a bit-line capacitor, a bit-line three-terminal switching element, a reference two-terminal switching element, a reference capacitor and a reference three-terminal switching element. A read voltage difference between the voltage level of the bit line and the reference line is generated. The bit-line two-terminal switching element, the bit-line three-terminal switching element, the reference two-terminal switching element and the reference three-terminal switching element are synchronizedly switched so as to generate a margin enhanced difference between the voltage level of the bit-line input node and the voltage level of the reference input node. The margin enhanced difference is equal to or greater than three times the read voltage difference.Type: GrantFiled: March 28, 2018Date of Patent: January 22, 2019Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Tzu-Hsien Yang, Meng-Fan Chang
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Patent number: 10176868Abstract: Memory systems and memory programming methods are described.Type: GrantFiled: December 20, 2013Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Makoto Kitagawa, Adam Johnson
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Patent number: 10157673Abstract: Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.Type: GrantFiled: December 28, 2017Date of Patent: December 18, 2018Assignee: Micron Technology, Inc.Inventor: Adam Johnson
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Patent number: 10147879Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to integrated circuit fabrics including correlated electron switch devices having various impedance characteristics.Type: GrantFiled: September 30, 2015Date of Patent: December 4, 2018Assignee: ARM Ltd.Inventor: Lucian Shifren
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Patent number: 10141503Abstract: A metal liner is deposited conformally to a pore within a first dielectric material of a semiconductor device. The pore extends through the first dielectric material to a top surface of a first metal electrode. The metal liner is etched such that the metal liner only substantially remains on sidewalls of the pore. A phase change material is selectively deposited within the pore of the first dielectric layer to substantially fill the pore with the phase change material. The selective deposition of the phase change material produces a growth rate of phase change material on the metal liner at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the first dielectric material.Type: GrantFiled: November 3, 2017Date of Patent: November 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. BrightSky, Robert Bruce, Takeshi Masuda
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Patent number: 10141508Abstract: Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.Type: GrantFiled: November 9, 2016Date of Patent: November 27, 2018Assignee: Micron Technology, Inc.Inventors: Antonino Rigano, Fabio Pellizzer
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Patent number: 10127981Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.Type: GrantFiled: April 30, 2018Date of Patent: November 13, 2018Assignee: ARM Ltd.Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
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Patent number: 10115473Abstract: Described are methods, systems and devices for operation of correlated electron switch (CES) devices. A CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. A programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.Type: GrantFiled: April 6, 2017Date of Patent: October 30, 2018Assignee: ARM Ltd.Inventors: Mudit Bhargava, Vikas Chandra
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Patent number: 10079060Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.Type: GrantFiled: April 24, 2017Date of Patent: September 18, 2018Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Hagop Nazarian, Lin Shih Liu
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Patent number: 10049748Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.Type: GrantFiled: April 28, 2017Date of Patent: August 14, 2018Assignee: SK Hynix Inc.Inventors: Yong Hwan Hong, Byung Ryul Kim
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Patent number: 10049733Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.Type: GrantFiled: October 31, 2014Date of Patent: August 14, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Naveen Muralimanohar, Erik Ordentlich, Yoocharn Jeon
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Patent number: 10037803Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.Type: GrantFiled: December 29, 2016Date of Patent: July 31, 2018Assignee: HGST NETHERLANDS BVInventors: Evangelos S. Eleftheriou, Angeliki Pantazi, Nikolaos Papandreou, Haris Pozidis, Abu Sebastian
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Patent number: 10008248Abstract: Devices or circuits based on spin torque transfer (STT) and Spin Hall effect are disclosed by using a spin Hall effect (SHE) metal layer coupled to a magnetic free layer for various applications. The efficiency or strength of the STT effect based on this combination of SHE and STT can be enhanced by an interface modification between the SHE metal layer and the magnetic free layer or by modifying or engineering the SHE metal layer by doping the SHE metal with certain impurities or other means.Type: GrantFiled: July 17, 2015Date of Patent: June 26, 2018Assignee: Cornell UniversityInventors: Robert A Buhrman, Minh-hai Nguyen, Chi-feng Pai, Daniel C Ralph
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Patent number: 10008262Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.Type: GrantFiled: October 20, 2017Date of Patent: June 26, 2018Assignee: SK HYNIX INC.Inventor: Seok-Joon Kang
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Patent number: 10008667Abstract: Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith which includes carbon and tungsten doped with nitrogen are disclosed and described. Such electrodes have a low contact resistance with the phase change material and a high thermal stability from room temperature to temperatures needed for programming operations.Type: GrantFiled: August 29, 2014Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Luca Fumagalli, Carla M. Lazzari, Valter Soncini
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Patent number: 9947402Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.Type: GrantFiled: February 27, 2017Date of Patent: April 17, 2018Assignee: ARM Ltd.Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
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Patent number: 9947400Abstract: A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell—that is, the tendency of the resistive change memory cell to retain its programmed resistive state—may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell.Type: GrantFiled: April 22, 2016Date of Patent: April 17, 2018Inventor: Darlene Viviani
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Patent number: 9940978Abstract: Embodiments include circuits, apparatuses, and systems for programmable memory device sense amplifiers. In embodiments, an electronic circuit may include a programmable memory device having a first resistance in a first state and a second resistance in a second state, a reference element, an amplifier to generate a first output signal based at least in part on the resistance of the programmable memory device and a second output signal based at least in part on a current from the reference element, and a comparator to determine a state of the programmable memory device based on the first and second output signals from the amplifier. Other embodiments may be described and claimed.Type: GrantFiled: October 24, 2016Date of Patent: April 10, 2018Assignee: INTEL IP CORPORATIONInventor: El Mehdi Boujamaa
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Patent number: 9921782Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.Type: GrantFiled: January 29, 2016Date of Patent: March 20, 2018Assignee: Avalanche Technology, Inc.Inventor: Dean K. Nobunaga
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Patent number: 9917139Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.Type: GrantFiled: December 20, 2016Date of Patent: March 13, 2018Inventors: Claude L. Bertin, C. Rinn Cleavelin, Thomas Rueckes, X. M. Henry Huang
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Patent number: 9875799Abstract: Memories having a plurality of cell pairs, where each cell pair of the plurality of cell pairs is programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in a memory are useful in mitigating match errors, such as in a CAM (Content Addressable Memory) memory device.Type: GrantFiled: January 8, 2016Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Tommaso Vali, Kenneth J. Eldredge, Vishal Sarin
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Patent number: 9865344Abstract: An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.Type: GrantFiled: July 6, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventor: Mi-Jung Kim
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Patent number: 9865348Abstract: A memory driving device and a method thereof applied for a RRAM array are provided. The memory driving device includes a voltage generator, a current detector, and a controller. The voltage generator generates a write voltage. An RRAM cell of the RRAM array is selected according to a selection signal for receiving the program voltage to generate a program current. The current detector detects the program current. The controller executes a driving procedure which includes: obtaining a voltage distribution for the program voltage; determining the initial voltage and the maximum voltage of the program voltage according to the voltage distribution; gradually increasing the program voltage from the initial voltage to the maximum voltage; determining whether the program current exceeds the reference current; and selecting another RRAM cell when the write current exceeds the reference current.Type: GrantFiled: August 23, 2016Date of Patent: January 9, 2018Assignee: Winbond Electronics Corp.Inventor: Chien-Min Wu
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Patent number: 9858999Abstract: The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.Type: GrantFiled: December 16, 2015Date of Patent: January 2, 2018Assignee: Micron Technology, Inc.Inventors: Alessandro Calderoni, Massimo Ferro, Paolo Fantini
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Patent number: 9851738Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.Type: GrantFiled: August 13, 2015Date of Patent: December 26, 2017Assignee: ARM Ltd.Inventors: Bal S. Sandhu, George McNeil Lattimore, Robert Campbell Aitken
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Patent number: 9852793Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses.Type: GrantFiled: June 23, 2016Date of Patent: December 26, 2017Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Glen Rosendale
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Patent number: 9847130Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.Type: GrantFiled: June 28, 2016Date of Patent: December 19, 2017Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Patent number: 9837469Abstract: An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.Type: GrantFiled: June 29, 2016Date of Patent: December 5, 2017Assignee: Cypress Semiconductor CorporationInventors: Seungmoo Choi, Sameer S. Haddad
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Patent number: 9837153Abstract: Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.Type: GrantFiled: March 24, 2017Date of Patent: December 5, 2017Assignee: Western Digital Technologies, Inc.Inventors: Bijesh Rajamohanan, Christopher Petti, Xinde Hu
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Patent number: 9830996Abstract: The present disclosure provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.Type: GrantFiled: October 25, 2016Date of Patent: November 28, 2017Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Chia Chi Yang
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Patent number: 9824752Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.Type: GrantFiled: July 11, 2016Date of Patent: November 21, 2017Assignee: Rambus Inc.Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis
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Patent number: 9824751Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.Type: GrantFiled: June 3, 2016Date of Patent: November 21, 2017Assignee: SK HYNIX INC.Inventor: Seok-Joon Kang
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Patent number: 9818467Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.Type: GrantFiled: September 13, 2016Date of Patent: November 14, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Nao Matsuoka, Kosuke Hatsuda, Katsuhiko Hoya
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Patent number: 9818478Abstract: Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.Type: GrantFiled: December 9, 2013Date of Patent: November 14, 2017Assignee: Attopsemi Technology Co., LTDInventor: Shine C. Chung