Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: The present disclosure relates to a device for determining and/or monitoring temperature of a liquid, comprising a temperature sensor, a reference element for in-situ calibration and/or validation of a temperature sensor and an electronics unit, wherein the reference element is composed at least partially of a material, in the case of which at least one phase transformation occurs at at least a first predetermined phase transformation temperature in a temperature range relevant for calibrating the temperature sensor, in which phase transformation the material remains in the solid phase. According to the present disclosure, the electronics unit is embodied to supply the reference element with a dynamic excitation signal. Furthermore, the present disclosure relates to a method for calibration and/or validation of a temperature sensor based on a device of the invention.

Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.

Abstract: A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.

Abstract: A static direct-access memory block for a receiving sensor, including a memory cell array, a row address decoder, a column data multiplexer, a read and write module having a read amplifier and a write driver, a control logic circuit, a data input, and a data output. The static direct-access memory block has internal memory clocking. At least one adder for adding input data coming in through the data input is integrated in the static direct-access memory block. The at least one adder is situated between the data input and the read and write module. This allows the read and write operations to be optimized and, thus, the power consumption to be decreased. A receiving sensor for a radar or lidar system, including an application-specific integrated circuit. The application-specific integrated circuit includes at least one static direct-access memory block.

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

Abstract: A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.

Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.

Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

Abstract: According to the present invention, there is provided a recording medium comprising a substrate, a platinum layer formed on the substrate and having a (111) plane preferentially oriented, and a fullerene single crystal thin film formed on the platinum layer, and configured to be a recording layer, wherein an average value of average surface roughness Ra's with respect to four or more visual fields measured by using an atomic force microscope in a surface of the fullerene thin film is 0.5 nm or less.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

Abstract: Spin switch devices with voltage controlled magnetism in ultra-low power usage applications are disclosed. The spin switch devices may be configured to provide ultra-low power and ultra-high speed switching by directly controlling drain or gate electron spins via electric field induced magnetic anisotropy tuned with finite gate voltage. A lateral spin switch with voltage controlled magnetic drain is placed in an “OFF” or an “ON” state by controlling the gate voltage to be equal to 0 or greater than 0 volts respectively. A vertical spin switch with voltage controlled magnetic gate is placed in an “OFF” or an “ON” state by controlling a value of the gate voltage to be less than a threshold voltage or greater than the threshold voltage respectively. A voltage controlled complementary switch provides a very large gain by controlling a value of the gate voltage to be equal to 0 volts.

Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Abstract: The present disclosure provides a sense amplifier. The sense amplifier includes a first inverting circuit, a second inverting circuit, a capacitor, and a write-back path circuit. The first inverting circuit has a first input end and a first output end, and the first input end receives a first bit line signal from a memory cell. The second inverting circuit has a second input end and a second output end, wherein the second input is coupled to the first output end, and the second output end is coupled to the first input end, and the second input end receives a second bit line signal from the memory cell. The capacitor receives a boost signal and generates a boosted voltage according to the boost signal during a write-back timing period. The write-back path circuit transports the boosted voltage to one of the first and second input ends during the write-back timing period.

Abstract: Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage element including a ferroelectric material, and operating the memory cell in a volatile operating mode and a nonvolatile operating mode. The option of operating the memory cell in the volatile operating mode enables the associated advantages of high memory speed at long endurance, wherein, however, the option of operating the memory cell in the nonvolatile operating mode can bridge gaps in the power supply.

Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.

Abstract: The invention is an electronic device including a ferroelectric random access memory (FRAM), a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) receive a first supply voltage of the first supply voltage domain and providing a second supply voltage of the second supply voltage domain. The second supply voltage domain supplies the FRAM. The LDO switches between a first state providing and maintaining the second supply voltage of the second supply voltage domain and a second state providing a high impedance output to the second supply voltage domain. The electronic device switches the LDO from the first state to the second state in response to a failure of the first supply voltage domain.

Abstract: A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer.

Abstract: According to this method for producing a magnetic tunnel junction, a film of a dielectric material capable of acting as a tunnel barrier is deposited between two nanocrystalline or amorphous magnetic films. The dielectric material constituting the tunnel barrier consists of an at least partially crystalline perovskite, and said material is deposited by ion beam sputtering in a vacuum chamber.

Abstract: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V1, Va, Vb and Vc, which satisfy predetermined inequality set corresponding to the one of the first to third states, are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively.

Abstract: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.

Abstract: A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate.

Abstract: A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors.

Abstract: A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer.

Abstract: A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV3 and INV4 of FIG. 1); a nonvolatile storage part (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a and Q2b) that utilizes the hysteresis characteristic of a ferroelectric element to store, in a nonvolatile manner, the data held in the loop structure part (LOOP); and a circuit isolating part (MUX1, MUX2, INV6, INV7, SW3 and SW4) that electrically isolates the loop structure part (LOOP) from the nonvolatile storage part.

Abstract: A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode.

Abstract: A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout.

Abstract: A novel pyroelectric compound is presented. The compound is inorganic, quasi-amorphous oxide compound of a metal, mixture of metals or semiconducting element.

Abstract: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines.

Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.

Abstract: A memory includes word lines; plate lines; first to eighth bit lines; cell transistors; ferroelectric capacitor connected in parallel with cell transistors; sense amplifiers, wherein cell transistors and ferroelectric capacitors configure cells, the cells are connected in series to configure first to eighth cell blocks, the cell blocks are connected to the same word lines, first ends of the cell blocks are respectively connected to the bit lines, second ends of the cell blocks are respectively connected to the different plate lines, one of the first to the fourth bit lines and one of the fifth to the eighth bit lines are configured to be selectively connected to the sense amplifier during an operation, numbers of the cells connected in series between the bit lines and the plate lines are different in the first to the fourth cell blocks, and are different in the fifth to the eighth cell blocks.

Abstract: A ferroelectric memory device includes: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation.

Abstract: A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.

Abstract: A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.

Abstract: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that is coupled to the first polarization. The writer performs a write operation in which a write potential is imposed across the first and second storage layers, such that the first coercive potential is exceeded across the first storage layer and the second coercive potential is exceeded across the second storage layer. The reader performs a read operation in which a read potential is imposed across the first and second storage layers, such that the second coercive potential is exceeded across the second storage layer and the first coercive potential is not exceeded across the first storage layer.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.

Abstract: A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.

Abstract: A magnetoresistive resistor memory cell having four individually polarizable magnetoresistive resistors that form a magnetoresistive bridge circuit. Each of the four magnetoresistive resistors is surrounded by a write trace segment pair. One upper write trace segment is directly above a magnetoresistive resistor and one lower write trace segment is directly below that resistor. The two write traces of a write trace segment pair are oriented at 90 degrees relative to the anisotropic axis, that is, the length, of the magnetoresistive resistor. The combination of the magnetoresistive resistor bridge circuit and four write trace segment pairs forms a magnetoresistive resistor memory cell.

Abstract: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization state; a plurality of data lines; a plurality of charge transfer circuits that connect the plurality of bit lines to the plurality of data lines, respectively, based on a potential on each of the bit lines; a capacitor connected to each of the plurality of data lines for storing negative charge; a positive charge canceling circuit that pulls out positive charge corresponding to the amount of “0” data readout charge from each of the plurality of bit lines; and a sense amplifier that judges data read out from the memory cells.