Ferroelectric Patents (Class 365/117)
  • Patent number: 10839881
    Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10839882
    Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10418083
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10339985
    Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner
  • Patent number: 10217502
    Abstract: A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: February 26, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Takashi Yamada
  • Patent number: 10153054
    Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Marcello Mariani, Giorgio Servalli, Andrea Locatelli
  • Patent number: 10049720
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 14, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chika Tanaka, Keiji Ikeda, Toshinori Numata, Tsutomu Tezuka
  • Patent number: 10033383
    Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Stefan Duenkel, Sven Beyer
  • Patent number: 10008232
    Abstract: According to the present invention, there is provided a recording medium comprising a substrate, a platinum layer formed on the substrate and having a (111) plane preferentially oriented, and a fullerene single crystal thin film formed on the platinum layer, and configured to be a recording layer, wherein an average value of average surface roughness Ra's with respect to four or more visual fields measured by using an atomic force microscope in a surface of the fullerene thin film is 0.5 nm or less.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: June 26, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Sho Tonegawa, Masatoshi Ichikawa, Kenzo Hanawa
  • Patent number: 9847117
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura, Charles L. Ingalls
  • Patent number: 9830969
    Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: November 28, 2017
    Assignee: NAMLAB GGMBH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic
  • Patent number: 9646666
    Abstract: Spin switch devices with voltage controlled magnetism in ultra-low power usage applications are disclosed. The spin switch devices may be configured to provide ultra-low power and ultra-high speed switching by directly controlling drain or gate electron spins via electric field induced magnetic anisotropy tuned with finite gate voltage. A lateral spin switch with voltage controlled magnetic drain is placed in an “OFF” or an “ON” state by controlling the gate voltage to be equal to 0 or greater than 0 volts respectively. A vertical spin switch with voltage controlled magnetic gate is placed in an “OFF” or an “ON” state by controlling a value of the gate voltage to be less than a threshold voltage or greater than the threshold voltage respectively. A voltage controlled complementary switch provides a very large gain by controlling a value of the gate voltage to be equal to 0 volts.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Deepanjan Datta, Vinayak Bharat Naik, Murali V R M Kota
  • Patent number: 9514797
    Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: December 6, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fan Chu, Shan Sun, Alan D DeVilbiss, Thomas Davenport
  • Patent number: 9406355
    Abstract: The present disclosure provides a sense amplifier. The sense amplifier includes a first inverting circuit, a second inverting circuit, a capacitor, and a write-back path circuit. The first inverting circuit has a first input end and a first output end, and the first input end receives a first bit line signal from a memory cell. The second inverting circuit has a second input end and a second output end, wherein the second input is coupled to the first output end, and the second output end is coupled to the first input end, and the second input end receives a second bit line signal from the memory cell. The capacitor receives a boost signal and generates a boosted voltage according to the boost signal during a write-back timing period. The write-back path circuit transports the boosted voltage to one of the first and second input ends during the write-back timing period.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 2, 2016
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Yu-Lin Chen
  • Patent number: 9368182
    Abstract: Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage element including a ferroelectric material, and operating the memory cell in a volatile operating mode and a nonvolatile operating mode. The option of operating the memory cell in the volatile operating mode enables the associated advantages of high memory speed at long endurance, wherein, however, the option of operating the memory cell in the nonvolatile operating mode can bridge gaps in the power supply.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: June 14, 2016
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Johannes Mueller
  • Patent number: 8854857
    Abstract: The invention is an electronic device including a ferroelectric random access memory (FRAM), a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) receive a first supply voltage of the first supply voltage domain and providing a second supply voltage of the second supply voltage domain. The second supply voltage domain supplies the FRAM. The LDO switches between a first state providing and maintaining the second supply voltage of the second supply voltage domain and a second state providing a high impedance output to the second supply voltage domain. The electronic device switches the LDO from the first state to the second state in response to a failure of the first supply voltage domain.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ruediger Kuhn, Adi Baumann, Ronald Nerlich, Matthias Arnold, Christian Sichert, Ralph Ledwa
  • Patent number: 8854858
    Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Craig Bartling, Sudhanshu Khanna
  • Patent number: 8743586
    Abstract: A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventor: Dennis M. Newns
  • Patent number: 8669122
    Abstract: According to this method for producing a magnetic tunnel junction, a film of a dielectric material capable of acting as a tunnel barrier is deposited between two nanocrystalline or amorphous magnetic films. The dielectric material constituting the tunnel barrier consists of an at least partially crystalline perovskite, and said material is deposited by ion beam sputtering in a vacuum chamber.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: March 11, 2014
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Bernard Viala, Marie-Claire Cyrille, Bernard Dieny, Kévin Garello, Olivier Redon
  • Patent number: 8565001
    Abstract: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V1, Va, Vb and Vc, which satisfy predetermined inequality set corresponding to the one of the first to third states, are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Kaneko
  • Patent number: 8493768
    Abstract: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 23, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chunwon Byun, ByeongHoon Kim, Sung Min Yoon, Shinhyuk Yang, Min Ki Ryu, Chi-Sun Hwang, Sang-Hee Park, Kyoung Ik Cho
  • Patent number: 8467223
    Abstract: A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 18, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8385099
    Abstract: A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Kaneko, Yoshihisa Kato, Hiroyuki Tanaka
  • Publication number: 20130033918
    Abstract: A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer.
    Type: Application
    Filed: February 2, 2012
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Dennis M. Newns
  • Patent number: 8254156
    Abstract: A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV3 and INV4 of FIG. 1); a nonvolatile storage part (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a and Q2b) that utilizes the hysteresis characteristic of a ferroelectric element to store, in a nonvolatile manner, the data held in the loop structure part (LOOP); and a circuit isolating part (MUX1, MUX2, INV6, INV7, SW3 and SW4) that electrically isolates the loop structure part (LOOP) from the nonvolatile storage part.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: August 28, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Hiromitsu Kimura
  • Patent number: 8199554
    Abstract: A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Hashimoto, Daisaburo Takashima
  • Patent number: 8199555
    Abstract: A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: June 12, 2012
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Kaneko
  • Patent number: 8182719
    Abstract: A novel pyroelectric compound is presented. The compound is inorganic, quasi-amorphous oxide compound of a metal, mixture of metals or semiconducting element.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 22, 2012
    Assignee: Yeda Research and Development Company Ltd.
    Inventor: Igor Lubomirsky
  • Patent number: 8081500
    Abstract: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: December 20, 2011
    Assignee: Ramtron International Corporation
    Inventors: Craig Taylor, Fan Chu, Shan Sun
  • Patent number: 8077494
    Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: December 13, 2011
    Assignee: Patrenella Capital Ltd., LLC
    Inventor: Hideaki Miyamoto
  • Patent number: 8064240
    Abstract: A memory includes word lines; plate lines; first to eighth bit lines; cell transistors; ferroelectric capacitor connected in parallel with cell transistors; sense amplifiers, wherein cell transistors and ferroelectric capacitors configure cells, the cells are connected in series to configure first to eighth cell blocks, the cell blocks are connected to the same word lines, first ends of the cell blocks are respectively connected to the bit lines, second ends of the cell blocks are respectively connected to the different plate lines, one of the first to the fourth bit lines and one of the fifth to the eighth bit lines are configured to be selectively connected to the sense amplifier during an operation, numbers of the cells connected in series between the bit lines and the plate lines are different in the first to the fourth cell blocks, and are different in the fifth to the eighth cell blocks.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Patent number: 8014186
    Abstract: A ferroelectric memory device includes: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: September 6, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hiromitsu Kimura, Takaaki Fuchikami, Yoshikazu Fujimori
  • Patent number: 7990750
    Abstract: A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidehiro Shiga, Daisaburo Takashima
  • Patent number: 7990749
    Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: August 2, 2011
    Assignee: Radiant Technology, Inc.
    Inventor: Joseph Tate Evans, Jr.
  • Patent number: 7920404
    Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: April 5, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir K. Madan, Hugh P. Mcadams
  • Patent number: 7898837
    Abstract: A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh P. McAdams, Scott R. Summerfelt
  • Patent number: 7894249
    Abstract: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer interposed between the first magnetic layer and the second magnetic layer. Magnetization of the first magnetic layer and magnetization of the second magnetic layer are antiferromagnetically coupled. One of the two magnetic layers is in contact with one end of the free layer in a long-axis direction, and the other of the two magnetic layers is in contact with the other end of the free layer in the long-axis direction.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 22, 2011
    Assignee: NEC Corporation
    Inventors: Ryusuke Nebashi, Tetsuhiro Suzuki
  • Patent number: 7830696
    Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichiro Shiratake
  • Patent number: 7821808
    Abstract: A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that is coupled to the first polarization. The writer performs a write operation in which a write potential is imposed across the first and second storage layers, such that the first coercive potential is exceeded across the first storage layer and the second coercive potential is exceeded across the second storage layer. The reader performs a read operation in which a read potential is imposed across the first and second storage layers, such that the second coercive potential is exceeded across the second storage layer and the first coercive potential is not exceeded across the first storage layer.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: October 26, 2010
    Assignee: Seagate Technology LLC
    Inventors: Tong Zhao, Martin Gerard Forrester, Florin Zavaliche, Joachim Ahner
  • Patent number: 7733681
    Abstract: A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: June 8, 2010
    Inventor: Hideaki Miyamoto
  • Patent number: 7733682
    Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Sudhir K. Madan
  • Patent number: 7724566
    Abstract: A magnetoresistive resistor memory cell having four individually polarizable magnetoresistive resistors that form a magnetoresistive bridge circuit. Each of the four magnetoresistive resistors is surrounded by a write trace segment pair. One upper write trace segment is directly above a magnetoresistive resistor and one lower write trace segment is directly below that resistor. The two write traces of a write trace segment pair are oriented at 90 degrees relative to the anisotropic axis, that is, the length, of the magnetoresistive resistor. The combination of the magnetoresistive resistor bridge circuit and four write trace segment pairs forms a magnetoresistive resistor memory cell.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: May 25, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Lance L. Sundstrom
  • Patent number: 7724561
    Abstract: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization state; a plurality of data lines; a plurality of charge transfer circuits that connect the plurality of bit lines to the plurality of data lines, respectively, based on a potential on each of the bit lines; a capacitor connected to each of the plurality of data lines for storing negative charge; a positive charge canceling circuit that pulls out positive charge corresponding to the amount of “0” data readout charge from each of the plurality of bit lines; and a sense amplifier that judges data read out from the memory cells.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: May 25, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Mitsuhiro Yamamura
  • Patent number: 7639342
    Abstract: A ferroelectric composite includes a core including a ferroelectric material and a skin layer including a carbon structure comprising carbon atoms.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: December 29, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyung Hwang, Byeong-Seob Ban
  • Patent number: 7604877
    Abstract: A ferroelectric film includes a plurality of ferroelectric nanodomains configured in a regularly staggered fashion. The ferroelectric film has a quasi 2-dimensional configuration and is comprised of a ferroelectric material. A method for forming a ferroelectric film is also provided. A ferroelectric film comprised of a ferroelectric material is prepared. The ferroelectric film has a quasi 2-dimensional configuration and defines a direction that is normal to the quasi 2-dimensional configuration. An electric field along the normal direction is applied to the ferroelectric film, thereby the ferroelectric film having an array of ferroelectric nanodomains configured in a regularly staggered fashion is obtained.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: October 20, 2009
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Hui Duan, Zhong-Qing Wu, Jian Wu, Bing-Lin Gu
  • Patent number: 7593250
    Abstract: A ferroelectric nanostructure formed as a low dimensional nano-scale ferroelectric material having at least one vortex ring of polarization generating an ordered toroid moment switchable between multi-stable states. A stress-free ferroelectric nanodot under open-circuit-like electrical boundary conditions maintains such a vortex structure for their local dipoles when subject to a transverse inhomogeneous static electric field controlling the direction of the macroscopic toroidal moment. Stress is also capable of controlling the vortex's chirality, because of the electromechanical coupling that exists in ferroelectric nanodots.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: September 22, 2009
    Assignee: Board of Trustees of the University of Arkansas
    Inventors: Ivan I. Naumov, Laurent M. Bellaiche, Sergey A. Prosandeev, Inna V. Ponomareva, Igor A. Kornev
  • Patent number: 7558098
    Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 7, 2009
    Inventor: Hideaki Miyamoto
  • Patent number: 7471551
    Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: December 30, 2008
    Assignee: TDK Corporation
    Inventor: Tohru Oikawa
  • Patent number: 7436689
    Abstract: When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 14, 2008
    Assignee: Fujitsu Limited
    Inventor: Isao Fukushi
  • Patent number: 7428162
    Abstract: A memory device including: a lower electrode; a ferroelectric layer formed above the lower electrode; a charge compensation layer formed above the ferroelectric layer and including an oxide having a composition differing from a composition of the ferroelectric layer; and upper electrodes formed above the charge compensation layer. The upper electrodes includes: a saturated polarization forming electrode used for forming a domain polarized to saturation in a predetermined direction in a predetermined region of the ferroelectric layer; a writing electrode disposed apart from the saturated polarization forming electrode; and a reading electrode disposed apart from the writing electrode.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: September 23, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Kijima, Yasuaki Hamada, Tatsuya Shimoda