Abstract: A ferroelectric composite includes a core including a ferroelectric material and a skin layer including a carbon structure comprising carbon atoms.

Abstract: A ferroelectric film includes a plurality of ferroelectric nanodomains configured in a regularly staggered fashion. The ferroelectric film has a quasi 2-dimensional configuration and is comprised of a ferroelectric material. A method for forming a ferroelectric film is also provided. A ferroelectric film comprised of a ferroelectric material is prepared. The ferroelectric film has a quasi 2-dimensional configuration and defines a direction that is normal to the quasi 2-dimensional configuration. An electric field along the normal direction is applied to the ferroelectric film, thereby the ferroelectric film having an array of ferroelectric nanodomains configured in a regularly staggered fashion is obtained.

Abstract: A ferroelectric nanostructure formed as a low dimensional nano-scale ferroelectric material having at least one vortex ring of polarization generating an ordered toroid moment switchable between multi-stable states. A stress-free ferroelectric nanodot under open-circuit-like electrical boundary conditions maintains such a vortex structure for their local dipoles when subject to a transverse inhomogeneous static electric field controlling the direction of the macroscopic toroidal moment. Stress is also capable of controlling the vortex's chirality, because of the electromechanical coupling that exists in ferroelectric nanodots.

Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.

Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.

Abstract: When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.

Abstract: A memory device including: a lower electrode; a ferroelectric layer formed above the lower electrode; a charge compensation layer formed above the ferroelectric layer and including an oxide having a composition differing from a composition of the ferroelectric layer; and upper electrodes formed above the charge compensation layer. The upper electrodes includes: a saturated polarization forming electrode used for forming a domain polarized to saturation in a predetermined direction in a predetermined region of the ferroelectric layer; a writing electrode disposed apart from the saturated polarization forming electrode; and a reading electrode disposed apart from the writing electrode.

Abstract: A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.

Abstract: A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected

Abstract: A nonvolatile semiconductor memory device obtained by combining a nonvolatile memory device with a SRAM is provided to improve operating speed and reliability. The nonvolatile semiconductor memory device includes a plurality of data registers. Preferably, each of the plurality of data registers includes a pull-up driving unit adapted and configured to pull up a storage node, a pull-down driving unit adapted and configured to pull down the storage node, a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line, and a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.

Abstract: An electric switch includes a ferroelectric substrate to which metal is added, a pair of electrodes provided on the ferroelectric substrate, and an electric field applying portion for changing the direction of polarization in part of the ferroelectric substrate.

Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

Abstract: An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

Abstract: A method for reading a nondestructive readout type ferroelectric memory device including a process in which 1-bit data is written in a pair of a cell for storage and a cell for reference disposed in series in the ferroelectric memory device, and a process in which a response obtained when a pulse is impressed to the 1-bit data written in the pair of a cell for storage and a cell for reference is resonated by a resonant circuit with a specified resonance frequency provided at a readout side to thereby output an output signal to be nondestructively readout.

Abstract: The present invention provides microelectronic electrochemical structures and related fabrication methods. A composite microelectronic structure is provided that includes first and second conductors dielectrically isolated from one another at a crossing thereof, the crossing surrounded by a dielectric material. A portion of the dielectric material around the crossing of the first and second conductors is removed to form a well that exposes respective outer surfaces of the first and second conductors and a molecule is deposited in the well such that the deposited molecule contacts the exposed outer surfaces of the first and second conductors.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential

Abstract: To provide a nondestructive-read ferroelectric memory capable of realizing high speed, high integration, and long service life. The present invention is provided with an MFSFET 100 having a ferroelectric thin film at its gate portion, word line 104, bit line 105, and bit line 106 so as to apply voltage equal to or higher than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first write timing and apply voltage equal to or higher than the coercive electric field between the bit line 106 and the word line 104 at second write timing, and applies voltage equal to or lower than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first read timing to detect the current flowing between the both bit lines, and applies voltage equal to or lower than the coercive electric field between the bit line 106 and the word line 104 at second read timing to detect the current flowing between the both bit lines.

Abstract: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.

Abstract: A ferroelectric memory device equipped with: a voltage source for generating a predetermined voltage; a first ferroelectric capacitor having one end electrically connected to a first bit line; a first resistance having a first resistance value, provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to a second bit line; a second resistance having a second resistance value different from the first resistance value, provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor by comparing a potential on the first bit line with a potential on the second bit line when the predetermined voltage is supplied to the first bit line and the second bit line.

Abstract: A ferroelectric memory device characterized in comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistance provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistance provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor based on a potential on the first bit line, according to a timing at which a potential on the second bit line changes when the predetermined voltage is supplied to the first bit line and the second bit line.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising: first and second memory units having bit lines, transistors for selection, sub-memory units composed of memory cells, and plate lines shared between the sub-memory units, wherein the first and second sub-memory units are formed on a same first insulating layer and another of the first and second sub-memory units are stacked over those units via a second insulating layer, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, in the first memory unit, a first common electrode is connected to the first bit line through one of said first transistors for selection, and the second electrode of each memory cell is individually connected to a shared plate line, in the second memory unit, a second common electrode is connected to the second bit line through one of said second transistors for selection, and the second electrode of each memory cell is individually connected to one of said shared plate lines, the first

Abstract: A ferroelectric memory device includes a plurality of memory cells, each memory cell includes a ferroelectric capacitor and a transistor, a plate line drive unit capable of providing a first voltage to the memory cell array in response to a plate line drive signal, and a reference voltage generating device. The reference voltage generating includes a reference cell block having a plurality of reference cells, each reference cell including a ferroelectric capacitor and a transistor, and a reference plate line drive to provide a reference plate line voltage to at least one reference cell in response to a plate line drive signal and a reference voltage generation signal, where each reference cell generates a reference voltage in response to the reference plate line voltage.

Abstract: An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

Abstract: A nonvolatile memory device features a serial diode cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a serial diode chain. The serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.

Abstract: The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (802). A short delay polarization value is obtained (804) by writing a data value, performing a short delay, and reading the data value. A long delay polarization value is obtained (806) by again writing the data value, performing a long delay, and again reading the data value. The short delay and long delay polarization values are compared (808) to obtain a data retention lifetime for the ferroelectric memory device. The obtained data retention lifetime is compared with acceptable values (810) and, if deemed unacceptable, avoids unnecessary performance of thermal bake data retention lifetime testing.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential

Abstract: A semiconductor memory device includes a first memory cell block that has one end connected to the first bit line and the other end connected to a common node, the first memory cell block including a plurality of series-connected unit cells, and a second memory cell block that has one end connected to the second bit line which is complementary to the first bit line and the other end connected to the common node, the second memory cell block including a plurality of series-connected unit cells. When data is restored in a selected unit cell, a potential corresponding to the first bit line is applied to one end of the selected unit cell and a complementary potential corresponding to the second bit line is applied to the other end of the selected unit cell via the common node.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.

Abstract: A memory array includes a memory layer that has hysteretic domains with domain axes extending between first and second memory layer surfaces. A conductive layer on the first memory layer surface has anisotropically increased electrical conductivity in a thickness direction. A movable conductive probe has a contact area on the conductive layer and moves to access a selected hysteretic domain.

Abstract: A data control device using a nonvolatile ferroelectric memory stores radio data having different types in a memory cell, thereby reducing a chip size. In the data control device, radio data such as image data, sound data and other data encoded as analog signals are stored in a unit cell including a nonvolatile ferroelectric capacitor. The analog data stored in a cell array block are converted into digital signals, and outputted, thereby reducing the configuration of adjacent systems and improving performance.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential

Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: Aspects of the invention can prevent delay in output timing of inverted data for each of ferroelectric capacitors, there can be provided NMOSs that can electrically connect upper electrodes of the ferroelectric capacitor with a plate line and electrically connect lower electrodes of the ferroelectric capacitor with bit lines. Further there can be provided NMOSs that can electrically connect the lower electrodes of the ferroelectric capacitor with the plate line, and electrically connect the upper electrodes of the ferroelectric capacitor with bit lines.

Abstract: A three dimensional monolithic memory comprising a memory cell allowing for increased density is disclosed. In the memory cell of the present invention, a bottom conductor preferably comprising tungsten is formed. Above the bottom conductor a semiconductor element preferably comprises two diode portions and an antifuse. Above the semiconductor element are additional conductors and semiconductor elements in multiple stones of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential

Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

Abstract: Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surface of the first insulation film and splashed away due to centrifugal force. Due to this, a first conductive film to being formed has an increased film thickness at portion of the hollow where the precursor solution is ready to correct, or portion to be formed into a lower electrode, and a decreased film thickness at portion other than the hollow. Accordingly, it is satisfactory to etch only the hollow portion when forming a lower electrode by dry-etching the first conductive film.

Abstract: A ferroelectric memory includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.

Abstract: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.

Abstract: A first fraction of a programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to other word lines coupled to control gates of non-selected memory cells. The first fraction of the programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells. A second fraction of the programming voltage is applied to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells.

Abstract: There is provided a magnetic memory including first and second wirings intersecting each other and disposed apart from each other, a magnetoresistance effect film positioned between the first and second wirings, and a first magnetic film including a first portion facing the magnetoresistance effect film with the first wiring interposed therebetween and a pair of second portions positioned on both sides of the first wiring and magnetically connected to the first portion, each of the first and second portions having either one of a high saturation magnetization soft magnetic material containing cobalt and a metal-nonmetal nano-granular film.

Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.

Abstract: An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a reduction in the number of metal layers, cost, and the chip size and an increase of production yields and product reliability. A memory cell 12 including a metal line 16 crossing a bit line 14 without contact therewith and a second conductive structure 24 connecting the metal line 16 and a switching element 20 is disclosed. A write driver circuit 26 for driving a write current through the metal line 16 and a ground 28 are connected to the metal line 16 through a switch 30 for selecting the circuit 26 or the ground 28.

Abstract: A ferroelectric memory device capable of structurally reducing data deterioration. In this ferroelectric memory device, bitlines are hierarchized, and sub-bitlines subordinate to the bitlines through sub-bitline select switches are provided in each of a plurality of block regions. The block regions are sequentially selected along an increment direction, and wordlines in each block are sequentially selected along the increment direction from the lowest wordline to the highest wordline. The number “n” of wordlines arranged in each block region is set equal to or less than a predetermined limit number about relaxation.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: In an FET having an MFMIS structure in which a floating gate, a ferroelectric layer and a control gate are sequentially provided through a gate insulating film on the surface of a source—drain region formed on the surface of a semiconductor substrate, the ferroelectric layer is constituted by an inorganic film having a vacancy rate of 50% or more.

Abstract: A test circuit is integrated in a ferroelectric memory component in order to make analog measurements of bit line signals of ferroelectric memory cells. The test circuit, when in a test mode, reads out analog signal values for the respective memory content of the cells and feds the analog signal values to a downstream evaluation device. The test circuit is integrated as an analog circuit in the ferroelectric memory component and, in the test mode with non-activated or disconnected sense amplifiers, is configured to output analog bit line signals from the memory component to a point outside the memory component.