Information Masking Patents (Class 365/120)
  • Patent number: 10261410
    Abstract: The present invention discloses an OPC method for a pattern corner, comprising the following steps of: S01: providing a photomask which has an original layout containing target patterns, wherein the target patterns have at least one convex corner at a vertex of two first adjacent sides with an angle of 90-degree therebetween and at least one concave corner at a vertex of two second adjacent sides with an angle of 270-degree; S02: modifying the original layout to obtain a modified layout by adding at least one first rectangular correction pattern from outside of the convex corner and/or removing at least one second rectangular correction pattern from inside of the concave corner; S03: performing a model-based OPC correction to the modified layout to obtain a corrected photomask.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 16, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Yueyu Zhang, Yue Wang
  • Patent number: 10210315
    Abstract: A method, computer program product, and computer system for managing and tracking commands associated with a change on a managed computer system. The managed computer system receives a log-on of an administrator onto the managed computer system, determines the lockdown level of the managed computer system by querying a managing computer system, and retrieves a list of authorized commands under the lockdown level from the managing computer system. The managed computer system determines, by querying the managing computer system, whether an authorized change on the managed computer system exists. The managed computer system removes the lockdown level to receive from the managing computer system authorization of commands that have been locked down, in response to determining that the authorized change exists. The managed computer system sets the lockdown level with the authorized commands on the managed computer system, in response to determining that the authorized change does not exist.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric Anderson, Christopher J. Dawson, Leslie A. Nelson, Brett W. Singletary
  • Patent number: 10182072
    Abstract: There is described an RF communication device, the device comprising (a) a data memory for storing data, (b) an RF interface (112) for RF communication with an external RF device (130), (c) a host interface (111) for communication with a host device (120), (d) a host access memory unit (214, 215) comprising host interface access control data, the host interface access control data defining host access rules for accessing data in the data memory through the host interface (111), and (e) a host access control unit for, based on the host interface access control data, controlling access to data in the data memory through the host interface (111). There is also described a system and a method.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 15, 2019
    Assignee: NXP B.V.
    Inventors: Sreedhar Patange, Nitin Labdhe, Martin Liebl
  • Patent number: 10019406
    Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt, Helena Deirdre O'Shea, ZhenQi Chen, Wolfgang Roethig
  • Patent number: 9858989
    Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A static random access memory (SRAM) array is configured to receive each of the plurality of serialized input signals. The SRAM array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Cheng Chen, Jack Liu
  • Patent number: 9792965
    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 17, 2017
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Frederick A. Ware, William N. Ng
  • Patent number: 9632266
    Abstract: The present disclosure includes an optical fiber ribbon, using polymer optical fibers and an extremely thin adhesive coating to provide adhesion between the fibers. The external surfaces of the optical fiber ribbons are precisely placed with respect to the optical cores of the constituent fibers, and the optical cores of the fibers are precisely placed with respect to each other. Therefore, the external surface of the ribbon is used as a reference surface for aligning the array of optical fiber cores to arrays of optical emitters or detectors at the ends of the ribbon. Thus, the optical fiber ribbon of the present disclosure is cut, either by a sharp blade or other tool as suitable to expose a cross-section of the ribbon, and inserted as a single unit into a receptacle that aligns the outer surface of the ribbon with respect to the array of optical emitters or detectors.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 25, 2017
    Assignee: CHROMIS FIBEROPTICS, INC.
    Inventor: Whitney R. White
  • Patent number: 9575835
    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 21, 2017
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Suresh N. Rajan, Ian P. Shaeffer, Frederick A. Ware, Wayne F. Ellis
  • Patent number: 9384825
    Abstract: A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jentsung Lin, Paul Bassett, Suresh Venkumahanti
  • Patent number: 9236382
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: January 12, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9200271
    Abstract: Methods, systems, and articles for selective three dimensional (3D) biopatterning are disclosed. A biological target may be imaged and a selected area of the image may define a desired pattern for guiding the emission of EM radiation into the biological target. Two or more groups of photosensitive elements responsive to different activation wavelengths may be provided. The photosensitive elements may be selectively activated on or within the biological target based on location and activation wavelength in order to guide cell differentiation, adhesion of growth factors to a scaffold, release of growth factors, and/or deletion of cells.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: December 1, 2015
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 8982682
    Abstract: An information storage device has small compartments for storing information in a solid body and can be used as a memory medium. The solid body can have at least one pair of parallel planar portions on its surface. The information is divided into bits and stored in discrete minute areas that are distributed three-dimensionally inside the memory medium. The data can be converted into a digital format for storage to regulate the number of ‘1s’ recorded in a direction of the memory medium.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takao Watanabe, Toshimichi Shintani
  • Patent number: 8958226
    Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
  • Patent number: 8804391
    Abstract: A semiconductor memory device includes memory blocks that each include memory cells coupled to bit lines, a column masking circuit configured to output data change signals in response to an address signal indicating bit lines of selected columns among a plurality of columns, and an operation circuit configured to store data of the memory cells transferred through the bit lines and simultaneously change data transferred through the bit lines of the selected columns into operation pass data in response to the data change signals.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung Hoon Ahn
  • Patent number: 8689279
    Abstract: To comply with a policy for a computing device indicating that data written by the computing device to the storage volume after activation of the policy be encrypted, an encrypted chunks map is accessed. The encrypted chunks map identifies whether, for each chunk of sectors of a storage volume, the sectors in the chunk are unencrypted. In response to a request to write content to a sector, the encrypted chunks map is checked to determine whether a chunk that includes the sector is unencrypted. If the chunk that includes the sector is unencrypted, then the sectors in the chunk are encrypted, and the content is encrypted and written to the sector. If the chunk that includes the sector is encrypted or not in use, then the content is encrypted and written to the sector.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 1, 2014
    Assignee: Microsoft Corporation
    Inventors: Innokentiy Basmov, Alex M. Semenko, Dustin L. Green, Magnus Bo Gustaf Nyström
  • Patent number: 8391086
    Abstract: Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Giulio Martinozzi, Mauro Pagliato
  • Patent number: 8347047
    Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: January 1, 2013
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Frederick A. Ware
  • Patent number: 8307270
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
  • Patent number: 8059477
    Abstract: A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Sic Yoon
  • Patent number: 8040712
    Abstract: An information memory device using an electromagnetic-wave resonance phenomenon is provided to achieve both high density and long-period storage of stored data. Memory cells are three-dimensionally arranged in the inside of a solid-like medium which is not contacted with a surface of the medium, and the memory cell has resonance characteristics to electromagnetic waves depending on the space coordinates of the memory cell. For the medium, a material is selected so that an electromagnetic wave having the resonance frequency of the memory cell. By observing absorption spectra of the irradiated electromagnetic wave or emission spectra after the absorption, three-dimensional space coordinates of the memory cell are calculated.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 18, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takao Watanabe, Toshimichi Shintani, Takeshi Maeda, Akemi Hirotsune, Yoshitaka Bito
  • Patent number: 7688649
    Abstract: A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: March 30, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Noriyoshi Sato, Nobutaka Nasu, Tetsuya Tanabe
  • Patent number: 7684258
    Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: March 23, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tatsuya Kanda, Kotoku Sato
  • Patent number: 7609583
    Abstract: Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: October 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Booth, Tyler J. Gomm
  • Publication number: 20090116276
    Abstract: A memory device of the present invention is characterized by a memory device for storing information by making use of molecular alignment of a liquid crystal compound in a liquid crystalline state formed by spot irradiation with a laser beam to carry out a selective heat treatment on an electroconductive liquid crystal semiconductor material layer containing a liquid crystal compound, comprising: a first electrode group including a plurality of linear electrodes which are parallel to each other; an electroconductive liquid crystal semiconductor material layer formed in such a manner that the layer covers the first electrode group, the layer containing a liquid crystal compound having a long linear conjugate structural moiety and exhibiting a smectic phase as a liquid crystal phase; and a second electrode group formed on the electroconductive liquid crystal semiconductor material layer and including a plurality of linear transparent electrodes being parallel to each other and extend in a direction intersecting
    Type: Application
    Filed: May 18, 2007
    Publication date: May 7, 2009
    Applicants: YAMANASHI UNIVERSITY, NIPPON CHEMICAL INDUSTRIAL CO., LTD.
    Inventors: Yuichiro Haramoto, Takamasa Kato, Kohki Hiroshima
  • Patent number: 7474556
    Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of local word lines and adapted to adjusting voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information. The plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver. The first section word line drivers include pull-down devices while not including pull-up devices.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-gil Choi, Chang-soo Lee, Bo-tak Lim
  • Patent number: 7426028
    Abstract: Optical breakdown by predetermined laser pulses in transparent dielectrics produces an ionized region of dense plasma confined within the bulk of the material. Such an ionized region is responsible for broadband radiation that accompanies a desired breakdown process. Spectroscopic monitoring of the accompanying light in real-time is utilized to ascertain the morphology of the radiated interaction volume. Such a method and apparatus as presented herein, provides commercial realization of rapid prototyping of optoelectronic devices, optical three-dimensional data storage devices, and waveguide writing.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: September 16, 2008
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Christopher W. Carr, Stavros Demos, Michael D. Feit, Alexander M. Rubenchik
  • Patent number: 7287103
    Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Paul Allen Ganfield, Kent Harold Haselhorst, Charles Ray Johns, Peichun Peter Liu
  • Patent number: 7212426
    Abstract: A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 1, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Gun Park, Jin-Yub Lee
  • Patent number: 7203107
    Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: April 10, 2007
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 7171528
    Abstract: A method and apparatus provides a mask key that is used instead of mask data. In an embodiment of the present invention, a write mask key is generated by a memory controller and transferred to a memory device that uses the write mask key to determine whether to write a data value to a storage array. A plurality of decoders, an OR logic gate tree and a binary propagation tree is used to provide the write mask key that reduces latency while using the approximate same circuit area and allows for the use of standard software tools in an embodiment of the present invention. A plurality of log2 decoders is coupled to a plurality of OR logic gates in the OR logic gate tree.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: January 30, 2007
    Assignee: Rambus Inc.
    Inventors: Marc Evans, Richard E. Perego, Frederick A. Ware
  • Patent number: 7020003
    Abstract: A device for compensating a semiconductor memory defect suitable for a semiconductor memory is provided. The device comprises: a memory array, the memory array having a memory region consisting of a plurality of memory cells, the memory array being coupled to the address decoder circuit and the sensing circuit for storing data, if the memory array has a defect, the memory array is divided into a plurality of sub-memory regions, wherein one of the plurality of sub-memory regions is defectless, the memory array is replaced by the defectless sub-memory regions for storing data. A selection circuit coupled to the control unit, selects one of the memory region and the defectless sub-memory region to store data. A first input address buffer coupled to the control unit and the address decoder circuit has an address input port and an address output port.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: March 28, 2006
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 6940801
    Abstract: An optical recording medium, an optical recording and reproducing method, and an apparatus that can record and reproduce multilevel information at a high density and with a high S/N ratio. Recording light emitted from a light source is collimated by a collimation lens and introduced into a polarization rotary device. Recording light transmitted by the polarization rotary device is focused by an objective lens onto an optical recording medium. In response, a photo-induced birefringence is recorded on the optical recording medium. Multilevel recording is performed by controlling a voltage applied to the polarization rotary device to change a polarization angle ? of recording light. Reproduction is performed by detecting light reflected from the optical recording medium with an analyzer and a detector.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: September 6, 2005
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Tsutomu Ishii, Katsunori Kawano, Kazuo Baba, Kiichi Ueyanagi
  • Patent number: 6912148
    Abstract: A system for writing data to and reading data from a magnetic semiconductor memory utilizing a spin polarized electron beam. The magnetic semiconductor memory comprises a plurality of storage locations, each storage location includes a magnetic material and a layer of semiconductor material capable of emitting photons. The method of reading data from the magnetic semiconductor memory comprising steps of directing a spin-polarized electron beam at the magnetic semiconductor memory, and detecting the light emission state of the semiconductor layer from the magnetic semiconductor memory.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Eric C. Hannah, Michael A. Brown
  • Patent number: 6850092
    Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: February 1, 2005
    Assignee: The Trustees of Columbia University
    Inventors: Tiberiu Chelcea, Steven M. Nowick
  • Publication number: 20040246759
    Abstract: A nonvolatile memory device includes a memory cell array, a control circuit, a voltage boost circuit, a timer circuit, a discharge circuit and a sensor circuit. The control circuit generates an erase execution (EE) signal in response to an erase command (EC) signal, stops the EE signal and generates a discharge control (DC) signal in response to an erase termination (ET) signal, stops the DC signal in response to a discharge termination (DT) signal, and stops the EE signal and the DC signal in response to a reset signal. The boost circuit provides high voltage in response to the EE signal. The timer circuit generates the ET signal after receiving the EE signal. The discharge circuit discharges the high voltage and the sensor is enabled in response to the DC signal or the reset signal. The sensor generates the DT signal when the high voltage drops to a predetermined voltage.
    Type: Application
    Filed: June 3, 2004
    Publication date: December 9, 2004
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Miyazaki
  • Patent number: 6826663
    Abstract: A memory system having a memory controller and a memory device coupled to the memory controller. The memory controller outputs a write data value to the memory device. The memory device receives the write data value from the memory controller, and compares the write data value with a mask key value. If the write data value matches the mask key value, the memory device does not store the write data value. If the write data value does not match the mask key value, the memory device stores the write data value.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: November 30, 2004
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Fredrick A. Ware
  • Patent number: 6798959
    Abstract: A display device comprises an actuator substrate which has actuator elements, an optical waveguide plate, crosspieces which is interposed between the optical waveguide plate and the actuator substrate and which surround the actuator elements, and picture element assemblies which are joined onto the actuator elements. A stack for constructing each of the picture element assemblies has a transparent layer opposed to the optical waveguide plate. The transparent layer contains a major component of a cured resin obtained by polymerization with a principal ingredient which is composed of one or more materials selected from modified epoxy, bisphenol A type epoxy, bisphenol F type epoxy, and glycidyl ether type epoxy, and a curing agent which is composed of one or more materials selected from modified polyamine, modified alicyclic polyamine, and heterocyclic diamine modified product of tertiary amine.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: September 28, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Yukihisa Takeuchi, Tsutomu Nanataki, Natsumi Shimogawa, Kazuhiro Yamamoto
  • Patent number: 6770524
    Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: Chien Chiang, Guy C. Wicker
  • Patent number: 6668302
    Abstract: The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: December 23, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: J. Ken Fox
  • Patent number: 6643194
    Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., x16 or x32.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: November 4, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Ryan, Christopher K. Morzano, Wen Li
  • Publication number: 20030196026
    Abstract: An embodiment of the invention provides a circuit and method for optimizing an index hashing function in a cache memory on a microprocessor. A programmable index hashing function is designed that allows the index hashing function to be programmed after the microprocessor has been fabricated. The index hashing function may be “tuned” by running an application on the microprocessor and observing the performance of the cache memory based on the type of index hashing function used. The index hashing function may be programmed by several methods.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 16, 2003
    Inventor: Paul J. Moyer
  • Patent number: 6528234
    Abstract: High density, photon-gated persistent spectral holeburning is effectuated in rare earth doped II-VI compounds such as MgS, CaS, BaS and SrS. Two-photon ionization of rare earth ions is performed, selected by a narrow band laser, producing narrow regions of reduced absorption (optical holes) in the absorption spectrum of a rare earth ion. These holes are useful for such applications as high density memory (especially, high density re-writable or photo-erasable memory), spectral holographic memory, communication, etc., no and demonstrate great survivability over reading cycles, thermal cycles and elevated temperatures. The embedment of the rare earth doped II-VI compound in a matrix comprising a polymeric material (such as PMMA), prior to the effectuation of the holeburning, may be advantageous for many embodiments. Inventive practice has successfully burned two hundred forty photon gated spectral holes in the zero phonon line (ZPL) of the 4f-5d transition of Eu2+ in a magnesium sulfide host.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: March 4, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Veerendra Kumar Mathur, Zameer Ul Hasan
  • Publication number: 20020122900
    Abstract: An organic electroluminescent device capable of blue emission with a high color purity, and a display unit capable of full-color display with high color expressivity by using the organic electroluminescent device are provided. The organic electroluminescent device includes at least a hole transportation layer and a luminescent layer held between a lower electrode to become an anode and an upper electrode to become a cathode in a state of lamination in that order from the anode side. The luminescent layer is made of a spiro compound, and the hole transportation layer is made of triphenylamine tetramer. Furthermore, the display unit includes organic electroluminescent devices as blue-emitting elements arrayed for a plurality of pixels.
    Type: Application
    Filed: February 6, 2002
    Publication date: September 5, 2002
    Inventors: Naoyuki Ueda, Ichinori Takada, Tetsuo Shibanuma, Mari Ichimura, Shinichiro Tamura
  • Publication number: 20020067634
    Abstract: An ultra-high-density data storage device including at least one energy-channeling component and a storage medium that usually includes at least one rectifying junction region. The energy-channeling component is generally capable of emitting such energies as, but not limited to, thermal, optical and electronic energy. The energy-channeling component is generally located either within close proximity of or in direct contact with the storage medium. The storage medium typically includes nanometer-scaled storage areas.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 6, 2002
    Inventor: Gary A. Gibson
  • Publication number: 20020027795
    Abstract: A semiconductor memory device includes a sense amplifier provided for the bit lines. To the sense amplifier, an internal power supply voltage and a negative voltage or a ground voltage are supplied. In the normal operation mode, first and second transistors are turned on, and the bit line is amplified to the internal power supply voltage or the ground voltage. In the test mode, first and third transistors turn on, and the bit line is amplified to the power supply voltage or the negative voltage. Thus, potential difference between adjacent storage nodes is increased.
    Type: Application
    Filed: February 2, 2001
    Publication date: March 7, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shunsuke Endo
  • Patent number: 6345009
    Abstract: A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: February 5, 2002
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel, Thomas J. Holman, Andrew V. Anderson
  • Publication number: 20010017787
    Abstract: A semiconductor memory device of a dynamic type having an interface of a static-type semiconductor memory device includes a memory cell array, and a control circuit controlling a read operation to be initiated in response to a predetermined signal externally applied thereto before a read or write command is externally applied to the control circuit.
    Type: Application
    Filed: February 27, 2001
    Publication date: August 30, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Hitoshi Ikeda
  • Publication number: 20010017786
    Abstract: An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 30, 2001
    Applicant: Lucent Technologies Inc.
    Inventor: Ted Kirk Woodward
  • Patent number: 6280904
    Abstract: The present invention relates to the field of optical recording materials, in particular, fluorescent compounds and matrices suitable for use in optical memory systems, including three dimensional optical memory systems for READ ONLY MEMORY (ROM). In particular, nonfluorescent Rhodamine B lactams are photochemically transformed into fluorescent Rhodamine B derivatives.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: August 28, 2001
    Assignee: Tridstore IP, LLC
    Inventors: Natalia T. Sokoluk, Vladimir V. Shubin, Eugene B. Levich, Jacob N. Malkin
  • Publication number: 20010014032
    Abstract: A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.
    Type: Application
    Filed: February 8, 2001
    Publication date: August 16, 2001
    Inventors: Tetsuhito Nakamura, Naonobu Sukegawa, Tsuguo Matsuura, Masanao Ito