Three-dimensional Magnetic Array Patents (Class 365/130)
  • Patent number: 10797227
    Abstract: A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a negative-magnetic-anisotropy assist layer having negative magnetic anisotropy that provides an in-plane magnetization within a plane that is perpendicular to the fixed magnetization direction, and a first nonmagnetic spacer layer located between the free layer and the negative-magnetic-anisotropy assist layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Quang Le, Zhanjie Li, Zhigang Bai, Paul Vanderheijden, Michael Ho
  • Patent number: 10546868
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, first memory portions, and second memory portions. The stacked body includes conductive layers. The conductive layers are arranged in a first direction and extend in a second direction. The stacked body includes first and second regions. The second region is arranged with the first region in the second direction. The first memory portions extend in the first direction through the first region and are arranged at a first pitch along the second direction. The second memory portions extend in the first direction through the second region and are arranged at the first pitch along the second direction. A distance between a first center of one of the first memory portions and a second center of one of the second memory portions is longer than the first pitch and shorter than 2 times the first pitch.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shigeru Kinoshita
  • Patent number: 10529385
    Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 7, 2020
    Assignee: ULTRAMEMORY INC.
    Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
  • Patent number: 10497437
    Abstract: An integrated circuit includes a three-dimensional cross point memory array having M levels of memory cells disposed in cross points of N first access line layers and P second access line layers. The integrated circuit further comprises first and second sets of first access line drivers. The first set of first access line drivers is operatively coupled to apply a common first operational voltage to selected first access lines in odd first access line layers. The second set of first access line drivers is operatively coupled to apply the common first operational voltage to selected first access lines in even first access layers. A plurality of sets of second access line drivers is operatively configured to apply a second operational voltage to selected second access lines in selected second access line layers.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsin-Yi Ho, Hsiang-Lan Lung
  • Patent number: 10388697
    Abstract: A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 20, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Zhuofan Chen, Yibin Song, Haiyang Zhang
  • Patent number: 10347308
    Abstract: A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 9, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Mourad El Baraji, Eric Michael Ryan
  • Patent number: 10304495
    Abstract: In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 28, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10296824
    Abstract: Fabrication methods of forming memory subsystem of CNN based digital IC for AI are disclosed. The method in SLC technology includes: providing a metal layer, forming a via layer, forming a HSL, forming a MTJ element layer and then etching out unmasked portions of the MTJ element layer to form at least two groups of different sized MTJ elements. The method in MLC technology includes: providing a metal layer, forming a via layer, forming a first HSL, forming a first MTJ element layer, etching out unmasked portions of the first MTJ element layer to form lower MTJ elements, forming a second HSL, forming a second MTJ element layer and etching out unmasked portions of the second MTJ element layer to form upper MTJ elements. Same sized first MTJ element layer and the second HSL are formed together.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 21, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong
  • Patent number: 10236439
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a diameter that is different from a diameter of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10210917
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 19, 2019
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 10211258
    Abstract: Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 19, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10141499
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a central axis that is offset from a central axis of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted. The off-center design may be used to adjust the location of the stray-field injection in the free layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 27, 2018
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10014045
    Abstract: Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. The data storage layers are each formed from a multi-layer structure. At ambient temperatures, the multi-layer structures exhibit an antiparallel coupling state with a near zero net magnetic moment. At higher transition temperatures, the multi-layer structures transition from the antiparallel coupling state to a parallel coupling state with a net magnetic moment. At yet higher temperatures, the multi-layer structure transitions from the antiparallel coupling state to a receiving state where the coercivity of the multi-layer structures drops below a particular level so that magnetic fields from write elements or neighboring data storage layers may imprint data into the data storage layer.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 3, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Olav Hellwig, Bruce D. Terris, Jan-Ulrich Thiele
  • Patent number: 10014057
    Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9953690
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Patent number: 9785615
    Abstract: Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular to a number of row lines, a memory element located at each intersection of a row line and a column line. A programming voltage is applied at each memory element to change a resistance value to represent a respective entry in a skew symmetric matrix representing a first vector, and an input voltage is applied along each row line to represent a dimensional component of a second vector. Sensors located at each column line measure output voltages along column lines, where the output voltages are generated by applying input voltages received by memory elements located along the row line to resistance values of the respective memory elements. Differential amplifiers collate the output voltages for pairs of sensors to generate dimensional components of the cross product.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 10, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Emmanuelle J. Merced Grafals, Noraica Davila Melendez, John Paul Strachan
  • Patent number: 9740418
    Abstract: A storage unit includes a U-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port. The U-shaped magnetic track includes a first port, a second port, a first storage area, and a second storage area. By controlling input voltages of the first port, the second port, the first drive port, and the second drive port and driving the first drive circuit, a current pulse is generated in the first storage area, and a magnetic domain wall in the first storage area is driven to move. By controlling the input voltages of the first port, the second port, the first drive port, and the second drive port and driving the second drive circuit, a current pulse is generated in the second storage area, and a magnetic domain in the second storage area is driven to move.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: August 22, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yinyin Lin, Zhulin Wei, Junfeng Zhao, Wei Yang, Yarong Fu, Kai Yang
  • Patent number: 9734880
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Patent number: 9735203
    Abstract: Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: August 15, 2017
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Cheol Seong Hwang, Jun Yeong Seok
  • Patent number: 9729106
    Abstract: A spin torque oscillator and a method of making same. The spin torque oscillator is configured to generate microwave electrical oscillations without the use of a magnetic field external thereto, the spin torque oscillator having one of a plurality of input nanopillars and a nanopillar having a plurality of free FM layers.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, George I. Bourianoff
  • Patent number: 9721631
    Abstract: A magnetic device that includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque and an in-plane magnetized free layer having a magnetization vector having at least a first stable state and a second stable state. The magnetic device also includes a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque can combine. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. An application of a voltage pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device causes the magnetization vector to oscillate between the first stable state and the second stable state for a portion of the duration regardless of an initial state of the magnetization vector.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 1, 2017
    Assignee: NEW YORK UNIVERSITY
    Inventors: Andrew Kent, Huanlong Liu
  • Patent number: 9698223
    Abstract: A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, George Matamis
  • Patent number: 9478279
    Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 25, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 9478741
    Abstract: A resistive random access memory (RRAM) including a substrate, a dielectric layer, memory cells and an interconnect structure is provided. The dielectric layer is disposed on the substrate. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first electrode, a second electrode and a variable resistance structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode. In two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other. The interconnect structure is disposed in the dielectric layer and connects the first electrodes of the memory cells.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 25, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Mao-Teng Hsu
  • Patent number: 9466790
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 11, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: George Samachisa
  • Patent number: 9450023
    Abstract: A three-dimensional (3D) non-volatile memory array is provided having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line. Methods of fabricating arrays including recessed memory cell areas are provided.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: September 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Konevecki, Vance Dunton, Steve Radigan
  • Patent number: 9430340
    Abstract: A verification control part has the same write information data piece written into each of a plurality of memories according to a write instruction and then reads out information data piece from the plurality of memories. At this time, a coincidence determining part performs first verification to determine whether respective read-out information data pieces read out from the memories coincide with each other and outputs a verification result signal to the outside, and simultaneously the verification control part outputs one of the read-out information data pieces as an information data piece for second verification, which performs coincidence determination with the write information data piece, to the outside.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 30, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takeshi Ichikawa
  • Patent number: 9418761
    Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Umut Arslan, Cyrille Dray
  • Patent number: 9419058
    Abstract: A memory device, such as a ReRAM device includes plural interdigitated word lines and a single select transistor controlling plural vertical local bit lines. The interdigitated word lines may be word line combs containing word line fingers which are electrically connected using contact pads and a sidewall bridge interconnect. The select transistor may be a vertical TFT or a planar field effect transistor.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: August 16, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seje Takaki, Yoshihiro Sato
  • Patent number: 9368625
    Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 14, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 9349941
    Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state. The magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs) with each MTJ including a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a barrier layer, and a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof. Each MTJ is separated from other MTJs in the stack by at least an isolation layer. The stack of MTJs may store more than one bit of information. The free layer of each MTJ has a switching current threshold different from free layers of other MTJs in the stack.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 24, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 9337413
    Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element that includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer. The stack is for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 10, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 9318703
    Abstract: A resistive random access memory (RRAM) including a substrate, a dielectric layer, memory cells and an interconnect structure is provided. The dielectric layer is disposed on the substrate. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first electrode, a second electrode and a variable resistance structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode. In two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other. The interconnect structure is disposed in the dielectric layer and connects the first electrodes of the memory cells.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 19, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Mao-Teng Hsu
  • Patent number: 9312474
    Abstract: Disclosed are electronic devices comprising a semiconductor memory unit capable of reducing the switching current of a variable resistance element for switching between different resistance states. One implementation of a disclosed electronic device may include a first magnetic layer having an easy magnetization axis in a first direction and having a variable magnetization direction, a third magnetic layer having a magnetization direction pinned in the first direction, a second magnetic layer interposed between the first magnetic layer and the third magnetic layer, and having a magnetization direction pinned in a second direction different from the first direction, a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and a non-magnetic layer interposed between the second magnetic layer and the third magnetic layer.
    Type: Grant
    Filed: December 29, 2013
    Date of Patent: April 12, 2016
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Ki-Seon Park
  • Patent number: 9236106
    Abstract: A magnetic domain wall motion memory according to an embodiment includes: a magnetic memory nanowire; a write magnetic wire intersecting with the magnetic memory nanowire; an intermediate joining portion provided in an intersection region between the write magnetic wire and the magnetic memory nanowire; adjacent pinning portions placed on one of the same side and the opposite side of the write magnetic wire as and from the magnetic memory nanowire; a read unit attached to the magnetic memory nanowire; a pair of first electrodes that applies a write current to the write magnetic wire; and a pair of second electrodes that applies a current for causing the magnetic memory nanowire to move a magnetic domain wall, wherein contact faces of the write magnetic wire in contact with the adjacent pinning portions have magnetization configurations antiparallel to each other.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shiho Nakamura
  • Patent number: 9218866
    Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: December 22, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 9147468
    Abstract: A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 9111855
    Abstract: A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 18, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 9036406
    Abstract: A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jin Kim, Sang-Kyu Kang, Dong-Hyun Sohn, Dong-Min Kim, Kyu-Chan Lee
  • Patent number: 9030859
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: May 12, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Raul-Adrian Cernea
  • Patent number: 9007821
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Inaba
  • Patent number: 8988936
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Grant
    Filed: October 4, 2014
    Date of Patent: March 24, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
  • Patent number: 8971091
    Abstract: A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Yi, Muhammad Shakeel Qureshi, Frederick Perner, Richard Carter
  • Patent number: 8934295
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Grant
    Filed: October 4, 2014
    Date of Patent: January 13, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
  • Patent number: 8929126
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Unity Semiconductor Corporation
    Inventor: Chang Hua Siau
  • Patent number: 8923038
    Abstract: Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Witold Kula, Gurtej S. Sandhu, Stephen J. Kramer
  • Patent number: 8917531
    Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, John K. DeBrosse
  • Patent number: 8897064
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 25, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorta
  • Patent number: 8885400
    Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: November 11, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
  • Patent number: 8879310
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Inaba