Abstract: A “toggling” type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a plurality of toggle memory cells stacked along the Z axis. Each memory stack is located at an intersection region between two orthogonal write lines. Each cell in the stack is a “toggle” cell that has its synthetic antiferromagnet (SAF) free layer easy axis of magnetization aligned nonparallel with the X and Y axes and angularly spaced about the Z axis from the easy axes of magnetization of all the other SAF free layers in the stack. Each cell in a stack is magnetically separated from adjacent cells in the stack by a nonmagnetic separation layer. The magnetization direction of the free layer in a selected memory cell in a stack can be switched without switching the magnetization directions of the free layers in the other memory cells in the stack.

Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: A “toggling” type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a plurality of toggle memory cells stacked along the Z axis. Each memory stack is located at an intersection region between two orthogonal write lines. Each cell in the stack is a “toggle” cell that has its synthetic antiferromagnet (SAF) free layer easy axis of magnetization aligned nonparallel with the X and Y axes and angularly spaced about the Z axis from the easy axes of magnetization of all the other SAF free layers in the stack. Each cell in a stack is magnetically separated from adjacent cells in the stack by a nonmagnetic separation layer. The magnetization direction of the free layer in a selected memory cell in a stack can be switched without switching the magnetization directions of the free layers in the other memory cells in the stack.

Abstract: A ferroelectric or electret volumetric memory device with a memory material provided in sandwich between first and second electrode layers with stripe-like electrodes forming word lines and bit lines of a matrix-addressable memory array, memory cells are defined in volumes of memeory material in between two crossing word lines and bit lines and a plurality of memory arrays are provided in a stacked arrangement. A stack of memory arrays is formed by tow or more ribbon-like structures, which are folded and/or braided into each other. Each ribbon-like structure includes a flexible substrate of non-conducting material and the electrode layers respectively provided on each surface of the substrate and including the parallel strip-like electrodes extending along the ribbon-like structure.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.

Abstract: A memory device includes an array of memory elements overlying a plurality of driver cells. Vias through an insulating layer connect the driver cells to the memory elements. The vias are distributed over the area of the array to connect the individual driver cells to the respective row and and/or column conductors of the memory array.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 1020 atoms cm−3 or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

Abstract: A one-dimensional data stream is encoded into a two-dimensional data array with reduced high frequency components, for recording on a two-dimensional recording device, such as a holographic storage device. A two-dimensional data array read from the two-dimensional recording device is decoded into the original one-dimensional data stream. To encode, a one-dimensional data stream is partitioned into a plurality of chunks of data. Each chunk of data is partitioned into a plurality of groups of bits. Each group of bits is encoded into a two dimensional data array according to a predefined constraint. A plurality of two-dimensional data arrays are concatenated into a data strip. A plurality of data strips are then assembled into a complete two-dimensional data block. To decode, a two-dimensional data stream is partitioned into multiple small two-dimensional arrays. Each array is decoded into a multi-bit group. In one embodiment, this decoding is a function of other nearby groups.

Abstract: Strips of fabric material are attached along the edges of an array of magnetic cores on a substrate with the strips having an upstanding ridge aligned parallel to the edges of the array. The material of the fabric serves as a guide for threading wires through the cores, and also serves as an attachment support for the wires to keep them from lifting free from the support after being inserted through the cores. The guide/supports are relatively simple, strong, durable, resistant to deterioration, and provide an inexpensive guide and support for the wires of the core memory.

Abstract: Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

Abstract: A small, very low cost, wide margin core memory couples a return current drive scheme with a crossover-free sense winding extending parallel to the Y drive conductors to eliminate the assembly time and wasted substrate space associated with sense winding crossovers. The return currents generate small noise signals which cancel with partial select noise signals to provide noise signals comparable to a 3 wire, 3D bow tie sense winding.

Abstract: A highly efficient core memory drive system passes currents down a selected X and Y conductor and divides the currents for return through the unselected drive wires in the same X or Y dimension. The drive conductors are coupled to drive and sink switches at a drive end and the X conductors are connected together at an opposite common end and the Y conductors are connected together at an opposite common end. Resistors provide a current path between the drive end of each X conductor and an X resistor bus and between the drive end of each Y conductor and a Y resistor bus. A pair of switching transistors including a sink transistor and a drive transistor is connected to a drive end of each conductor to generate a drive current therein. The drive current divides equally among the unselected conductors at the common end to return through the unselected conductors and through the resistors to the resistor bus.

Abstract: A core memory utilizes an auxiliary core that is driven concurrently with selected data cores to increase tolerances by automatically tracking the peaking time and the output magnitude. Wide variations in both the magnitude and duration of core output switching signals are compensated by use of the auxiliary core to control the sensing strobe time during a read part cycle and drive current duration during both read and write part cycles. Subtracting half of the auxiliary core output switching signal from a selected data core output switching signal normalizes the difference about zero volts with a one being indicated by the presence of a positive voltage and a zero by a negative voltage. With the reference threshold at zero there is no precise adjustment. Since the peak of the auxiliary core output tracks the peak of the selected data core output, substantial changes in the peaking and switching times do not interfere with accurate determinations of data core data states.

Abstract: Organizations are disclosed for driving bit lines of a two-line 21/2D coincident current magnetic core memory in which a bit line not used for reading a bit out of a core is placed physically in parallel with the bit line driven by half select current to approximate in the unused line the capacitive and inductive coupling of the driven line with the word drive line. That coupling produces in the unused line the same noise (crosstalk) produced in the driven bit line by the word drive pulse. The crosstalk signal in the unused line is subtracted from the signal in the driven bit line before amplification and detection. The unused line may be a separate dummy line, or simply another bit line not being used for the bit being read out. In the case of paired bit lines used for common mode rejection of the bit drive signal, a second pair of unused bit lines is arranged in parallel for crosstalk cancellation.

Abstract: A processor controlled postage meter includes memories for storage of meter account balance data. Thermal security of the balance data is maintained through the employment of magnetic core memories constructed to withstand high temperatures which may be generated during a fire at the location of the meter. The magnetic core memory includes a matrix of toroids arranged in a plane and encased within ceramic cement for thermal insulation. The toroids are preferably formed of a non-oxidized pure metal magnetic alloy having a Curie temperature of at least 650 degrees Celsius.

Abstract: A ferrite core memory in the form of a hollow plait of ferrite matrices. ferrite matrices comprise ferrite cores interwoven with coordinate wires and wires forming readout and inhibition windings. The hollow plait consists of alternating squares of ferrite matrices connected at their edges and formed into a hollow cylindrical plait. The diagonal lines of the matrices extend axially and transversely of the plait. The coordinate wires interweaving the ferrite cores extend along orthogonally intersecting helical lines lying on the cylindrical surface of the plait. The outgoing leads of the readout and inhibition windings are distributed longitudinally along the plait.

Abstract: A large, 2 wire, 21/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Writing is accomplished in two sub-operations by separately controlling partial select digit currents in each of the 5 pairs of Y conductors. A bidirectional X drive and switching arrangement utilizes overlapping X drive currents and shared circuitry to maximize memory speed and reduce electronic components costs.

Abstract: A large, 2 wire, 21/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid sucession read sub-operations. Writing is accomplished in two sub-operations by separately controlling partial select digit currents in each of the 5 pairs of Y conductors. A bidirectional X drive and switching arrangement utilizes overlapping X drive currents and shared circuitry to maximize memory speed and reduce electronic components costs.