Ferroelectric Patents (Class 365/145)
  • Patent number: 11329099
    Abstract: A magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in a second area of the chip. For example, the first set of magnetic random access memory elements can have performance characteristics that match or exceed those of a non-volatile memory, whereas the second set of magnetic random access memory elements can have performance characteristic that match or exceed those of a static random access memory element.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz, Thomas D. Boone
  • Patent number: 11322191
    Abstract: A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11309034
    Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 19, 2022
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventors: Menno Mennenga, Johannes Ocker
  • Patent number: 11309036
    Abstract: Systems and methods that may be implemented for that may be implemented to compensate for NAND flash memory voltage threshold (Vth) shift by using one or more designated calibration wordlines that are programmed into the NAND flash memory with a pre-defined data pattern. In one example configuration, the disclosed systems and methods may be automatically implemented by a SSD controller when needed to compensate for flash memory voltage threshold (Vth) shift that occurs, e.g., due to NAND memory cell charge loss due to power-off data retention over an extended period of time.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 19, 2022
    Assignee: Dell Products L.P.
    Inventors: Chai Im Teoh, Lip Vui Kan
  • Patent number: 11296186
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Patent number: 11295813
    Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 5, 2022
    Assignee: Zeno Semiconductor Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11295797
    Abstract: Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Angelo Visconti
  • Patent number: 11282572
    Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11276449
    Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney
  • Patent number: 11270740
    Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kyoichi Nagata
  • Patent number: 11264074
    Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 11257865
    Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 22, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yasuhiro Tomita, Chi Shun Lin
  • Patent number: 11250900
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11244999
    Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Patent number: 11244960
    Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Kun Young Lee, Sun Young Kim, Jae Gil Lee
  • Patent number: 11239361
    Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Joshua M. Howard, Seiyon Kim, Ian A. Young
  • Patent number: 11238907
    Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo
  • Patent number: 11238913
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura
  • Patent number: 11232823
    Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi
  • Patent number: 11231992
    Abstract: A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region, and a memory controller configured to store data to be stored in a plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundancy word line to which a plurality of redundancy memory cells among the plurality of memory cells are connected in response to a correctable error correction code (CECC) occurring in at least one of the plurality of selected memory cells.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhoon Park, Dong Kim, Hyunglae Eun, Chulseung Lim, Wonyeoung Jung
  • Patent number: 11222958
    Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Patent number: 11222668
    Abstract: Methods, systems, and devices for memory cell sensing stress mitigation are described. A memory device may be configured to bias a memory cell to a voltage with a first polarity or a second polarity (e.g., a positive voltage or a negative voltage) during an access operation to level wear experienced by the memory cell during the access operation. For example, during a first read operation, a first pulse with the first polarity (e.g., a negative voltage) may be applied to the memory cell to read out a first logic state stored at the memory cell. During a second read operation, a second pulse with the second polarity (e.g., a positive voltage) may be applied to the memory cell to read out a second logic state stored at the memory cell. The memory device may include a selection component for selecting between the different pulses used for different read operations.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Duane R. Mills, Richard E. Fackenthal, Yasuko Hattori
  • Patent number: 11211109
    Abstract: Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 11211550
    Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 28, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bin Liu, Eng Huat Toh, Samarth Agarwal, Ruchil Kumar Jain, Kiok Boone Elgin Quek
  • Patent number: 11205468
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 11195592
    Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 7, 2021
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: PaiLu Dennis Wang, Lien-Sheng Yang
  • Patent number: 11189330
    Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Visconti, Andrea Locatelli, Giorgio Servalli
  • Patent number: 11189331
    Abstract: A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 30, 2021
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventors: Antoine Benoist, Marko Noack
  • Patent number: 11176047
    Abstract: A data storage system comprises physical storage, cache memory and a processor connected to the physical storage and the cache memory. The processor is arranged to maintain a set of active regions in the cache memory, each active region having a size equal to an integer multiple of an update size of a flash chip within the physical storage, where the integer could be 1. The processor receives requests for one or more blocks of the cache memory from components within the storage system and allocates one or more blocks from an active region in response to a received request. If the processor determines that all blocks in an active region have been allocated and that all allocated blocks within this region have been written to, then the processor destages the content of this region to the physical storage.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Miles Mulholland, Lee J. Sanders, Ben Sasson, William J. Scales
  • Patent number: 11164889
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Patent number: 11158361
    Abstract: A memory cell arrangement is provided that may include: a plurality of memory cells including one or more memory cells to be read out and one or more memory cells not to be read out; a control circuit defining a base voltage and configured to: apply a select voltage, a first readout voltage and a second readout voltage, to one word-line and to a source/bit-line pair corresponding to the one or more memory cells to be read out, respectively; apply a voltage that is substantially the base voltage to one or more word-lines corresponding to the one or more memory cells not to be read out; wherein both the first readout voltage and the second readout voltage are provided with an offset to the base voltage, and wherein the first readout voltage and the second readout voltage are different from one another.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: October 26, 2021
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Stefan Müller
  • Patent number: 11156678
    Abstract: A magnetic field sensor based on two anti-ferromagnetically coupled magnetic layers separated by multilayer graphene, prepared in a single sputter chamber without a vacuum break.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 26, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van't Erve, Enrique Cobas, Shu-Fan Cheng, Berend T. Jonker
  • Patent number: 11158362
    Abstract: Each pre-sense amplifier produces, in a read operation, an output potential obtained by resistively dividing a power supply voltage based on a potential of one of two first bit lines or one of a plurality of second bit lines. The two first bit lines are connected to a first memory cell holding data of a first and a second logic values. The second bit lines are individually connected to one of a plurality of second memory cells each holding data of the first or the second logic value. Each twin sense amplifier outputs, in the read operation, data determination results based on two reference potentials and a data potential. The two reference potentials are the output potentials produced based on the potentials of the two first bit lines. The data potential is the output potential produced based on the potential of one of the second bit lines.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 26, 2021
    Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
    Inventor: Hiroshi Yoshioka
  • Patent number: 11152049
    Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 11145664
    Abstract: Disclosed is an integrated circuit for ferroelectric memory, the integrated circuit comprising: a ferroelectric memory array having a storage unit array formed on a ferroelectric single-crystal layer, wherein each ferroelectric memory unit in the ferroelectric memory array is at least formed by one storage unit in the storage unit array, or at least formed by one storage unit in the storage unit array and one transistor formed on a silicon substrate of a silicon-based reading and writing circuit that is electrically connected to the storage unit.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 12, 2021
    Assignee: Fudan University
    Inventors: Anquan Jiang, Yan Zhang, Zilong Bai
  • Patent number: 11145336
    Abstract: A method comprising receiving, at a memory sub-system from a host system, configuration parameters associated with usage of the memory sub-system, monitoring environmental parameters of the memory sub-system, wherein the environmental parameters comprise characteristics of the memory sub-system and an environment of the memory sub-system, and selecting values for program pulse characteristics of the memory sub-system based on the configuration parameters and environmental parameters, the program pulse characteristics comprising at least a program pulse voltage.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 12, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Christopher J. Bueb, Poorna Kale
  • Patent number: 11137917
    Abstract: A memory system includes a memory controller. The memory controller includes a program history manager for managing a program history of a first memory unit including a plurality of sub-units of which write protection mode is set; and a memory unit manager for selecting, based on the program history, at least one sub-unit on which a program operation is not performed during a set period among the plurality of sub-units, and releasing the write protection mode of the at least one selected sub-unit.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Hui Won Lee
  • Patent number: 11139310
    Abstract: To provide a semiconductor memory device that avoids a voltage drop caused by an oxide film formed on a surface of a semiconductor substrate, and appropriately operates even in a case where a memory cell array is formed. A semiconductor memory device including a first transistor, a capacitor provided with a pair of capacitor electrodes opposed to each other via an insulator, one of the capacitor electrodes being electrically coupled to a gate electrode of the first transistor, a second transistor in which one of a source or a drain is electrically coupled to one of a source or a drain of the first transistor and to another of the capacitor electrodes, and a plate line electrically coupled to the gate electrode of the first transistor and to the one of the capacitor electrodes.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 5, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Masanori Tsukamoto
  • Patent number: 11133047
    Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xinwei Guo, Daniele Vimercati
  • Patent number: 11133048
    Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xinwei Guo, Daniele Vimercati
  • Patent number: 11133329
    Abstract: A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 28, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 11127436
    Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jiyun Li
  • Patent number: 11120859
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11120872
    Abstract: A resistive memory device includes a memory cell array of resistive memory cells connected to word and bit lines, each bay of the memory cell array including K tiles; a write/read circuit connected to the memory cell array through a row decoder and a column decoder, the write/read circuit being configured to perform a write operation in a target tile of the memory cell array, the write/read circuit comprising write drivers corresponding to the bays; a control voltage generator configured to generate first and second control voltages based on a reference current; and a control circuit configured to control the write/read circuit and the control voltage generator. A first write driver that corresponds to a first bay of the bays is configured to provide the target tile with a write current corresponding to a physical position of a selected memory cell of the target tile in the memory cell array.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungyu Lee, Bilal Ahmad Janjua
  • Patent number: 11114149
    Abstract: Embodiments of operation methods of ferroelectric memory are disclosed. In an example, a method for reading ferroelectric memory cells is disclosed. The ferroelectric memory cells include a first set of ferroelectric memory cells and a second set of ferroelectric memory cells. In a first cycle, first data in a first ferroelectric memory cell of the first set of ferroelectric memory cells is sensed. In a second cycle subsequent to the first cycle, the sensed first data is written back to the first ferroelectric memory cell, and second data in a second ferroelectric memory cell of the second set of ferroelectric memory cells is simultaneously sensed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 7, 2021
    Assignee: WUXI PETABYTE TECHNOLOGIES CO, LTD.
    Inventor: Feng Pan
  • Patent number: 11114156
    Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Josephine Tiu Hamada, Kenneth Richard Surdyk, Lingming Yang, Mingdong Cui
  • Patent number: 11114465
    Abstract: A memory device, including: memory cells, first conductive lines, second conductive lines, third conductive lines and fourth conductive lines. The memory cells are arranged in an array. Each memory cell includes a transistor and a capacitor connected to a gate terminal of the transistor in series. The first conductive lines extend in a first direction. Each first conductive line connects to gate terminals of transistors arranged in same column in the array. The second conductive lines extend in the first direction. Each second conductive line connects to source terminals of transistors arranged in same column in the array. The third conductive lines extend in the first direction. Each third conductive line connects to drain terminals of transistors arranged in same column in the array. The fourth conductive lines extend in a second direction. Each fourth conductive line couples to the capacitor arranged in same row in the array.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nuo Xu, Zhiqiang Wu
  • Patent number: 11114147
    Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo
  • Patent number: 11107835
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • Patent number: 11107515
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura