Abstract: A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises detecting a transition associated with the memory device from a first power state to a second power state, responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency, and performing one or more block family calibration operations.

Abstract: A differential sensing device includes two reference cells, four path selectors, and four sample circuits. The first path selector is coupled to a first sensing node, the second reference cell, and a first memory cell. The second path selector is coupled to a second sensing node, the first reference cell, and the first memory cell. The third path selector is coupled to a third sensing node, the first reference cell, and a second memory cell. The fourth path selector is coupled to a fourth sensing node, the second reference cell, and the second memory cell. During a sample operation, the first sample circuit samples a first cell current, the second sample circuit samples the first reference current, the third sample circuit samples a second cell current, and the fourth sample circuit samples the second reference current.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: Provided are a weight matrix circuit and a weight matrix input circuit. The weight matrix circuit includes a memory array including n input lines, m output lines, and n×m resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic, an input circuit connected to each of the input lines, and an output circuit connected to each of the output lines. The input circuit is connected to the resistive memory devices such that the weight matrix circuit has a linear current-voltage characteristic.

Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Abstract: An IC structure includes a first FinFET including a first plurality of gate structures overlying a first plurality of fin structures, a second FinFET including a second plurality of gate structures overlying a second plurality of fin structures, and an eFuse including a conductive element positioned between the first and second pluralities of gate structures. The conductive element of the eFuse includes a first contact region electrically connected to each of the first and second pluralities of fin structures.

Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

Abstract: The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.

Abstract: A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.

Abstract: A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

Abstract: Tapered resistive memory devices with interface dipoles are provided. In one aspect, a ReRAM device includes: a bottom electrode; a core dielectric that is thermally conductive disposed on the bottom electrode; an oxide resistive memory cell disposed along outer sidewalls of the core dielectric, wherein the oxide resistive memory cell has inner edges adjacent to the core dielectric, and outer edges that are tapered; an outer coating disposed adjacent to the outer edges of the oxide resistive memory cell; and a top electrode disposed on the core dielectric, the oxide resistive memory cell, and the outer coating. A method of forming a ReRAM device as well as a method of operating a ReRAM device are also provided.

Abstract: A memory device includes a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal that regulates the generating of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.

Abstract: A computer-implemented method for suppressing outlier drift of a phase change memory (PCM) device includes programming, by a controller, a conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first time-point, the first time-point being a programming time-point. The programming further includes determining, at a first pre-compensation time-point, that the conductance of the PCM device has changed to a second conductance value that differs from a target conductance value by no more than a predetermined threshold. Further, the programming includes, based on the above determination, reprogramming the PCM device to the first conductance value at a second time-point, including measuring said pre-compensation again, but at a second pre-compensation time-point.

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: Technology for operating cross-bar arrays is disclosed herein. The memory cells may each have a reversible resistivity element and a steering element comprising a diode. The cross-bar array may be operated in read mode and a bipolar programming mode. Selected memory cells may be sensed by operating the steering elements such that sense currents pass through the diodes and any sneak currents are blocked by the diodes. During bipolar programming of selected memory cells, the steering element of the selected memory cells allows current to flow in either direction through the steering element to permit bipolar programming. In some aspects, the steering element has a switch in parallel with the diode. The switches may be opened when sensing selected memory cells to pass sense currents and block sneak currents with the diodes. The switches may be closed during bipolar programming of the selected memory cells to allow bi-directional current flow.

Abstract: A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.

Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.

Abstract: A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state.

Abstract: A magnetic memory including a first spin-orbital-transfer-spin-torque-transfer (SOT-SIT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

Abstract: A selector device for a memory cell in a memory array includes a first electrode, a second electrode, and a separator between the first electrode and the second electrode. The separator includes a mixed ionic-electronic conduction material with first ions having a first charge such that the first ions respond to a voltage applied between the first electrode and the second electrode by moving away from the first electrode. The separator is doped near the second electrode with second ions having a second charge that opposes the first charge.

Abstract: A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.

Abstract: A non-volatile memory device and a method for programming a non-volatile memory device are provided. The non-volatile memory device includes a memory array and a memory controller. The memory array includes a plurality of memory cells. The memory controller is configured to regulate a programming operation by applying a program pulse generated according to a set pulse and a reset pulse to each of the memory cells. The memory controller determines whether a memory cell resistance of each of the memory cells is within a target range and apply the program pulse to each of the memory cells until the memory cell resistances of all of the memory cells are within the target range.

Abstract: A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

Abstract: A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.

Abstract: A computing device and method are provided. The computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-period lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the levels of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charge or discharge the conductive line to a voltage indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum.

Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate including a first area, a second area, and a third area, the second and the third areas being adjacent to the first area; a first insulating layer disposed in the first to the third areas; a first wiring disposed on a surface of the first insulating layer in the first area; a first memory cell disposed on the first wiring; a second wiring disposed on the first memory cell; and a contact connected to the second wiring in the second area. The surface of the first insulating layer includes: first surfaces disposed in at least one of the second area and the third area and arranged in the first direction; and second surfaces disposed between the first surfaces. The second surfaces are close to or far from the substrate compared with the first surfaces.

Abstract: According to one embodiment, a memory device includes a resistance change memory element including a first electrode, a second electrode, and an intermediate layer provided between the first electrode and the second electrode, containing germanium (Ge), tellurium (Te) and at least one element selected from lithium (Li) and sodium (Na), and at least a part of which being capable of exhibiting a crystalline state.

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

Abstract: The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

Abstract: Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).

Abstract: A method, apparatus and system. The method includes: generating, during a read operation of a memory cell, a mirror current iMir1 at one of a WL node or a BL node of the memory cell opposite, respectively, one of a BL side or a WL side of the memory cell to which a current mode sense circuitry is connected, the iMir1 to reduce a value of the read voltage from VDM1 to VDM2, wherein the read voltage is between the WL node and the BL node; and sensing, using the current mode sense circuitry, a logic state of the memory cell at VDM2.

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Abstract: Methods are disclosed herein for controlling the switching characteristics of correlated electron material (CEM) switching devices. The methods comprise one or more of controlling a density of grain boundaries in the CEM layer, controlling an open pore porosity in the CEM layer and controlling a surface area of exposed surfaces of the CEM layer during the fabrication of the CEM switching devices.

Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.

Abstract: The present invention is directed to a memory cell array comprising an array of magnetic memory elements arranged in rows and columns; a plurality of electrodes, each of which is formed adjacent to a respective one of the array of magnetic memory elements; a plurality of first conductive lines, each of which is connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines. Each composite line includes a volatile switching layer connected to a respective column of the plurality of electrodes along a column direction; an electrode layer formed adjacent to the volatile switching layer; and a second conductive line formed adjacent to the electrode layer. The dimension of the volatile switching layer may be substantially larger than the size of the magnetic memory element along the row direction.

Abstract: A three-dimensional stacked phase change memory and a preparation method thereof are provided. The method comprises: preparing first horizontal electrodes spaced apart from each other on a substrate; preparing first strip-shaped phase change layers, each having a central gap, between the first horizontal electrodes; preparing first selectors in the central gaps of the first strip-shaped phase change layers; preparing a first insulating layer; preparing second strip-shaped phase change layers at same vertical positions on the first insulating layer; preparing second selectors; then preparing horizontally-oriented insulating holes between the horizontal electrodes; and preparing vertical electrodes between the adjacent insulating holes, thereby forming a multilayer stacked phase change memory with a vertical structure.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.

Abstract: According to one embodiment, a detection device includes a substrate, a drive electrode provided on the substrate, a detection electrode provided on the substrate and capacitively coupling with the drive electrode, and a first thin film transistor and a second thin film transistor, electrically connected to the drive electrode, and the first thin film transistor has a withstand voltage higher than a withstand voltage of the second thin film transistor.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell array of a plurality of memory cells each including a variable resistance element and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element; a driving control circuit operable to control a reference data to be written in a selected memory cell among the memory cells, during a sensing operation; a resistance monitoring circuit operable to receive the cell voltage of the selected memory cell and output a monitoring voltage based on the cell voltage at the bit line, the monitoring voltage corresponding to a change in the resistance value during the sensing operation; and an amplifying circuit operable to amplify the monitoring voltage and output an amplified monitoring voltage as output data.

Abstract: Technologies relating to controlling forming process in RRAM devices implemented in a cross-bar circuit using one or more feedback circuits are disclosed. An example apparatus includes an RRAM cell configured to form a channel; a MOSFET having a drain terminal, a source terminal, and a gate terminal, wherein the MOSFET is connected to the RRAM cell via the drain terminal; a TIA connected to the MOSFET via the source terminal; a first signal generator connected to the RRAM cell; a second signal generator connected to the MOSFET via the gate terminal; and a comparator having a first input end, a second input end, and an output end, wherein the comparator is connected to the TIA via the first input end, the second input end is connected to a reference voltage source, and the output end is connected to the first signal generator and the second signal generator.

Abstract: Technologies relating to crossbar array circuits with nTnR design to reduce sneak current path and minimize area size are disclosed. An example crossbar array circuit includes: a first transistor comprising a first source terminal, a first drain terminal and a first gate terminal; a first RRAM device connected to the first source terminal of the first transistor; a second transistor comprising a second source terminal, a second drain terminal and a second gate terminal; a second RRAM device connected to the second source terminal of the second transistor; a word line connected to the first drain terminal of the first transistor and the second drain terminal of the second transistor; a first bit line connected to the first RRAM device; and a second bit line connected to the second RRAM device, wherein the first gate terminal of the first transistor is configured to be connected to a first selective voltage source, and the second gate terminal is configured to be connected to a second selective voltage source.

Abstract: A magnetic memory according to one embodiment of the present invention comprises: a magnetic tunnel junction comprising a free layer, a reference layer, and a tunnel barrier layer disposed between the free layer and the reference layer; a first conductive line disposed adjacent to the free layer; and a second conductive line disposed adjacent to the free layer and intersecting the first conductive line. A magnetization switching method of the magnetic memory comprises the steps of: applying an alternating current-type first current having a first frequency to the first conductive line; and applying an alternating current-type second current having the first frequency to the second conductive line. The free layer performs magnetization reversal, using the first current and the second current, and the magnetic tunnel junction is disposed on an intersection point between the first conductive line and the second conductive line.