Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Abstract: An RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.

Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: Disclosed herein is a compound of formula (I): [M(L)n]m+(Ay?)z??(I) where A, M, L, n, m, y and z are as defined herein, which can be used in the formation of a resistive memory device. Also disclosed herein are methods of manufacturing such devices and their uses.

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Abstract: A method for controlling a resistive random access memory (ReRAM) is proposed. The method calculates a number of a bit value of a data when the data is to be written to the resistive random access memory. Each bit of the data is flipped and the data is written to the ReRAM if the number of the bit value is greater than a half of a length of the data. The data as it original is written to the ReRAM if the number of the bit value is less than a half of the length of the data.

Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

Abstract: Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.

Abstract: Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.

Abstract: A resistive memory includes an array area where memory cells are arranged in rows and columns, word lines connected to the memory cells in a row direction, a local bit line extending in a column direction, local source lines, a shared bit line, and a writing device. Each memory cell includes a variable resistance element and an accessing transistor. The local source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line and second electrodes of the memory cells in the row direction. The writing device pre-charges the bit line and the source lines to a first voltage and applies a write pulse to the selected memory cell by discharging the corresponding selected source line after applying a write voltage to the selected word line, the writing device.

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.

Abstract: Briefly, the disclosure relates to circuits utilized to perform writing operations to a memory array, in which elements of the array comprise resistive memory cells coupled in series with an access device. In one embodiment, a circuit may comprise a supply voltage coupled to a first side of the array and a current source coupled to a second side of the array. The access devices of the elements of the array may be body-biased, which may operate to reduce the turn-on voltage (VTH) of the access devices. Particular voltages may be applied to gate regions of the access devices to control leakage current to the resistive memory cells of the array.

Abstract: A semiconductor memory device includes a memory cell array and bit lines connected to the memory cell array. The semiconductor memory device also includes a first upper line and a second upper line which overlap with the bit lines and are spaced apart from the bit lines by different distances.

Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.

Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.

Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.

Abstract: A semiconductor storage device is provided, the semiconductor storage device including: a resistance element configured to generate a reference potential to be supplied to a sense amplifier; and a switch unit having at least two states including a state in which the reference potential to be supplied to the sense amplifier is generated by injection of a current to the resistance element, and a state in which a reference potential generated outside the semiconductor storage device is supplied to the sense amplifier.

Abstract: A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias.

Abstract: Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer.

Abstract: The disclosure is directed to a method and an apparatus for verifying an operation performed by a cell of a RRAM. In an aspect of the disclosure, the method of verifying an operation performed by a cell of a RRAM would include not limited to performing a first write operation by applying a first write voltage on a cell of the RRAM; measuring a first resistance and a first rate of change of the resistance of the cell; detecting whether the first rate of change of the resistance is below a negative change of resistance threshold; detecting whether the first resistance is below a target resistance value in response to having detected that the first rate of change of the resistance is below the negative change of resistance threshold; and having determined the cell is valid in response to having detected the first resistance dropping below the target resistance value.

Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, and a controller coupled to the plurality of memory cells. The controller of the example apparatus may be configured to apply a first signal to the first access line, and while the first signal is being applied to the first access line, apply a second signal to a first of the plurality of memory cells via another respective one of the plurality of second access lines and apply a third signal to a second of the plurality of memory cells via another respective one of the plurality of second access lines. The material implication operation may be performed as a result of the signals (e.g.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.

Abstract: A method for forming a CoFeSiB—Pd alloy thin film exhibiting perpendicular magnetic anisotropy includes: simultaneously sputtering a CoFeSiB target and a Pd target inside a vacuum chamber to form a CoFeSiB—Pd alloy thin film on a substrate disposed inside the vacuum chamber; and annealing the substrate, on which the CoFeSiB—Pd alloy thin film is formed, to exhibit perpendicular magnetic anisotropy.

Abstract: Provided is a method for reading a current for processing analog information in a memory array for a synaptic device. To this end, the method for reading the memory array including a two-terminal switching material, comprises (a) selecting at least one cell by applying a voltage to the memory array, and (b) simultaneously measuring the sum of currents from the at least one cell selected. The voltage applied to the at least one cell selected in operation (a) is higher than a voltage applied to at least one cell not selected while being within a range in which all of the selected at least one cell is not turned on.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Abstract: Embodiments of the present disclosure provide a memcapacitor, a programming method for a memcapacitor and a capacitive random access memory. The memcapacitor includes: a source electrode made of a metal material; a first dielectric layer disposed at an outer side of the source electrode in a horizontal direction; a programming electrode disposed at an outer side of the first dielectric layer in the horizontal direction; a second dielectric layer disposed at an upper surface of the source electrode and an upper surface of the first dielectric layer; and a reading electrode disposed at an upper surface of the second dielectric layer, where the reading electrode, the second dielectric layer and the source electrode form a capacitor.

Abstract: A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

Abstract: A solution for using elementary electrochemical components, manufactured from the same arrangement of materials and incorporated in a single electronic circuit, for information storage or for energy storage, is presented. Electrochemical components incorporating a first electrode, a second electrode and an active area between the two, can, by the application of different voltages for switching from a highly resistive state to a weakly resistive state or for switching from a state having one given electromotive force to a state having another electromotive force, be used respectively as a memory or as a battery.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.

Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

Abstract: In some embodiments, the present disclosure relates to a method of operating a phase change memory cell, which includes writing a first data state and a second data state to the phase change memory cell. To write the first data state, a phase change material (PCM) is heated to a melting point of the PCM, and then cooled to an ambient temperature below the melting point of the PCM over a first predetermined time period, thereby solidifying the PCM to correspond to the first data state. To write the second data state, the PCM is heated to the melting point of the PCM, and then cooled to the ambient temperature over a second predetermined cooling time period, thereby solidifying the PCM to correspond to the second data state. The second predetermined cooling time period differs from the first predetermined time period.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.